482 lines
13 KiB
C#
482 lines
13 KiB
C#
//////////////////////////////////////////////////////////////////////////
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// Mapper090 PC-JY-?? //
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//////////////////////////////////////////////////////////////////////////
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using VirtualNes.Core.Debug;
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using static VirtualNes.Core.CPU;
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using static VirtualNes.MMU;
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using BYTE = System.Byte;
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using INT = System.Int32;
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namespace VirtualNes.Core
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{
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public class Mapper090 : Mapper
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{
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BYTE patch;
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BYTE[] prg_reg = new byte[4];
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BYTE[] nth_reg = new byte[4];
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BYTE[] ntl_reg = new byte[4];
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BYTE[] chh_reg = new byte[8];
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BYTE[] chl_reg = new byte[8];
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BYTE irq_enable;
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BYTE irq_counter;
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BYTE irq_latch;
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BYTE irq_occur;
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BYTE irq_preset;
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BYTE irq_offset;
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BYTE prg_6000, prg_E000;
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BYTE prg_size, chr_size;
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BYTE mir_mode, mir_type;
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BYTE key_val;
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BYTE mul_val1, mul_val2;
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BYTE sw_val;
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public Mapper090(NES parent) : base(parent)
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{
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}
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public override void Reset()
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{
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SetPROM_32K_Bank(PROM_8K_SIZE - 4, PROM_8K_SIZE - 3, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
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SetVROM_8K_Bank(0);
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patch = 0;
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uint crc = nes.rom.GetPROM_CRC();
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if (crc == 0x2a268152)
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{
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patch = 1;
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}
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if (crc == 0x2224b882)
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{
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nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER);
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}
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irq_enable = 0; // Disable
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irq_counter = 0;
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irq_latch = 0;
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irq_occur = 0;
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irq_preset = 0;
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irq_offset = 0;
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prg_6000 = 0;
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prg_E000 = 0;
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prg_size = 0;
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chr_size = 0;
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mir_mode = 0;
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mir_type = 0;
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key_val = 0;
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mul_val1 = mul_val2 = 0;
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for (byte i = 0; i < 4; i++)
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{
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prg_reg[i] = (byte)(PROM_8K_SIZE - 4 + i);
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ntl_reg[i] = 0;
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nth_reg[i] = 0;
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chl_reg[i] = i;
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chh_reg[i] = 0;
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chl_reg[i + 4] = (byte)(i + 4);
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chh_reg[i + 4] = 0;
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}
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if (sw_val != 0)
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sw_val = 0x00;
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else
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sw_val = 0xFF;
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// nes.SetRenderMethod( NES::PRE_ALL_RENDER );
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}
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//BYTE Mapper090::ReadLow(WORD addr)
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public override byte ReadLow(ushort addr)
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{
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Debuger.Log($"RD:{addr:X4}");
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switch (addr)
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{
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case 0x5000:
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return (byte)((sw_val != 0) ? 0x00 : 0xFF);
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case 0x5800:
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return (BYTE)(mul_val1 * mul_val2);
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case 0x5801:
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return (BYTE)((mul_val1 * mul_val2) >> 8);
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case 0x5803:
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return key_val;
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}
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if (addr >= 0x6000)
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{
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return base.ReadLow(addr);
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}
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// return sw_val?0x00:0xFF;
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return (BYTE)(addr >> 8);
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}
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//void Mapper090::WriteLow(WORD addr, BYTE data)
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public override void WriteLow(ushort addr, byte data)
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{
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Debuger.Log($"WR:{addr:X4} {data:X2}");
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if (addr == 0x5800)
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{
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mul_val1 = data;
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}
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else
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if (addr == 0x5801)
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{
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mul_val2 = data;
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}
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else
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if (addr == 0x5803)
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{
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key_val = data;
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}
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}
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//void Mapper090::Write(WORD addr, BYTE data)
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public override void Write(ushort addr, byte data)
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{
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switch (addr & 0xF007)
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{
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case 0x8000:
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case 0x8001:
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case 0x8002:
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case 0x8003:
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prg_reg[addr & 3] = data;
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SetBank_CPU();
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break;
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case 0x9000:
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case 0x9001:
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case 0x9002:
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case 0x9003:
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case 0x9004:
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case 0x9005:
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case 0x9006:
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case 0x9007:
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chl_reg[addr & 7] = data;
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SetBank_PPU();
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break;
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case 0xA000:
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case 0xA001:
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case 0xA002:
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case 0xA003:
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case 0xA004:
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case 0xA005:
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case 0xA006:
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case 0xA007:
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chh_reg[addr & 7] = data;
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SetBank_PPU();
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break;
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case 0xB000:
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case 0xB001:
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case 0xB002:
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case 0xB003:
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ntl_reg[addr & 3] = data;
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SetBank_VRAM();
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break;
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case 0xB004:
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case 0xB005:
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case 0xB006:
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case 0xB007:
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nth_reg[addr & 3] = data;
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SetBank_VRAM();
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break;
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case 0xC002:
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irq_enable = 0;
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irq_occur = 0;
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nes.cpu.ClrIRQ(IRQ_MAPPER);
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break;
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case 0xC003:
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irq_enable = 0xFF;
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irq_preset = 0xFF;
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break;
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case 0xC004:
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break;
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case 0xC005:
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if ((irq_offset & 0x80) != 0)
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{
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irq_latch = (byte)(data ^ (irq_offset | 1));
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}
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else
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{
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irq_latch = (byte)(data | (irq_offset & 0x27));
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}
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irq_preset = 0xFF;
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break;
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case 0xC006:
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if (patch != 0)
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{
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irq_offset = data;
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}
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break;
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case 0xD000:
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prg_6000 = (byte)(data & 0x80);
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prg_E000 = (byte)(data & 0x04);
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prg_size = (byte)(data & 0x03);
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chr_size = (byte)((data & 0x18) >> 3);
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mir_mode = (byte)(data & 0x20);
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SetBank_CPU();
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SetBank_PPU();
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SetBank_VRAM();
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break;
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case 0xD001:
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mir_type = (byte)(data & 0x03);
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SetBank_VRAM();
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break;
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case 0xD003:
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break;
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}
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}
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//void Mapper090::HSync(INT scanline)
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public override void HSync(int scanline)
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{
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if ((scanline >= 0 && scanline <= 239))
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{
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if (nes.ppu.IsDispON())
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{
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if (irq_preset != 0)
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{
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irq_counter = irq_latch;
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irq_preset = 0;
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}
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if (irq_counter != 0)
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{
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irq_counter--;
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}
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if (irq_counter == 0)
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{
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if (irq_enable != 0)
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{
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// irq_occur = 0xFF;
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nes.cpu.SetIRQ(IRQ_MAPPER);
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}
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}
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}
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}
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}
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//void Mapper090::Clock(INT cycles)
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public override void Clock(int cycles)
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{
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// if( irq_occur ) {
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// nes.cpu.IRQ_NotPending();
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// }
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}
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void SetBank_CPU()
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{
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if (prg_size == 0)
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{
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SetPROM_32K_Bank(PROM_8K_SIZE - 4, PROM_8K_SIZE - 3, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
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}
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else
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if (prg_size == 1)
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{
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SetPROM_32K_Bank(prg_reg[1] * 2, prg_reg[1] * 2 + 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
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}
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else
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if (prg_size == 2)
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{
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if (prg_E000 != 0)
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{
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SetPROM_32K_Bank(prg_reg[0], prg_reg[1], prg_reg[2], prg_reg[3]);
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}
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else
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{
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if (prg_6000 != 0)
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{
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SetPROM_8K_Bank(3, prg_reg[3]);
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}
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SetPROM_32K_Bank(prg_reg[0], prg_reg[1], prg_reg[2], PROM_8K_SIZE - 1);
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}
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}
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else
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{
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SetPROM_32K_Bank(prg_reg[3], prg_reg[2], prg_reg[1], prg_reg[0]);
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}
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}
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void SetBank_PPU()
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{
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INT[] bank = new int[8];
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for (INT i = 0; i < 8; i++)
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{
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bank[i] = ((INT)chh_reg[i] << 8) | ((INT)chl_reg[i]);
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}
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if (chr_size == 0)
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{
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SetVROM_8K_Bank(bank[0]);
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}
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else
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if (chr_size == 1)
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{
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SetVROM_4K_Bank(0, bank[0]);
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SetVROM_4K_Bank(4, bank[4]);
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}
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else
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if (chr_size == 2)
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{
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SetVROM_2K_Bank(0, bank[0]);
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SetVROM_2K_Bank(2, bank[2]);
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SetVROM_2K_Bank(4, bank[4]);
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SetVROM_2K_Bank(6, bank[6]);
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}
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else
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{
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SetVROM_8K_Bank(bank[0], bank[1], bank[2], bank[3], bank[4], bank[5], bank[6], bank[7]);
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}
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}
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void SetBank_VRAM()
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{
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INT[] bank = new int[4];
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for (INT i = 0; i < 4; i++)
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{
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bank[i] = ((INT)nth_reg[i] << 8) | ((INT)ntl_reg[i]);
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}
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if (patch == 0 && mir_mode != 0)
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{
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for (INT i = 0; i < 4; i++)
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{
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if (nth_reg[i] == 0 && (ntl_reg[i] == (BYTE)i))
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{
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mir_mode = 0;
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}
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}
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if (mir_mode != 0)
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{
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SetVROM_1K_Bank(8, bank[0]);
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SetVROM_1K_Bank(9, bank[1]);
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SetVROM_1K_Bank(10, bank[2]);
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SetVROM_1K_Bank(11, bank[3]);
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}
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}
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else
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{
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if (mir_type == 0)
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{
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SetVRAM_Mirror(VRAM_VMIRROR);
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}
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else
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if (mir_type == 1)
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{
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SetVRAM_Mirror(VRAM_HMIRROR);
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}
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else
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{
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SetVRAM_Mirror(VRAM_MIRROR4L);
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}
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}
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}
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//void Mapper090::SaveState(LPBYTE p)
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public override void SaveState(byte[] p)
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{
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INT i;
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for (i = 0; i < 4; i++)
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{
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p[i] = prg_reg[i];
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}
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for (i = 0; i < 8; i++)
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{
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p[i + 4] = chh_reg[i];
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}
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for (i = 0; i < 8; i++)
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{
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p[i + 12] = chl_reg[i];
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}
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for (i = 0; i < 4; i++)
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{
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p[i + 20] = nth_reg[i];
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}
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for (i = 0; i < 4; i++)
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{
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p[i + 24] = ntl_reg[i];
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}
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p[28] = irq_enable;
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p[29] = irq_counter;
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p[30] = irq_latch;
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p[31] = prg_6000;
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p[32] = prg_E000;
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p[33] = prg_size;
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p[34] = chr_size;
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p[35] = mir_mode;
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p[36] = mir_type;
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p[37] = mul_val1;
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p[38] = mul_val2;
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p[39] = key_val;
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p[40] = irq_occur;
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p[41] = irq_preset;
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p[42] = irq_offset;
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}
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//void Mapper090::LoadState(LPBYTE p)
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public override void LoadState(byte[] p)
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{
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INT i;
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for (i = 0; i < 4; i++)
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{
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prg_reg[i] = p[i];
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}
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for (i = 0; i < 8; i++)
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{
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chh_reg[i] = p[i + 4];
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}
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for (i = 0; i < 8; i++)
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{
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chl_reg[i] = p[i + 12];
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}
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for (i = 0; i < 4; i++)
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{
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nth_reg[i] = p[i + 20];
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}
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for (i = 0; i < 4; i++)
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{
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ntl_reg[i] = p[i + 24];
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}
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irq_enable = p[28];
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irq_counter = p[29];
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irq_latch = p[30];
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prg_6000 = p[31];
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prg_E000 = p[32];
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prg_size = p[33];
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chr_size = p[34];
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mir_mode = p[35];
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mir_type = p[36];
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mul_val1 = p[37];
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mul_val2 = p[38];
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key_val = p[39];
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irq_occur = p[40];
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irq_preset = p[41];
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irq_offset = p[42];
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}
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public override bool IsStateSave()
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{
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return true;
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}
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}
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}
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