去掉不必要的内容
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@ -1,8 +0,0 @@
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fileFormatVersion: 2
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guid: f996a7038b3e4a04bbc4722c030e7c0e
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folderAsset: yes
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DefaultImporter:
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externalObjects: {}
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userData:
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assetBundleName:
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assetBundleVariant:
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@ -1,263 +0,0 @@
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using System;
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using System.Runtime.InteropServices;
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namespace MAME.Core.AxiBitmap
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{
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[StructLayout(LayoutKind.Explicit)]
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public struct AxiColor
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{
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[FieldOffset(0)]
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public int sdColor;
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[FieldOffset(0)]
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public byte r;
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[FieldOffset(1)]
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public byte g;
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[FieldOffset(2)]
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public byte b;
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[FieldOffset(3)]
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public byte a;
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public AxiColor(byte _r, byte _g, byte _b)
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{
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r = g = b = a = 0;
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sdColor = 0;
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r = _r;
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g = _g;
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b = _b;
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a = byte.MaxValue;
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}
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public AxiColor(byte _r, byte _g, byte _b, byte _a)
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{
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r = g = b = a = 0;
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sdColor = 0;
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r = _r;
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g = _g;
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b = _b;
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a = _a;
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}
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public static AxiColor FromArgb(int argb)
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{
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return new AxiColor { sdColor = argb };
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}
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public override string ToString()
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{
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return String.Format("{0:X8}", sdColor);
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}
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public static int ToArgb(AxiColor color)
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{
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return color.sdColor;
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}
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#region 颜色定义
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public static AxiColor Transparent => new AxiColor(0, 0, 0, 0);
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public static AxiColor AliceBlue => new AxiColor(240, 248, 255);
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public static AxiColor AntiqueWhite => new AxiColor(250, 235, 215);
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public static AxiColor Aqua => new AxiColor(0, 255, 255);
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public static AxiColor Aquamarine => new AxiColor(127, 255, 212);
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public static AxiColor Azure => new AxiColor(240, 255, 255);
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public static AxiColor Beige => new AxiColor(245, 245, 220);
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public static AxiColor Bisque => new AxiColor(255, 228, 196);
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public static AxiColor Black => new AxiColor(0, 0, 0);
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public static AxiColor BlanchedAlmond => new AxiColor(255, 235, 205);
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public static AxiColor Blue => new AxiColor(0, 0, 255);
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public static AxiColor BlueViolet => new AxiColor(138, 43, 226);
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public static AxiColor Brown => new AxiColor(165, 42, 42);
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public static AxiColor BurlyWood => new AxiColor(222, 184, 135);
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public static AxiColor CadetBlue => new AxiColor(95, 158, 160);
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public static AxiColor Chartreuse => new AxiColor(127, 255, 0);
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public static AxiColor Chocolate => new AxiColor(210, 105, 30);
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public static AxiColor Coral => new AxiColor(255, 127, 80);
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public static AxiColor CornflowerBlue => new AxiColor(100, 149, 237);
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public static AxiColor Cornsilk => new AxiColor(255, 248, 220);
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public static AxiColor Crimson => new AxiColor(220, 20, 60);
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public static AxiColor Cyan => new AxiColor(0, 255, 255);
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public static AxiColor DarkBlue => new AxiColor(0, 0, 139);
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public static AxiColor DarkCyan => new AxiColor(0, 139, 139);
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public static AxiColor DarkGoldenrod => new AxiColor(184, 134, 11);
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public static AxiColor DarkGray => new AxiColor(169, 169, 169);
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public static AxiColor DarkGreen => new AxiColor(0, 100, 0);
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public static AxiColor DarkKhaki => new AxiColor(189, 183, 107);
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public static AxiColor DarkMagenta => new AxiColor(139, 0, 139);
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public static AxiColor DarkOliveGreen => new AxiColor(85, 107, 47);
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public static AxiColor DarkOrange => new AxiColor(255, 140, 0);
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public static AxiColor DarkOrchid => new AxiColor(153, 50, 204);
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public static AxiColor DarkRed => new AxiColor(139, 0, 0);
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public static AxiColor DarkSalmon => new AxiColor(233, 150, 122);
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public static AxiColor DarkSeaGreen => new AxiColor(143, 188, 143);
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public static AxiColor DarkSlateBlue => new AxiColor(72, 61, 139);
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public static AxiColor DarkSlateGray => new AxiColor(47, 79, 79);
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public static AxiColor DarkViolet => new AxiColor(148, 0, 211);
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public static AxiColor DeepPink => new AxiColor(255, 20, 147);
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public static AxiColor DeepSkyBlue => new AxiColor(0, 191, 255);
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public static AxiColor DimGray => new AxiColor(105, 105, 105);
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public static AxiColor DodgerBlue => new AxiColor(30, 144, 255);
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public static AxiColor FireBrick => new AxiColor(178, 34, 34);
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public static AxiColor FloralWhite => new AxiColor(255, 250, 240);
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public static AxiColor ForestGreen => new AxiColor(34, 139, 34);
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public static AxiColor Fuchsia => new AxiColor(255, 0, 255);
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public static AxiColor Gainsboro => new AxiColor(220, 220, 220);
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public static AxiColor GhostWhite => new AxiColor(248, 248, 255);
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public static AxiColor Gold => new AxiColor(255, 215, 0);
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public static AxiColor Goldenrod => new AxiColor(218, 165, 32);
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public static AxiColor Gray => new AxiColor(128, 128, 128);
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public static AxiColor Green => new AxiColor(0, 128, 0);
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public static AxiColor GreenYellow => new AxiColor(173, 255, 47);
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public static AxiColor Honeydew => new AxiColor(240, 255, 240);
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public static AxiColor HotPink => new AxiColor(255, 105, 180);
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public static AxiColor IndianRed => new AxiColor(205, 92, 92);
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public static AxiColor Indigo => new AxiColor(75, 0, 130);
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public static AxiColor Ivory => new AxiColor(255, 255, 240);
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public static AxiColor Khaki => new AxiColor(240, 230, 140);
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public static AxiColor Lavender => new AxiColor(230, 230, 250);
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public static AxiColor LavenderBlush => new AxiColor(255, 240, 245);
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public static AxiColor LawnGreen => new AxiColor(124, 252, 0);
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public static AxiColor LemonChiffon => new AxiColor(255, 250, 205);
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public static AxiColor LightBlue => new AxiColor(173, 216, 230);
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public static AxiColor LightCoral => new AxiColor(240, 128, 128);
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public static AxiColor LightCyan => new AxiColor(224, 255, 255);
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public static AxiColor LightGoldenrodYellow => new AxiColor(250, 250, 210);
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public static AxiColor LightGray => new AxiColor(211, 211, 211);
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public static AxiColor LightGreen => new AxiColor(144, 238, 144);
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public static AxiColor LightPink => new AxiColor(255, 182, 193);
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public static AxiColor LightSalmon => new AxiColor(255, 160, 122);
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public static AxiColor LightSeaGreen => new AxiColor(32, 178, 170);
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public static AxiColor LightSkyBlue => new AxiColor(135, 206, 250);
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public static AxiColor LightSlateGray => new AxiColor(119, 136, 153);
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public static AxiColor LightYellow => new AxiColor(255, 255, 224);
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public static AxiColor Lime => new AxiColor(0, 255, 0);
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public static AxiColor LimeGreen => new AxiColor(50, 205, 50);
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public static AxiColor Linen => new AxiColor(250, 240, 230);
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public static AxiColor Magenta => new AxiColor(255, 0, 255);
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public static AxiColor Maroon => new AxiColor(176, 48, 96);
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public static AxiColor MediumAquamarine => new AxiColor(102, 205, 170);
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public static AxiColor MediumBlue => new AxiColor(0, 0, 205);
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public static AxiColor MediumOrchid => new AxiColor(186, 85, 211);
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public static AxiColor MediumPurple => new AxiColor(147, 112, 219);
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public static AxiColor MediumSeaGreen => new AxiColor(60, 179, 113);
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public static AxiColor MediumSlateBlue => new AxiColor(123, 104, 238);
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public static AxiColor MediumSpringGreen => new AxiColor(0, 250, 154);
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public static AxiColor MediumTurquoise => new AxiColor(72, 209, 204);
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public static AxiColor MediumVioletRed => new AxiColor(199, 21, 133);
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public static AxiColor MidnightBlue => new AxiColor(25, 25, 112);
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public static AxiColor MintCream => new AxiColor(245, 255, 250);
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public static AxiColor MistyRose => new AxiColor(255, 228, 225);
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public static AxiColor Moccasin => new AxiColor(255, 228, 181);
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public static AxiColor NavajoWhite => new AxiColor(255, 222, 173);
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public static AxiColor Navy => new AxiColor(0, 0, 128);
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public static AxiColor OldLace => new AxiColor(253, 245, 230);
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public static AxiColor Olive => new AxiColor(128, 128, 0);
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public static AxiColor OliveDrab => new AxiColor(107, 142, 35);
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public static AxiColor Orange => new AxiColor(255, 165, 0);
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public static AxiColor OrangeRed => new AxiColor(255, 69, 0);
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public static AxiColor Orchid => new AxiColor(218, 112, 214);
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public static AxiColor PaleGoldenrod => new AxiColor(238, 232, 170);
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public static AxiColor PaleGreen => new AxiColor(152, 251, 152);
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public static AxiColor PaleTurquoise => new AxiColor(175, 238, 238);
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public static AxiColor PaleVioletRed => new AxiColor(219, 112, 147);
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public static AxiColor PapayaWhip => new AxiColor(255, 239, 213);
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public static AxiColor PeachPuff => new AxiColor(255, 218, 185);
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public static AxiColor Peru => new AxiColor(205, 133, 63);
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public static AxiColor Pink => new AxiColor(255, 192, 203);
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public static AxiColor Plum => new AxiColor(221, 160, 221);
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public static AxiColor PowderBlue => new AxiColor(176, 224, 230);
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public static AxiColor Purple => new AxiColor(160, 32, 240);
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public static AxiColor Red => new AxiColor(255, 0, 0);
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public static AxiColor RosyBrown => new AxiColor(188, 143, 143);
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public static AxiColor RoyalBlue => new AxiColor(65, 105, 225);
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public static AxiColor SaddleBrown => new AxiColor(139, 69, 19);
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public static AxiColor Salmon => new AxiColor(250, 128, 114);
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public static AxiColor SandyBrown => new AxiColor(244, 164, 96);
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public static AxiColor SeaGreen => new AxiColor(46, 139, 87);
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public static AxiColor SeaShell => new AxiColor(255, 245, 238);
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public static AxiColor Sienna => new AxiColor(160, 82, 45);
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public static AxiColor Silver => new AxiColor(192, 192, 192);
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public static AxiColor SkyBlue => new AxiColor(135, 206, 235);
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public static AxiColor SlateBlue => new AxiColor(106, 90, 205);
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public static AxiColor SlateGray => new AxiColor(112, 128, 144);
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public static AxiColor Snow => new AxiColor(255, 250, 250);
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public static AxiColor SpringGreen => new AxiColor(0, 255, 127);
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public static AxiColor SteelBlue => new AxiColor(70, 130, 180);
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public static AxiColor Tan => new AxiColor(210, 180, 140);
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public static AxiColor Teal => new AxiColor(0, 128, 128);
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public static AxiColor Thistle => new AxiColor(216, 191, 216);
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public static AxiColor Tomato => new AxiColor(255, 99, 71);
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public static AxiColor Turquoise => new AxiColor(64, 224, 208);
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public static AxiColor Violet => new AxiColor(238, 130, 238);
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public static AxiColor Wheat => new AxiColor(245, 222, 179);
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public static AxiColor White => new AxiColor(255, 255, 255);
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public static AxiColor WhiteSmoke => new AxiColor(245, 245, 245);
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public static AxiColor Yellow => new AxiColor(255, 255, 0);
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public static AxiColor YellowGreen => new AxiColor(154, 205, 50);
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#endregion
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}
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public static class AxiBitmapEx
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{
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public static int ToArgb(this AxiColor color)
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{
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return (color.a << 24) | (color.r << 16) | (color.g << 8) | color.b;
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}
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//public static void CloneIntColorArr(int[] baseBitmap, int[] targetBitmap, int baseWidth, int baseHeight, Rectangle rect)
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//{
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// // 检查矩形是否超出位图边界
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// if (rect.X < 0 || rect.X + rect.Width > baseWidth || rect.Y < 0 || rect.Y + rect.Height > baseHeight)
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// {
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// throw new ArgumentException("Rectangle is out of bitmap bounds.");
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// }
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// int baseStartIndex = rect.Y * baseWidth + rect.X;
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// int targetStartIndex = rect.Y * rect.Width;
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// for (int y = 0; y < rect.Height; y++)
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// {
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// // 注意这里使用了rect.Width作为要拷贝的元素数量，而不是baseWidth
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// Buffer.BlockCopy(baseBitmap, baseStartIndex + y * baseWidth, targetBitmap, targetStartIndex + y * rect.Width, rect.Width * sizeof(int));
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// // 或者使用Array.Copy，但要注意类型的大小（在这里是int）
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// // Array.Copy(baseBitmap, baseStartIndex + y * baseWidth, targetBitmap, targetStartIndex + y * rect.Width, rect.Width);
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// }
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//}
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public static void CloneIntColorArr(int[] baseBitmap, int[] targetBitmap, int Width, int Height, Rectangle rect)
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{
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// 检查矩形是否超出位图边界
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if (rect.X < 0 || rect.Right > Width || rect.Y < 0 || rect.Bottom > Height)
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{
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throw new ArgumentException("out of");
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}
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int srcStartIndex = rect.Y * Width + rect.X;
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for (int y = 0; y < rect.Height; y++)
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{
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Array.Copy(baseBitmap, srcStartIndex + y * Width, targetBitmap, y * rect.Width, rect.Width);
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}
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}
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public struct Rectangle
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{
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public int X;
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public int Y;
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public int Width;
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public int Height;
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public Rectangle(int x, int y, int width, int height)
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{
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X = x;
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Y = y;
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Width = width;
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Height = height;
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}
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public int Right => X + Width;
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public int Bottom => Y + Height;
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public int Area { get { return Width * Height; } }
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public bool Contains(int pointX, int pointY) { return pointX >= X && pointX < X + Width && pointY >= Y && pointY < Y + Height; }
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}
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}
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}
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@ -1,11 +0,0 @@
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fileFormatVersion: 2
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guid: b94fc4b46eb73b541b66a64f2831e49c
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MonoImporter:
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externalObjects: {}
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serializedVersion: 2
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defaultReferences: []
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executionOrder: 0
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icon: {instanceID: 0}
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userData:
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assetBundleName:
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assetBundleVariant:
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@ -7,7 +7,7 @@ namespace MAME.Core
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public class MameMainMotion
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{
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public string tsslStatus;
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public CheatMotion cheatmotion;
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//public CheatMotion cheatmotion;
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public M68000Motion m68000motion;
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public Z80Motion z80motion;
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public M6809Motion m6809motion;
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@ -26,7 +26,7 @@ namespace MAME.Core
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public MameMainMotion()
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{
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neogeomotion = new NeogeoMotion();
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cheatmotion = new CheatMotion();
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//cheatmotion = new CheatMotion();
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m68000motion = new M68000Motion();
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m6809motion = new M6809Motion();
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z80motion = new Z80Motion();
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@ -204,8 +204,6 @@ namespace MAME.Core
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public void StartGame()
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{
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bIsNewThreadMode = false;
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M68000Motion.iStatus = 0;
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M68000Motion.iValue = 0;
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Mame.exit_pending = false;
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Mame.mame_execute_UpdateMode_Start();
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@ -214,8 +212,6 @@ namespace MAME.Core
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public void StartGame_WithNewThread()
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{
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bIsNewThreadMode = true;
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M68000Motion.iStatus = 0;
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M68000Motion.iValue = 0;
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Mame.exit_pending = false;
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//初始化停帧信号量
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@ -1,138 +0,0 @@
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using cpu.m68000;
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using cpu.nec;
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using System;
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using System.Collections.Generic;
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namespace MAME.Core
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{
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public unsafe partial class CheatMotion
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{
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public enum LockState
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{
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LOCK_NONE = 0,
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LOCK_SECOND,
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LOCK_FRAME,
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}
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public LockState lockState = LockState.LOCK_NONE;
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public List<int[]> lsCheatdata1;
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public List<int[]> lsCheatdata2;
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private string[] sde6 = new string[1] { "," }, sde7 = new string[1] { ";" }, sde9 = new string[1] { "$" }, sde10 = new string[] { "+" };
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public Func<int, byte> CheatReadByte;
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public Action<int, byte> CheatWriteByte;
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#region
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List<string> mTxList_tbResult = new List<string>();
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#endregion
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public CheatMotion()
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{
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cheatForm_Load();
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}
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private void cheatForm_Load()
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{
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switch (Machine.sBoard)
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{
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case "CPS-1":
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case "CPS-1(QSound)":
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case "CPS2":
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case "Data East":
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case "Tehkan":
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case "Neo Geo":
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case "Taito B":
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case "Konami 68000":
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case "Capcom":
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CheatReadByte = (int i1) => { return Memory.mainram_Ptr[i1]; };
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CheatWriteByte = (int i1, byte b1) => { Memory.mainram_Ptr[i1] = b1; };
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break;
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case "Namco System 1":
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CheatReadByte = (int i1) => { return Namcos1.N0ReadMemory((ushort)i1); };
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CheatWriteByte = (int i1, byte b1) => { Namcos1.N0WriteMemory((ushort)i1, b1); };
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break;
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case "IGS011":
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CheatReadByte = (int i1) => { return (byte)MC68000.m1.ReadByte(i1); };
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CheatWriteByte = (int i1, byte b1) => { MC68000.m1.WriteByte(i1, (sbyte)b1); };
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break;
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case "PGM":
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CheatReadByte = (int i1) => { return (byte)MC68000.m1.ReadByte(i1); };
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CheatWriteByte = (int i1, byte b1) => { MC68000.m1.WriteByte(i1, (sbyte)b1); };
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break;
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case "M72":
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case "M92":
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CheatReadByte = (int i1) => { return Nec.nn1[0].ReadByte(i1); };
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CheatWriteByte = (int i1, byte b1) => { Nec.nn1[0].WriteByte(i1, b1); };
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break;
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}
|
||||
}
|
||||
private void GetCheatdata()
|
||||
{
|
||||
// lsCheatdata1 = new List<int[]>();
|
||||
// lsCheatdata2 = new List<int[]>();
|
||||
// int i1, i2, i3, iAddress, iOffsetAddress1, iOffsetAddress2, iValue2, n3;
|
||||
// string[] ss1, ss2, ss3;
|
||||
// foreach (ListViewItem item1 in listViewControl1.myListView.Items)
|
||||
// {
|
||||
// if (item1.Checked)
|
||||
// {
|
||||
// i1 = listViewControl1.myListView.Items.IndexOf(item1);
|
||||
// i2 = Array.IndexOf(listViewControl1.ssCItem[i1], item1.SubItems[1].Text);
|
||||
// ss1 = listViewControl1.ssCValue[i1][i2].Split(sde7, StringSplitOptions.RemoveEmptyEntries);
|
||||
// n3 = ss1.Length;
|
||||
// for (i3 = 0; i3 < n3; i3++)
|
||||
// {
|
||||
// ss3 = ss1[i3].Split(sde6, StringSplitOptions.RemoveEmptyEntries);
|
||||
// iValue2 = Convert.ToInt32(ss3[1], 16);
|
||||
// if (ss3[0].IndexOf("$") >= 0)
|
||||
// {
|
||||
// ss2 = ss3[0].Split(sde9, StringSplitOptions.RemoveEmptyEntries);
|
||||
// iOffsetAddress1 = Convert.ToInt32(ss2[0], 16);
|
||||
// iOffsetAddress2 = Convert.ToInt32(ss2[1], 16);
|
||||
// lsCheatdata1.Add(new int[] { iOffsetAddress1, iOffsetAddress2, iValue2 });
|
||||
// }
|
||||
// else if (ss3[0].IndexOf("+") >= 0)
|
||||
// {
|
||||
// ss2 = ss3[0].Split(sde10, StringSplitOptions.RemoveEmptyEntries);
|
||||
// iOffsetAddress1 = Convert.ToInt32(ss2[0], 16);
|
||||
// iOffsetAddress2 = Convert.ToInt32(ss2[1], 16);
|
||||
// iAddress = iOffsetAddress1 + iOffsetAddress2;
|
||||
// lsCheatdata2.Add(new int[] { iAddress, iValue2 });
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// iAddress = Convert.ToInt32(ss3[0], 16);
|
||||
// lsCheatdata2.Add(new int[] { iAddress, iValue2 });
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
}
|
||||
public void ApplyCheat()
|
||||
{
|
||||
int iAddress, iValue1;
|
||||
foreach (int[] ii1 in lsCheatdata1)
|
||||
{
|
||||
//iAddress = bbMem[ii1[0]] * 0x100 + bbMem[ii1[0] + 1] + ii1[1];
|
||||
//iValue1 = bbMem[iAddress];
|
||||
//bbMem[iAddress] = (byte)ii1[2];
|
||||
iAddress = CheatReadByte(ii1[0]) * 0x100 + CheatReadByte(ii1[0] + 1) + ii1[1];
|
||||
iValue1 = CheatReadByte(iAddress);
|
||||
CheatWriteByte(iAddress, (byte)ii1[2]);
|
||||
if (iValue1 != ii1[2])
|
||||
{
|
||||
mTxList_tbResult.Add(iAddress.ToString("X4") + " " + iValue1.ToString("X2") + " " + ii1[2].ToString("X2") + "\r\n");
|
||||
}
|
||||
}
|
||||
foreach (int[] ii1 in lsCheatdata2)
|
||||
{
|
||||
iAddress = ii1[0];
|
||||
//iValue1 = bbMem[iAddress];
|
||||
//bbMem[ii1[0]] = (byte)ii1[1];
|
||||
iValue1 = CheatReadByte(iAddress);
|
||||
CheatWriteByte(ii1[0], (byte)ii1[1]);
|
||||
if (iValue1 != ii1[1])
|
||||
{
|
||||
mTxList_tbResult.Add(ii1[0].ToString("X4") + " " + iValue1.ToString("X2") + " " + ii1[1].ToString("X2") + "\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,11 +0,0 @@
|
||||
fileFormatVersion: 2
|
||||
guid: 847edc5d4d82b7448a62f92c9d3dee10
|
||||
MonoImporter:
|
||||
externalObjects: {}
|
||||
serializedVersion: 2
|
||||
defaultReferences: []
|
||||
executionOrder: 0
|
||||
icon: {instanceID: 0}
|
||||
userData:
|
||||
assetBundleName:
|
||||
assetBundleVariant:
|
||||
@ -1,36 +1,7 @@
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace MAME.Core
|
||||
namespace MAME.Core
|
||||
{
|
||||
public partial class CpsMotion
|
||||
{
|
||||
private string[] sde2 = new string[] { "," };
|
||||
private int locationX, locationY;
|
||||
|
||||
#region
|
||||
public bool cbLockpal = false;
|
||||
public bool cbRowscroll = false;
|
||||
public string tbInput = string.Empty;
|
||||
public bool cbL0 = false;
|
||||
public bool cbL1 = false;
|
||||
public bool cbL2 = false;
|
||||
public bool cbL3 = false;
|
||||
public string tbFile = string.Empty;
|
||||
public string tbPoint = string.Empty;
|
||||
public int cbLayer = 0;
|
||||
public string tbCode = string.Empty;
|
||||
public string tbColor = string.Empty;
|
||||
|
||||
public string tbScroll1x = string.Empty;
|
||||
public string tbScroll1y = string.Empty;
|
||||
public string tbScroll2x = string.Empty;
|
||||
public string tbScroll2y = string.Empty;
|
||||
public string tbScroll3x = string.Empty;
|
||||
public string tbScroll3y = string.Empty;
|
||||
public string tbScrollsx = string.Empty;
|
||||
public string tbScrollsy = string.Empty;
|
||||
public List<string> tbResult = new List<string>();
|
||||
#endregion
|
||||
public CpsMotion()
|
||||
{
|
||||
}
|
||||
|
||||
@ -2,18 +2,8 @@
|
||||
{
|
||||
public class Konami68000Motion
|
||||
{
|
||||
private int locationX, locationY;
|
||||
|
||||
#region
|
||||
public bool cbT0 = false;
|
||||
public bool cbT1 = false;
|
||||
public bool cbT2 = false;
|
||||
public bool cbSprite = false;
|
||||
public string tbSprite;
|
||||
#endregion
|
||||
public Konami68000Motion()
|
||||
{
|
||||
tbSprite = "0000-4000";
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -6,187 +6,8 @@ namespace MAME.Core
|
||||
{
|
||||
public class M68000Motion
|
||||
{
|
||||
private string[] sde6 = new string[1] { "," }, sde7 = new string[1] { ";" }, sde9 = new string[1] { "$" }, sde10 = new string[] { "+" };
|
||||
private bool bLogNew, bNew;
|
||||
public static int iStatus, iRAddress, iWAddress, iROp, iWOp, iValue;
|
||||
private int PPCTill, PPC, Addr;
|
||||
private ulong CyclesTill, TotalExecutedCycles;
|
||||
private List<int> lsAddr = new List<int>();
|
||||
private List<int> lsPPC = new List<int>();
|
||||
|
||||
|
||||
#region
|
||||
string[] mTxList_tbDs;
|
||||
string[] mTxList_tbAs;
|
||||
Boolean[] mBList_cbDs;
|
||||
Boolean[] mBList_cbAs;
|
||||
List<Boolean> mBList_lsCB;
|
||||
|
||||
string mTx_tbPPC = string.Empty;
|
||||
string mTx_tbOP = string.Empty;
|
||||
Boolean b_cbS = false;
|
||||
Boolean b_cbM = false;
|
||||
Boolean b_cbX = false;
|
||||
Boolean b_cbN = false;
|
||||
Boolean b_cbZ = false;
|
||||
Boolean b_cbV = false;
|
||||
Boolean b_cbC = false;
|
||||
Boolean b_cbPC = false;
|
||||
Boolean b_cbTotal = false;
|
||||
Boolean b_cbLog = false;
|
||||
string mTx_tbIML = string.Empty;
|
||||
string mTx_tbUSP = string.Empty;
|
||||
string mTx_tbSSP = string.Empty;
|
||||
string mTx_tbCycles = string.Empty;
|
||||
string mTx_tbPC = string.Empty;
|
||||
string mTx_tbDisassemble = string.Empty;
|
||||
List<string> mTxList_tbResult = new List<string>();
|
||||
public string mTx_tsslStatus = string.Empty;
|
||||
#endregion
|
||||
|
||||
public enum M68000State
|
||||
{
|
||||
M68000_NONE = 0,
|
||||
M68000_RUN,
|
||||
M68000_STEP,
|
||||
M68000_STEP2,
|
||||
M68000_STEP3,
|
||||
M68000_STOP,
|
||||
}
|
||||
public static M68000State m68000State, m68000FState;
|
||||
public M68000Motion()
|
||||
{
|
||||
int i;
|
||||
mTxList_tbDs = new string[8];
|
||||
mTxList_tbAs = new string[8];
|
||||
mBList_cbDs = new bool[8];
|
||||
mBList_cbAs = new bool[8];
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
mTxList_tbDs[i] = string.Empty;
|
||||
mBList_cbDs[i] = false;
|
||||
mTxList_tbAs[i] = string.Empty;
|
||||
mBList_cbAs[i] = false;
|
||||
}
|
||||
|
||||
b_cbPC = false;
|
||||
b_cbTotal = false;
|
||||
mBList_lsCB = new List<bool>();
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
mBList_lsCB.Add(mBList_cbDs[i]);
|
||||
mBList_lsCB.Add(mBList_cbAs[i]);
|
||||
}
|
||||
mBList_lsCB.Add(b_cbPC);
|
||||
}
|
||||
//public void GetData()
|
||||
//{
|
||||
// int i;
|
||||
// string sDisassemble, sDisassemble2 = "";
|
||||
// for (i = 0; i < 8; i++)
|
||||
// {
|
||||
// mTxList_tbDs[i] = MC68000.m1.D[i].u32.ToString("X8");
|
||||
// mTxList_tbAs[i] = MC68000.m1.A[i].u32.ToString("X8");
|
||||
// }
|
||||
// mTx_tbPPC = MC68000.m1.PPC.ToString("X6");
|
||||
// mTx_tbOP = MC68000.m1.op.ToString("X4");
|
||||
// b_cbS = MC68000.m1.S;
|
||||
// b_cbM = MC68000.m1.M;
|
||||
// b_cbX = MC68000.m1.X;
|
||||
// b_cbN = MC68000.m1.N;
|
||||
// b_cbZ = MC68000.m1.Z;
|
||||
// b_cbV = MC68000.m1.V;
|
||||
// b_cbC = MC68000.m1.C;
|
||||
// mTx_tbIML = MC68000.m1.InterruptMaskLevel.ToString();
|
||||
// mTx_tbUSP = MC68000.m1.usp.ToString("X8");
|
||||
// mTx_tbSSP = MC68000.m1.ssp.ToString("X8");
|
||||
// mTx_tbCycles = MC68000.m1.TotalExecutedCycles.ToString("X16");
|
||||
// mTx_tbPC = MC68000.m1.PC.ToString("X6");
|
||||
// sDisassemble = MC68000.m1.Disassemble(MC68000.m1.PPC).ToString();
|
||||
// mTx_tbDisassemble = sDisassemble;
|
||||
// sDisassemble2 = sDisassemble;
|
||||
// foreach (bool cb in mBList_lsCB)
|
||||
// {
|
||||
// if (cb)
|
||||
// {
|
||||
// //sDisassemble2 += " " + cb + cb.TB.Text;
|
||||
// sDisassemble2 += " " + cb + cb;
|
||||
// }
|
||||
// }
|
||||
// if (b_cbTotal)
|
||||
// {
|
||||
// sDisassemble2 = MC68000.m1.TotalExecutedCycles.ToString("X") + " " + sDisassemble2;
|
||||
// }
|
||||
// mTxList_tbResult.Add(sDisassemble2 + "\r\n");
|
||||
//}
|
||||
//public void m68000_start_debug()
|
||||
//{
|
||||
// if (bLogNew && lsPPC.IndexOf(MC68000.m1.PPC) < 0)
|
||||
// {
|
||||
// m68000FState = m68000State;
|
||||
// m68000State = M68000State.M68000_STOP;
|
||||
// lsPPC.Add(MC68000.m1.PPC);
|
||||
// mTxList_tbResult.Add(MC68000.m1.Disassemble(MC68000.m1.PPC).ToString() + "\r\n");
|
||||
// m68000State = m68000FState;
|
||||
// }
|
||||
// PPC = MC68000.m1.PPC;
|
||||
// TotalExecutedCycles = MC68000.m1.TotalExecutedCycles;
|
||||
// if (iStatus == 1)
|
||||
// {
|
||||
// iStatus = 0;
|
||||
// }
|
||||
// if (m68000State == M68000State.M68000_STEP2)
|
||||
// {
|
||||
// if (MC68000.m1.PPC == PPCTill)
|
||||
// {
|
||||
// m68000State = M68000State.M68000_STOP;
|
||||
// }
|
||||
// }
|
||||
// if (m68000State == M68000State.M68000_STEP3)
|
||||
// {
|
||||
// if (MC68000.m1.TotalExecutedCycles >= CyclesTill)
|
||||
// {
|
||||
// m68000State = M68000State.M68000_STOP;
|
||||
// }
|
||||
// }
|
||||
// if (b_cbLog == true && (m68000State == M68000State.M68000_STEP2 || m68000State == M68000State.M68000_STEP3))
|
||||
// {
|
||||
// GetData();
|
||||
// }
|
||||
// if (m68000State == M68000State.M68000_STOP)
|
||||
// {
|
||||
// GetData();
|
||||
// mTx_tsslStatus = "m68000 stop";
|
||||
// }
|
||||
// while (m68000State == M68000State.M68000_STOP)
|
||||
// {
|
||||
|
||||
// }
|
||||
//}
|
||||
//public void m68000_stop_debug()
|
||||
//{
|
||||
// if (iStatus == 1)
|
||||
// {
|
||||
// GetData();
|
||||
// m68000State = M68000State.M68000_STOP;
|
||||
// mTx_tsslStatus = "m68000 stop";
|
||||
// iStatus = 2;
|
||||
// }
|
||||
// if (m68000State == M68000State.M68000_STEP)
|
||||
// {
|
||||
// m68000State = M68000State.M68000_STOP;
|
||||
// mTx_tsslStatus = "m68000 stop";
|
||||
// }
|
||||
// if (iStatus == 0)
|
||||
// {
|
||||
// /*if(Memory.mainram_Ptr[0xd1b]==0x05)
|
||||
// {
|
||||
// iStatus = 1;
|
||||
// GetData();
|
||||
// m68000State = M68000State.M68000_STOP;
|
||||
// tsslStatus.Text = "m68000 stop";
|
||||
// }*/
|
||||
// }
|
||||
//}
|
||||
}
|
||||
}
|
||||
|
||||
@ -6,100 +6,8 @@ namespace MAME.Core
|
||||
|
||||
public partial class M6809Motion
|
||||
{
|
||||
//private Disassembler disassembler;
|
||||
private bool bLogNew;
|
||||
public static int iStatus;
|
||||
private int PPCTill;
|
||||
private ulong CyclesTill;
|
||||
private List<ushort> lPPC = new List<ushort>();
|
||||
public static CPUState m6809State, m6809FState;
|
||||
|
||||
#region
|
||||
public List<string> tbResult = new List<string>();
|
||||
public string tsslStatus = string.Empty;
|
||||
public string tbD = string.Empty;
|
||||
public string tbDp = string.Empty;
|
||||
public string tbU = string.Empty;
|
||||
public string tbS = string.Empty;
|
||||
public string tbX = string.Empty;
|
||||
public string tbY = string.Empty;
|
||||
public string tbCc = string.Empty;
|
||||
public string tbIrqstate0 = string.Empty;
|
||||
public string tbIrqstate1 = string.Empty;
|
||||
public string tbIntstate = string.Empty;
|
||||
public string tbNmistate = string.Empty;
|
||||
public string tbPPC = string.Empty;
|
||||
public string tbCycles = string.Empty;
|
||||
public string tbDisassemble = string.Empty;
|
||||
#endregion
|
||||
|
||||
public M6809Motion()
|
||||
{
|
||||
}
|
||||
public void GetData()
|
||||
{
|
||||
int reg, offset;
|
||||
reg = M6809.mm1[0].PPC.LowWord / 0x2000;
|
||||
offset = M6809.mm1[0].PPC.LowWord & 0x1fff;
|
||||
tbD = M6809.mm1[0].D.LowWord.ToString("X4");
|
||||
tbDp = M6809.mm1[0].DP.LowWord.ToString("X4");
|
||||
tbU = M6809.mm1[0].U.LowWord.ToString("X4");
|
||||
tbS = M6809.mm1[0].S.LowWord.ToString("X4");
|
||||
tbX = M6809.mm1[0].X.LowWord.ToString("X4");
|
||||
tbY = M6809.mm1[0].Y.LowWord.ToString("X4");
|
||||
tbCc = M6809.mm1[0].CC.ToString("X2");
|
||||
tbIrqstate0 = M6809.mm1[0].irq_state[0].ToString("X2");
|
||||
tbIrqstate1 = M6809.mm1[0].irq_state[1].ToString("X2");
|
||||
tbIntstate = M6809.mm1[0].int_state.ToString("X2");
|
||||
tbNmistate = M6809.mm1[0].nmi_state.ToString("X2");
|
||||
tbPPC = (Namcos1.user1rom_offset[0, reg] + offset).ToString("X6");
|
||||
tbCycles = M6809.mm1[0].TotalExecutedCycles.ToString("X16");
|
||||
tbDisassemble = M6809.mm1[0].m6809_dasm(M6809.mm1[0].PPC.LowWord);
|
||||
|
||||
}
|
||||
public void m6809_start_debug()
|
||||
{
|
||||
if (bLogNew && lPPC.IndexOf(M6809.mm1[0].PPC.LowWord) < 0)
|
||||
{
|
||||
m6809FState = m6809State;
|
||||
m6809State = CPUState.STOP;
|
||||
lPPC.Add(M6809.mm1[0].PPC.LowWord);
|
||||
tbResult.Add(M6809.mm1[0].PPC.LowWord.ToString("X4") + ": ");
|
||||
m6809State = m6809FState;
|
||||
}
|
||||
if (m6809State == CPUState.STEP2)
|
||||
{
|
||||
if (M6809.mm1[0].PPC.LowWord == PPCTill)
|
||||
{
|
||||
m6809State = CPUState.STOP;
|
||||
}
|
||||
}
|
||||
if (m6809State == CPUState.STEP3)
|
||||
{
|
||||
if (M6809.mm1[0].TotalExecutedCycles >= CyclesTill)
|
||||
{
|
||||
m6809State = CPUState.STOP;
|
||||
}
|
||||
}
|
||||
if (m6809State == CPUState.STOP)
|
||||
{
|
||||
GetData();
|
||||
tsslStatus = "m6809 stop";
|
||||
}
|
||||
while (m6809State == CPUState.STOP)
|
||||
{
|
||||
Video.video_frame_update();
|
||||
//??
|
||||
//Application.DoEvents();
|
||||
}
|
||||
}
|
||||
public void m6809_stop_debug()
|
||||
{
|
||||
if (m6809State == CPUState.STEP)
|
||||
{
|
||||
m6809State = CPUState.STOP;
|
||||
tsslStatus = "m6809 stop";
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -4,33 +4,8 @@ namespace MAME.Core
|
||||
{
|
||||
public partial class NeogeoMotion
|
||||
{
|
||||
private string[] sde2 = new string[] { "," };
|
||||
private int locationX, locationY;
|
||||
public List<string> tbResult;
|
||||
public string tbSprite = string.Empty;
|
||||
public string tbPoint = string.Empty;
|
||||
public string tbFile = string.Empty;
|
||||
public string tbSOffset = string.Empty;
|
||||
public string tbPensoffset = string.Empty;
|
||||
|
||||
#region
|
||||
bool cbL0 = false;
|
||||
bool cbL1 = false;
|
||||
#endregion
|
||||
public NeogeoMotion()
|
||||
{
|
||||
tbResult = new List<string>();
|
||||
neogeoForm_Load();
|
||||
}
|
||||
private void neogeoForm_Load()
|
||||
{
|
||||
cbL0 = true;
|
||||
cbL1 = true;
|
||||
tbSprite = "000-17C";
|
||||
tbFile = "00";
|
||||
tbPoint = "350,240,30,16";
|
||||
tbSOffset = "01cb0600";
|
||||
tbPensoffset = "ed0";
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -3,130 +3,12 @@ using System.Collections.Generic;
|
||||
|
||||
namespace MAME.Core
|
||||
{
|
||||
public enum CPUState
|
||||
{
|
||||
NONE = 0,
|
||||
RUN,
|
||||
STEP,
|
||||
STEP2,
|
||||
STEP3,
|
||||
STOP,
|
||||
}
|
||||
public partial class Z80Motion
|
||||
{
|
||||
private Disassembler disassembler;
|
||||
private bool bLogNew;
|
||||
public static int iStatus;
|
||||
private int PPCTill;
|
||||
private ulong CyclesTill;
|
||||
private List<ushort> lPPC = new List<ushort>();
|
||||
|
||||
#region
|
||||
string mTx_tbAF = string.Empty;
|
||||
string mTx_tbBC = string.Empty;
|
||||
string mTx_tbDE = string.Empty;
|
||||
string mTx_tbHL = string.Empty;
|
||||
string mTx_tbShadowAF = string.Empty;
|
||||
string mTx_tbShadowBC = string.Empty;
|
||||
string mTx_tbShadowDE = string.Empty;
|
||||
string mTx_tbShadowHL = string.Empty;
|
||||
string mTx_tbI = string.Empty;
|
||||
string mTx_tbR = string.Empty;
|
||||
string mTx_tbIX = string.Empty;
|
||||
string mTx_tbIY = string.Empty;
|
||||
string mTx_tbSP = string.Empty;
|
||||
string mTx_tbRPC = string.Empty;
|
||||
string mTx_tbPPC = string.Empty;
|
||||
string mTx_tbR2 = string.Empty;
|
||||
string mTx_tbWZ = string.Empty;
|
||||
string mTx_tbCycles = string.Empty;
|
||||
string mTx_tbDisassemble = string.Empty;
|
||||
|
||||
public string mTx_tsslStatus = string.Empty;
|
||||
List<string> mTxList_tbResult = new List<string>();
|
||||
#endregion
|
||||
public enum Z80AState
|
||||
{
|
||||
Z80A_NONE = 0,
|
||||
Z80A_RUN,
|
||||
Z80A_STEP,
|
||||
Z80A_STEP2,
|
||||
Z80A_STEP3,
|
||||
Z80A_STOP,
|
||||
}
|
||||
public static Z80AState z80State, z80FState;
|
||||
public Z80Motion()
|
||||
{
|
||||
disassembler = new Disassembler();
|
||||
Disassembler.GenerateOpcodeSizes();
|
||||
}
|
||||
|
||||
public void GetData()
|
||||
{
|
||||
string sDisassemble;
|
||||
mTx_tbAF = Z80A.zz1[0].RegisterAF.ToString("X4");
|
||||
mTx_tbBC = Z80A.zz1[0].RegisterBC.ToString("X4");
|
||||
mTx_tbDE = Z80A.zz1[0].RegisterDE.ToString("X4");
|
||||
mTx_tbHL = Z80A.zz1[0].RegisterHL.ToString("X4");
|
||||
mTx_tbShadowAF = Z80A.zz1[0].RegisterShadowAF.ToString("X4");
|
||||
mTx_tbShadowBC = Z80A.zz1[0].RegisterShadowBC.ToString("X4");
|
||||
mTx_tbShadowDE = Z80A.zz1[0].RegisterShadowDE.ToString("X4");
|
||||
mTx_tbShadowHL = Z80A.zz1[0].RegisterShadowHL.ToString("X4");
|
||||
mTx_tbI = Z80A.zz1[0].RegisterI.ToString("X2");
|
||||
mTx_tbR = Z80A.zz1[0].RegisterR.ToString("X2");
|
||||
mTx_tbIX = Z80A.zz1[0].RegisterIX.ToString("X4");
|
||||
mTx_tbIY = Z80A.zz1[0].RegisterIY.ToString("X4");
|
||||
mTx_tbSP = Z80A.zz1[0].RegisterSP.ToString("X4");
|
||||
mTx_tbRPC = Z80A.zz1[0].RegisterPC.ToString("X4");
|
||||
mTx_tbPPC = Z80A.zz1[0].PPC.ToString("X4");
|
||||
mTx_tbR2 = Z80A.zz1[0].RegisterR2.ToString("X2");
|
||||
mTx_tbWZ = Z80A.zz1[0].RegisterWZ.ToString("X4");
|
||||
mTx_tbCycles = Z80A.zz1[0].TotalExecutedCycles.ToString("X16");
|
||||
sDisassemble = disassembler.GetDisassembleInfo(Z80A.zz1[0].PPC);
|
||||
mTx_tbDisassemble = sDisassemble;
|
||||
mTxList_tbResult.Add(sDisassemble + "\r\n");
|
||||
}
|
||||
public void z80_start_debug()
|
||||
{
|
||||
if (bLogNew && lPPC.IndexOf(Z80A.zz1[0].PPC) < 0)
|
||||
{
|
||||
z80FState = z80State;
|
||||
z80State = Z80AState.Z80A_STOP;
|
||||
lPPC.Add(Z80A.zz1[0].PPC);
|
||||
mTxList_tbResult.Add(Z80A.zz1[0].PPC.ToString("X4") + ": " + disassembler.GetDisassembleInfo(Z80A.zz1[0].PPC) + "\r\n");
|
||||
z80State = z80FState;
|
||||
}
|
||||
if (z80State == Z80AState.Z80A_STEP2)
|
||||
{
|
||||
if (Z80A.zz1[0].PPC == PPCTill)
|
||||
{
|
||||
z80State = Z80AState.Z80A_STOP;
|
||||
}
|
||||
}
|
||||
if (z80State == Z80AState.Z80A_STEP3)
|
||||
{
|
||||
if (Z80A.zz1[0].TotalExecutedCycles >= CyclesTill)
|
||||
{
|
||||
z80State = Z80AState.Z80A_STOP;
|
||||
}
|
||||
}
|
||||
if (z80State == Z80AState.Z80A_STOP)
|
||||
{
|
||||
GetData();
|
||||
mTx_tsslStatus = "z80 stop";
|
||||
}
|
||||
while (z80State == Z80AState.Z80A_STOP)
|
||||
{
|
||||
|
||||
}
|
||||
}
|
||||
public void z80_stop_debug()
|
||||
{
|
||||
if (z80State == Z80AState.Z80A_STEP)
|
||||
{
|
||||
z80State = Z80AState.Z80A_STOP;
|
||||
mTx_tsslStatus = "z80 stop";
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -146,7 +146,6 @@ namespace cpu.m6502
|
||||
{
|
||||
byte op;
|
||||
ppc.d = pc.d;
|
||||
//debugger_instruction_hook(Machine, PCD);
|
||||
if (pending_irq != 0)
|
||||
{
|
||||
m6502_take_irq();
|
||||
|
||||
@ -1,144 +0,0 @@
|
||||
using System.Text;
|
||||
|
||||
namespace cpu.m68000
|
||||
{
|
||||
public sealed class DisassemblyInfo
|
||||
{
|
||||
public int PC;
|
||||
public string Mnemonic;
|
||||
public string Args;
|
||||
public string RawBytes;
|
||||
public int Length;
|
||||
|
||||
public override string ToString()
|
||||
{
|
||||
return string.Format("{0:X6}: {3,-20} {1,-8} {2}", PC, Mnemonic, Args, RawBytes);
|
||||
}
|
||||
}
|
||||
|
||||
partial class MC68000
|
||||
{
|
||||
//public DisassemblyInfo Disassemble(int pc)
|
||||
//{
|
||||
// var info = new DisassemblyInfo { Mnemonic = "UNKNOWN", PC = pc, Length = 2 };
|
||||
// op = (ushort)ReadOpWord(pc);
|
||||
|
||||
// if (Opcodes[op] == MOVE) MOVE_Disasm(info);//
|
||||
// else if (Opcodes[op] == MOVEA) MOVEA_Disasm(info);
|
||||
// else if (Opcodes[op] == MOVEQ) MOVEQ_Disasm(info);
|
||||
// else if (Opcodes[op] == MOVEM0) MOVEM0_Disasm(info);
|
||||
// else if (Opcodes[op] == MOVEM1) MOVEM1_Disasm(info);
|
||||
// else if (Opcodes[op] == LEA) LEA_Disasm(info);//
|
||||
// else if (Opcodes[op] == CLR) CLR_Disasm(info);
|
||||
// else if (Opcodes[op] == EXT) EXT_Disasm(info);
|
||||
// else if (Opcodes[op] == PEA) PEA_Disasm(info);
|
||||
// else if (Opcodes[op] == ANDI) ANDI_Disasm(info);
|
||||
// else if (Opcodes[op] == ANDI_CCR) ANDI_CCR_Disasm(info);
|
||||
// else if (Opcodes[op] == EORI) EORI_Disasm(info);
|
||||
// else if (Opcodes[op] == EORI_CCR) EORI_CCR_Disasm(info);
|
||||
// else if (Opcodes[op] == ORI) ORI_Disasm(info);
|
||||
// else if (Opcodes[op] == ORI_CCR) ORI_CCR_Disasm(info);
|
||||
// else if (Opcodes[op] == ASLd) ASLd_Disasm(info);
|
||||
// else if (Opcodes[op] == ASRd) ASRd_Disasm(info);
|
||||
// else if (Opcodes[op] == LSLd) LSLd_Disasm(info);
|
||||
// else if (Opcodes[op] == LSRd) LSRd_Disasm(info);
|
||||
// else if (Opcodes[op] == ROXLd) ROXLd_Disasm(info);
|
||||
// else if (Opcodes[op] == ROXRd) ROXRd_Disasm(info);
|
||||
// else if (Opcodes[op] == ROLd) ROLd_Disasm(info);
|
||||
// else if (Opcodes[op] == RORd) RORd_Disasm(info);
|
||||
// else if (Opcodes[op] == ASLd0) ASLd0_Disasm(info);
|
||||
// else if (Opcodes[op] == ASRd0) ASRd0_Disasm(info);
|
||||
// else if (Opcodes[op] == LSLd0) LSLd0_Disasm(info);
|
||||
// else if (Opcodes[op] == LSRd0) LSRd0_Disasm(info);
|
||||
// else if (Opcodes[op] == ROXLd0) ROXLd0_Disasm(info);
|
||||
// else if (Opcodes[op] == ROXRd0) ROXRd0_Disasm(info);
|
||||
// else if (Opcodes[op] == ROLd0) ROLd0_Disasm(info);
|
||||
// else if (Opcodes[op] == RORd0) RORd0_Disasm(info);
|
||||
// else if (Opcodes[op] == SWAP) SWAP_Disasm(info);
|
||||
// else if (Opcodes[op] == AND0) AND0_Disasm(info);
|
||||
// else if (Opcodes[op] == AND1) AND1_Disasm(info);
|
||||
// else if (Opcodes[op] == EOR) EOR_Disasm(info);
|
||||
// else if (Opcodes[op] == OR0) OR0_Disasm(info);
|
||||
// else if (Opcodes[op] == OR1) OR1_Disasm(info);
|
||||
// else if (Opcodes[op] == NOT) NOT_Disasm(info);
|
||||
// else if (Opcodes[op] == NEG) NEG_Disasm(info);
|
||||
// else if (Opcodes[op] == JMP) JMP_Disasm(info);
|
||||
// else if (Opcodes[op] == JSR) JSR_Disasm(info);
|
||||
// else if (Opcodes[op] == Bcc) Bcc_Disasm(info);
|
||||
// else if (Opcodes[op] == BRA) BRA_Disasm(info);
|
||||
// else if (Opcodes[op] == BSR) BSR_Disasm(info);
|
||||
// else if (Opcodes[op] == DBcc) DBcc_Disasm(info);
|
||||
// else if (Opcodes[op] == Scc) Scc_Disasm(info);
|
||||
// else if (Opcodes[op] == RTE) RTE_Disasm(info);
|
||||
// else if (Opcodes[op] == RTS) RTS_Disasm(info);
|
||||
// else if (Opcodes[op] == RTR) RTR_Disasm(info);
|
||||
// else if (Opcodes[op] == TST) TST_Disasm(info);
|
||||
// else if (Opcodes[op] == BTSTi) BTSTi_Disasm(info);
|
||||
// else if (Opcodes[op] == BTSTr) BTSTr_Disasm(info);
|
||||
// else if (Opcodes[op] == BCHGi) BCHGi_Disasm(info);
|
||||
// else if (Opcodes[op] == BCHGr) BCHGr_Disasm(info);
|
||||
// else if (Opcodes[op] == BCLRi) BCLRi_Disasm(info);
|
||||
// else if (Opcodes[op] == BCLRr) BCLRr_Disasm(info);
|
||||
// else if (Opcodes[op] == BSETi) BSETi_Disasm(info);
|
||||
// else if (Opcodes[op] == BSETr) BSETr_Disasm(info);
|
||||
// else if (Opcodes[op] == LINK) LINK_Disasm(info);
|
||||
// else if (Opcodes[op] == UNLK) UNLK_Disasm(info);
|
||||
// else if (Opcodes[op] == RESET) RESET_Disasm(info);
|
||||
// else if (Opcodes[op] == NOP) NOP_Disasm(info);
|
||||
// else if (Opcodes[op] == ADD0) ADD_Disasm(info);
|
||||
// else if (Opcodes[op] == ADD1) ADD_Disasm(info);
|
||||
// else if (Opcodes[op] == ADDA) ADDA_Disasm(info);
|
||||
// else if (Opcodes[op] == ADDI) ADDI_Disasm(info);
|
||||
// else if (Opcodes[op] == ADDQ) ADDQ_Disasm(info);
|
||||
// else if (Opcodes[op] == SUB0) SUB_Disasm(info);
|
||||
// else if (Opcodes[op] == SUB1) SUB_Disasm(info);
|
||||
// else if (Opcodes[op] == SUBA) SUBA_Disasm(info);
|
||||
// else if (Opcodes[op] == SUBI) SUBI_Disasm(info);
|
||||
// else if (Opcodes[op] == SUBQ) SUBQ_Disasm(info);
|
||||
// else if (Opcodes[op] == CMP) CMP_Disasm(info);
|
||||
// else if (Opcodes[op] == CMPM) CMPM_Disasm(info);
|
||||
// else if (Opcodes[op] == CMPA) CMPA_Disasm(info);
|
||||
// else if (Opcodes[op] == CMPI) CMPI_Disasm(info);
|
||||
// else if (Opcodes[op] == MULU) MULU_Disasm(info);
|
||||
// else if (Opcodes[op] == MULS) MULS_Disasm(info);
|
||||
// else if (Opcodes[op] == DIVU) DIVU_Disasm(info);
|
||||
// else if (Opcodes[op] == DIVS) DIVS_Disasm(info);
|
||||
// else if (Opcodes[op] == MOVEtSR) MOVEtSR_Disasm(info);//
|
||||
// else if (Opcodes[op] == MOVEfSR) MOVEfSR_Disasm(info);
|
||||
// else if (Opcodes[op] == MOVEUSP) MOVEUSP_Disasm(info);
|
||||
// else if (Opcodes[op] == ANDI_SR) ANDI_SR_Disasm(info);
|
||||
// else if (Opcodes[op] == EORI_SR) EORI_SR_Disasm(info);
|
||||
// else if (Opcodes[op] == ORI_SR) ORI_SR_Disasm(info);
|
||||
// else if (Opcodes[op] == MOVECCR) MOVECCR_Disasm(info);
|
||||
// else if (Opcodes[op] == TRAP) TRAP_Disasm(info);
|
||||
// else if (Opcodes[op] == NBCD) NBCD_Disasm(info);
|
||||
// else if (Opcodes[op] == ILLEGAL) ILLEGAL_Disasm(info);
|
||||
// else if (Opcodes[op] == STOP) STOP_Disasm(info);
|
||||
// else if (Opcodes[op] == TRAPV) TRAPV_Disasm(info);
|
||||
// else if (Opcodes[op] == CHK) CHK_Disasm(info);
|
||||
// else if (Opcodes[op] == NEGX) NEGX_Disasm(info);
|
||||
// else if (Opcodes[op] == SBCD0) SBCD0_Disasm(info);
|
||||
// else if (Opcodes[op] == SBCD1) SBCD1_Disasm(info);
|
||||
// else if (Opcodes[op] == ABCD0) ABCD0_Disasm(info);
|
||||
// else if (Opcodes[op] == ABCD1) ABCD1_Disasm(info);
|
||||
// else if (Opcodes[op] == EXGdd) EXGdd_Disasm(info);
|
||||
// else if (Opcodes[op] == EXGaa) EXGaa_Disasm(info);
|
||||
// else if (Opcodes[op] == EXGda) EXGda_Disasm(info);
|
||||
// else if (Opcodes[op] == TAS) TAS_Disasm(info);
|
||||
// else if (Opcodes[op] == MOVEP) MOVEP_Disasm(info);
|
||||
// else if (Opcodes[op] == ADDX0) ADDX0_Disasm(info);
|
||||
// else if (Opcodes[op] == ADDX1) ADDX1_Disasm(info);
|
||||
// else if (Opcodes[op] == SUBX0) SUBX0_Disasm(info);
|
||||
// else if (Opcodes[op] == SUBX1) SUBX1_Disasm(info);
|
||||
// else if (Opcodes[op] == ILL) ILL_Disasm(info);
|
||||
|
||||
// var sb = new StringBuilder();
|
||||
// for (int p = info.PC; p < info.PC + info.Length; p += 2)
|
||||
// {
|
||||
// sb.AppendFormat("{0:X4} ", ReadOpWord(p));
|
||||
// }
|
||||
// info.RawBytes = sb.ToString();
|
||||
// return info;
|
||||
//}
|
||||
}
|
||||
}
|
||||
@ -1,11 +0,0 @@
|
||||
fileFormatVersion: 2
|
||||
guid: 59a132d3fbbd20c488b17cf0b0bedd22
|
||||
MonoImporter:
|
||||
externalObjects: {}
|
||||
serializedVersion: 2
|
||||
defaultReferences: []
|
||||
executionOrder: 0
|
||||
icon: {instanceID: 0}
|
||||
userData:
|
||||
assetBundleName:
|
||||
assetBundleVariant:
|
||||
@ -44,33 +44,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void AND0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int dstReg = (op >> 9) & 0x07;
|
||||
int size = (op >> 6) & 0x03;
|
||||
int srcMode = (op >> 3) & 0x07;
|
||||
int srcReg = op & 0x07;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: // Byte
|
||||
info.Mnemonic = "and.b";
|
||||
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 1, ref pc), dstReg);
|
||||
break;
|
||||
case 1: // Word
|
||||
info.Mnemonic = "and.w";
|
||||
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 2, ref pc), dstReg);
|
||||
break;
|
||||
case 2: // Long
|
||||
info.Mnemonic = "and.l";
|
||||
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 4, ref pc), dstReg);
|
||||
break;
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void AND1() // AND Dn, <ea>
|
||||
{
|
||||
@ -117,33 +90,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void AND1_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int srcReg = (op >> 9) & 0x07;
|
||||
int size = (op >> 6) & 0x03;
|
||||
int dstMode = (op >> 3) & 0x07;
|
||||
int dstReg = op & 0x07;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: // Byte
|
||||
info.Mnemonic = "and.b";
|
||||
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 1, ref pc));
|
||||
break;
|
||||
case 1: // Word
|
||||
info.Mnemonic = "and.w";
|
||||
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 2, ref pc));
|
||||
break;
|
||||
case 2: // Long
|
||||
info.Mnemonic = "and.l";
|
||||
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 4, ref pc));
|
||||
break;
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ANDI() // ANDI #<data>, <ea>
|
||||
{
|
||||
@ -192,44 +138,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ANDI_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int size = ((op >> 6) & 0x03);
|
||||
int dstMode = ((op >> 3) & 0x07);
|
||||
int dstReg = (op & 0x07);
|
||||
|
||||
int pc = info.PC + 2;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: // Byte
|
||||
{
|
||||
info.Mnemonic = "andi.b";
|
||||
sbyte imm = (sbyte)ReadOpWord(pc); pc += 2;
|
||||
info.Args = string.Format("${0:X}, ", imm);
|
||||
info.Args += DisassembleValue(dstMode, dstReg, 1, ref pc);
|
||||
break;
|
||||
}
|
||||
case 1: // Word
|
||||
{
|
||||
info.Mnemonic = "andi.w";
|
||||
short imm = ReadOpWord(pc); pc += 2;
|
||||
info.Args = string.Format("${0:X}, ", imm);
|
||||
info.Args += DisassembleValue(dstMode, dstReg, 2, ref pc);
|
||||
break;
|
||||
}
|
||||
case 2: // Long
|
||||
{
|
||||
info.Mnemonic = "andi.l";
|
||||
int imm = ReadOpLong(pc); pc += 4;
|
||||
info.Args = string.Format("${0:X}, ", imm);
|
||||
info.Args += DisassembleValue(dstMode, dstReg, 4, ref pc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ANDI_CCR() //m68k_op_andi_16_toc , 0xffff, 0x023c, { 20}
|
||||
{
|
||||
@ -239,13 +147,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 20;
|
||||
}
|
||||
|
||||
void ANDI_CCR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "andi";
|
||||
info.Args = DisassembleImmediate(1, ref pc) + ", CCR";
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void EOR() // EOR Dn, <ea>
|
||||
{
|
||||
@ -292,33 +193,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void EOR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int srcReg = (op >> 9) & 0x07;
|
||||
int size = (op >> 6) & 0x03;
|
||||
int dstMode = (op >> 3) & 0x07;
|
||||
int dstReg = op & 0x07;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: // Byte
|
||||
info.Mnemonic = "eor.b";
|
||||
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 1, ref pc));
|
||||
break;
|
||||
case 1: // Word
|
||||
info.Mnemonic = "eor.w";
|
||||
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 2, ref pc));
|
||||
break;
|
||||
case 2: // Long
|
||||
info.Mnemonic = "eor.l";
|
||||
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 4, ref pc));
|
||||
break;
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void EORI()
|
||||
{
|
||||
@ -364,40 +238,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void EORI_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: // byte
|
||||
{
|
||||
info.Mnemonic = "eori.b";
|
||||
sbyte immed = (sbyte)ReadOpWord(pc); pc += 2;
|
||||
info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 1, ref pc));
|
||||
break;
|
||||
}
|
||||
case 1: // word
|
||||
{
|
||||
info.Mnemonic = "eori.w";
|
||||
short immed = ReadOpWord(pc); pc += 2;
|
||||
info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 2, ref pc));
|
||||
break;
|
||||
}
|
||||
case 2: // long
|
||||
{
|
||||
info.Mnemonic = "eori.l";
|
||||
int immed = ReadOpLong(pc); pc += 4;
|
||||
info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 4, ref pc));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void EORI_CCR()//m68k_op_eori_16_toc , 0xffff, 0x0a3c, { 20}
|
||||
{
|
||||
@ -408,13 +248,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 20;
|
||||
}
|
||||
|
||||
void EORI_CCR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "eori";
|
||||
info.Args = DisassembleImmediate(1, ref pc) + ", CCR";
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void OR0() // OR <ea>, Dn
|
||||
{
|
||||
@ -456,33 +289,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void OR0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int dstReg = (op >> 9) & 0x07;
|
||||
int size = (op >> 6) & 0x03;
|
||||
int srcMode = (op >> 3) & 0x07;
|
||||
int srcReg = op & 0x07;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: // Byte
|
||||
info.Mnemonic = "or.b";
|
||||
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 1, ref pc), dstReg);
|
||||
break;
|
||||
case 1: // Word
|
||||
info.Mnemonic = "or.w";
|
||||
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 2, ref pc), dstReg);
|
||||
break;
|
||||
case 2: // Long
|
||||
info.Mnemonic = "or.l";
|
||||
info.Args = string.Format("{0}, D{1}", DisassembleValue(srcMode, srcReg, 4, ref pc), dstReg);
|
||||
break;
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void OR1() // OR Dn, <ea>
|
||||
{
|
||||
@ -529,33 +335,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void OR1_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int srcReg = (op >> 9) & 0x07;
|
||||
int size = (op >> 6) & 0x03;
|
||||
int dstMode = (op >> 3) & 0x07;
|
||||
int dstReg = op & 0x07;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: // Byte
|
||||
info.Mnemonic = "or.b";
|
||||
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 1, ref pc));
|
||||
break;
|
||||
case 1: // Word
|
||||
info.Mnemonic = "or.w";
|
||||
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 2, ref pc));
|
||||
break;
|
||||
case 2: // Long
|
||||
info.Mnemonic = "or.l";
|
||||
info.Args = string.Format("D{0}, {1}", srcReg, DisassembleValue(dstMode, dstReg, 4, ref pc));
|
||||
break;
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ORI()
|
||||
{
|
||||
@ -601,40 +380,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ORI_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: // byte
|
||||
{
|
||||
info.Mnemonic = "ori.b";
|
||||
sbyte immed = (sbyte)ReadOpWord(pc); pc += 2;
|
||||
info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 1, ref pc));
|
||||
break;
|
||||
}
|
||||
case 1: // word
|
||||
{
|
||||
info.Mnemonic = "ori.w";
|
||||
short immed = ReadOpWord(pc); pc += 2;
|
||||
info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 2, ref pc));
|
||||
break;
|
||||
}
|
||||
case 2: // long
|
||||
{
|
||||
info.Mnemonic = "ori.l";
|
||||
int immed = ReadOpLong(pc); pc += 4;
|
||||
info.Args = String.Format("${0:X}, {1}", immed, DisassembleValue(mode, reg, 4, ref pc));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ORI_CCR()//m68k_op_ori_16_toc , 0xffff, 0x003c, { 20}
|
||||
{
|
||||
@ -644,13 +389,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 20;
|
||||
}
|
||||
|
||||
void ORI_CCR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "ori";
|
||||
info.Args = DisassembleImmediate(1, ref pc) + ", CCR";
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void NOT()
|
||||
{
|
||||
@ -696,32 +434,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void NOT_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int size = (op >> 6) & 0x03;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: // Byte
|
||||
info.Mnemonic = "not.b";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
break;
|
||||
case 1: // Word
|
||||
info.Mnemonic = "not.w";
|
||||
info.Args = DisassembleValue(mode, reg, 2, ref pc);
|
||||
break;
|
||||
case 2: // Long
|
||||
info.Mnemonic = "not.l";
|
||||
info.Args = DisassembleValue(mode, reg, 4, ref pc);
|
||||
break;
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void LSLd()
|
||||
{
|
||||
@ -771,27 +483,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void LSLd_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int rot = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int m = (op >> 5) & 1;
|
||||
int reg = op & 7;
|
||||
|
||||
if (m == 0 && rot == 0) rot = 8;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "lsl.b"; break;
|
||||
case 1: info.Mnemonic = "lsl.w"; break;
|
||||
case 2: info.Mnemonic = "lsl.l"; break;
|
||||
}
|
||||
if (m == 0) info.Args = rot + ", D" + reg;
|
||||
else info.Args = "D" + rot + ", D" + reg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void LSLd0()
|
||||
{
|
||||
@ -816,15 +507,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 8 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void LSLd0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
info.Mnemonic = "lsl";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void LSRd()
|
||||
{
|
||||
@ -874,27 +556,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void LSRd_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int rot = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int m = (op >> 5) & 1;
|
||||
int reg = op & 7;
|
||||
|
||||
if (m == 0 && rot == 0) rot = 8;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "lsr.b"; break;
|
||||
case 1: info.Mnemonic = "lsr.w"; break;
|
||||
case 2: info.Mnemonic = "lsr.l"; break;
|
||||
}
|
||||
if (m == 0) info.Args = rot + ", D" + reg;
|
||||
else info.Args = "D" + rot + ", D" + reg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void LSRd0()
|
||||
{
|
||||
@ -920,15 +581,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 8 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void LSRd0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
info.Mnemonic = "lsr";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ASLd()
|
||||
{
|
||||
@ -984,27 +636,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ASLd_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int rot = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int m = (op >> 5) & 1;
|
||||
int reg = op & 7;
|
||||
|
||||
if (m == 0 && rot == 0) rot = 8;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "asl.b"; break;
|
||||
case 1: info.Mnemonic = "asl.w"; break;
|
||||
case 2: info.Mnemonic = "asl.l"; break;
|
||||
}
|
||||
if (m == 0) info.Args = rot + ", D" + reg;
|
||||
else info.Args = "D" + rot + ", D" + reg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ASLd0()
|
||||
{
|
||||
@ -1030,15 +661,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 8 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void ASLd0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
info.Mnemonic = "asl";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ASRd()
|
||||
{
|
||||
@ -1094,27 +716,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ASRd_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int rot = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int m = (op >> 5) & 1;
|
||||
int reg = op & 7;
|
||||
|
||||
if (m == 0 && rot == 0) rot = 8;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "asr.b"; break;
|
||||
case 1: info.Mnemonic = "asr.w"; break;
|
||||
case 2: info.Mnemonic = "asr.l"; break;
|
||||
}
|
||||
if (m == 0) info.Args = rot + ", D" + reg;
|
||||
else info.Args = "D" + rot + ", D" + reg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ASRd0()
|
||||
{
|
||||
@ -1143,15 +744,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 8 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void ASRd0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
info.Mnemonic = "asr";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ROLd()
|
||||
{
|
||||
@ -1201,27 +793,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ROLd_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int rot = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int m = (op >> 5) & 1;
|
||||
int reg = op & 7;
|
||||
|
||||
if (m == 0 && rot == 0) rot = 8;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "rol.b"; break;
|
||||
case 1: info.Mnemonic = "rol.w"; break;
|
||||
case 2: info.Mnemonic = "rol.l"; break;
|
||||
}
|
||||
if (m == 0) info.Args = rot + ", D" + reg;
|
||||
else info.Args = "D" + rot + ", D" + reg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ROLd0()
|
||||
{
|
||||
@ -1246,15 +817,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 8 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void ROLd0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
info.Mnemonic = "rol";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void RORd()
|
||||
{
|
||||
@ -1304,27 +866,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void RORd_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int rot = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int m = (op >> 5) & 1;
|
||||
int reg = op & 7;
|
||||
|
||||
if (m == 0 && rot == 0) rot = 8;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "ror.b"; break;
|
||||
case 1: info.Mnemonic = "ror.w"; break;
|
||||
case 2: info.Mnemonic = "ror.l"; break;
|
||||
}
|
||||
if (m == 0) info.Args = rot + ", D" + reg;
|
||||
else info.Args = "D" + rot + ", D" + reg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void RORd0()
|
||||
{
|
||||
@ -1349,15 +890,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 8 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void RORd0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
info.Mnemonic = "ror";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ROXLd()
|
||||
{
|
||||
@ -1410,27 +942,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ROXLd_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int rot = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int m = (op >> 5) & 1;
|
||||
int reg = op & 7;
|
||||
|
||||
if (m == 0 && rot == 0) rot = 8;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "roxl.b"; break;
|
||||
case 1: info.Mnemonic = "roxl.w"; break;
|
||||
case 2: info.Mnemonic = "roxl.l"; break;
|
||||
}
|
||||
if (m == 0) info.Args = rot + ", D" + reg;
|
||||
else info.Args = "D" + rot + ", D" + reg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ROXLd0()
|
||||
{
|
||||
@ -1457,15 +968,7 @@ namespace cpu.m68000
|
||||
pendingCycles -= 8 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void ROXLd0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
info.Mnemonic = "roxl";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
|
||||
void ROXRd()
|
||||
{
|
||||
@ -1518,28 +1021,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ROXRd_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int rot = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int m = (op >> 5) & 1;
|
||||
int reg = op & 7;
|
||||
|
||||
if (m == 0 && rot == 0) rot = 8;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "roxr.b"; break;
|
||||
case 1: info.Mnemonic = "roxr.w"; break;
|
||||
case 2: info.Mnemonic = "roxr.l"; break;
|
||||
}
|
||||
if (m == 0) info.Args = rot + ", D" + reg;
|
||||
else info.Args = "D" + rot + ", D" + reg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ROXRd0()
|
||||
{
|
||||
//m68k_op_roxr_16_ai , 0xfff8, 0xe4d0, { 12}
|
||||
@ -1566,15 +1047,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 8 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void ROXRd0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
info.Mnemonic = "roxr";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void SWAP()
|
||||
{
|
||||
@ -1586,11 +1058,5 @@ namespace cpu.m68000
|
||||
pendingCycles -= 4;
|
||||
}
|
||||
|
||||
void SWAP_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int reg = op & 7;
|
||||
info.Mnemonic = "swap";
|
||||
info.Args = "D" + reg;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -41,36 +41,6 @@ namespace cpu.m68000
|
||||
Z = (value == 0);
|
||||
}
|
||||
|
||||
void MOVE_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = ((op >> 12) & 0x03);
|
||||
int dstMode = ((op >> 6) & 0x07);
|
||||
int dstReg = ((op >> 9) & 0x07);
|
||||
int srcMode = ((op >> 3) & 0x07);
|
||||
int srcReg = (op & 0x07);
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 1:
|
||||
info.Mnemonic = "move.b";
|
||||
info.Args = DisassembleValue(srcMode, srcReg, 1, ref pc) + ", ";
|
||||
info.Args += DisassembleValue(dstMode, dstReg, 1, ref pc);
|
||||
break;
|
||||
case 3:
|
||||
info.Mnemonic = "move.w";
|
||||
info.Args = DisassembleValue(srcMode, srcReg, 2, ref pc) + ", ";
|
||||
info.Args += DisassembleValue(dstMode, dstReg, 2, ref pc);
|
||||
break;
|
||||
case 2:
|
||||
info.Mnemonic = "move.l";
|
||||
info.Args = DisassembleValue(srcMode, srcReg, 4, ref pc) + ", ";
|
||||
info.Args += DisassembleValue(dstMode, dstReg, 4, ref pc);
|
||||
break;
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void MOVEA()
|
||||
{
|
||||
@ -131,26 +101,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void MOVEA_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = ((op >> 12) & 0x03);
|
||||
int dstReg = ((op >> 9) & 0x07);
|
||||
int srcMode = ((op >> 3) & 0x07);
|
||||
int srcReg = (op & 0x07);
|
||||
|
||||
if (size == 3)
|
||||
{
|
||||
info.Mnemonic = "movea.w";
|
||||
info.Args = DisassembleValue(srcMode, srcReg, 2, ref pc) + ", A" + dstReg;
|
||||
}
|
||||
else
|
||||
{
|
||||
info.Mnemonic = "movea.l";
|
||||
info.Args = DisassembleValue(srcMode, srcReg, 4, ref pc) + ", A" + dstReg;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void MOVEP()
|
||||
{
|
||||
@ -196,39 +146,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void MOVEP_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dReg = ((op >> 9) & 0x07);
|
||||
int dir = ((op >> 7) & 0x01);
|
||||
int size = ((op >> 6) & 0x01);
|
||||
int aReg = (op & 0x07);
|
||||
if (size == 0)
|
||||
{
|
||||
info.Mnemonic = "movep.w";
|
||||
if (dir == 0)
|
||||
{
|
||||
info.Args = DisassembleValue(5, aReg, 2, ref pc) + ", D" + dReg;
|
||||
}
|
||||
else if (dir == 1)
|
||||
{
|
||||
info.Args = "D" + dReg + ", " + DisassembleValue(5, aReg, 2, ref pc);
|
||||
}
|
||||
}
|
||||
else if (size == 1)
|
||||
{
|
||||
info.Mnemonic = "movep.l";
|
||||
if (dir == 0)
|
||||
{
|
||||
info.Args = DisassembleValue(5, aReg, 4, ref pc) + ", D" + dReg;
|
||||
}
|
||||
else if (dir == 1)
|
||||
{
|
||||
info.Args = "D" + dReg + ", " + DisassembleValue(5, aReg, 4, ref pc);
|
||||
}
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void MOVEQ()
|
||||
{
|
||||
@ -241,11 +158,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 4;
|
||||
}
|
||||
|
||||
void MOVEQ_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
info.Mnemonic = "moveq";
|
||||
info.Args = String.Format("${0:X}, D{1}", (int)((sbyte)op), (op >> 9) & 7);
|
||||
}
|
||||
|
||||
static string DisassembleRegisterList0(ushort registers)
|
||||
{
|
||||
@ -434,20 +346,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void MOVEM0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = (op >> 6) & 1;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
ushort registers = (ushort)ReadOpWord(pc); pc += 2;
|
||||
string address = DisassembleAddress(mode, reg, ref pc);
|
||||
|
||||
info.Mnemonic = size == 0 ? "movem.w" : "movem.l";
|
||||
info.Args = DisassembleRegisterList0(registers) + ", " + address;
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void MOVEM1()
|
||||
{
|
||||
@ -562,21 +460,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void MOVEM1_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = (op >> 6) & 1;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
ushort registers = (ushort)ReadOpWord(pc); pc += 2;
|
||||
string address = DisassembleAddress(mode, reg, ref pc);
|
||||
|
||||
info.Mnemonic = size == 0 ? "movem.w" : "movem.l";
|
||||
info.Args = address + ", " + DisassembleRegisterList1(registers);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void LEA()
|
||||
{
|
||||
int mode = (op >> 3) & 7;
|
||||
@ -601,19 +484,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void LEA_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int sReg = (op >> 0) & 7;
|
||||
int dReg = (op >> 9) & 7;
|
||||
|
||||
info.Mnemonic = "lea";
|
||||
info.Args = DisassembleAddress(mode, sReg, ref pc);
|
||||
info.Args += ", A" + dReg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void CLR()
|
||||
{
|
||||
@ -634,21 +504,6 @@ namespace cpu.m68000
|
||||
Z = true;
|
||||
}
|
||||
|
||||
void CLR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "clr.b"; info.Args = DisassembleValue(mode, reg, 1, ref pc); break;
|
||||
case 1: info.Mnemonic = "clr.w"; info.Args = DisassembleValue(mode, reg, 2, ref pc); break;
|
||||
case 2: info.Mnemonic = "clr.l"; info.Args = DisassembleValue(mode, reg, 4, ref pc); break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void EXT()
|
||||
{
|
||||
@ -674,17 +529,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 4;
|
||||
}
|
||||
|
||||
void EXT_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int size = (op >> 6) & 1;
|
||||
int reg = op & 7;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "ext.w"; info.Args = "D" + reg; break;
|
||||
case 1: info.Mnemonic = "ext.l"; info.Args = "D" + reg; break;
|
||||
}
|
||||
}
|
||||
|
||||
void PEA()
|
||||
{
|
||||
@ -712,15 +556,5 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void PEA_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
info.Mnemonic = "pea";
|
||||
info.Args = DisassembleAddress(mode, reg, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -113,27 +113,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ADD_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int Dreg = (op >> 9) & 7;
|
||||
int dir = (op >> 8) & 1;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
string op1 = "D" + Dreg;
|
||||
string op2;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "add.b"; op2 = DisassembleValue(mode, reg, 1, ref pc); break;
|
||||
case 1: info.Mnemonic = "add.w"; op2 = DisassembleValue(mode, reg, 2, ref pc); break;
|
||||
default: info.Mnemonic = "add.l"; op2 = DisassembleValue(mode, reg, 4, ref pc); break;
|
||||
}
|
||||
info.Args = dir == 0 ? (op2 + ", " + op1) : (op1 + ", " + op2);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ADDI()
|
||||
{
|
||||
@ -193,30 +172,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ADDI_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
info.Mnemonic = "addi.b";
|
||||
info.Args = DisassembleImmediate(1, ref pc) + ", " + DisassembleValue(mode, reg, 1, ref pc);
|
||||
break;
|
||||
case 1:
|
||||
info.Mnemonic = "addi.w";
|
||||
info.Args = DisassembleImmediate(2, ref pc) + ", " + DisassembleValue(mode, reg, 2, ref pc);
|
||||
break;
|
||||
case 2:
|
||||
info.Mnemonic = "addi.l";
|
||||
info.Args = DisassembleImmediate(4, ref pc) + ", " + DisassembleValue(mode, reg, 4, ref pc);
|
||||
break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ADDQ()
|
||||
{
|
||||
@ -290,24 +245,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ADDQ_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int data = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
data = data == 0 ? 8 : data; // range is 1-8; 0 represents 8
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "addq.b"; info.Args = data + ", " + DisassembleValue(mode, reg, 1, ref pc); break;
|
||||
case 1: info.Mnemonic = "addq.w"; info.Args = data + ", " + DisassembleValue(mode, reg, 2, ref pc); break;
|
||||
case 2: info.Mnemonic = "addq.l"; info.Args = data + ", " + DisassembleValue(mode, reg, 4, ref pc); break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ADDA()
|
||||
{
|
||||
@ -333,19 +270,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ADDA_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int aReg = (op >> 9) & 7;
|
||||
int size = (op >> 8) & 1;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
info.Mnemonic = (size == 0) ? "adda.w" : "adda.l";
|
||||
info.Args = DisassembleValue(mode, reg, (size == 0) ? 2 : 4, ref pc) + ", A" + aReg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void SUB0()
|
||||
{
|
||||
@ -456,27 +380,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void SUB_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dReg = (op >> 9) & 7;
|
||||
int dir = (op >> 8) & 1;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
string op1 = "D" + dReg;
|
||||
string op2;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "sub.b"; op2 = DisassembleValue(mode, reg, 1, ref pc); break;
|
||||
case 1: info.Mnemonic = "sub.w"; op2 = DisassembleValue(mode, reg, 2, ref pc); break;
|
||||
default: info.Mnemonic = "sub.l"; op2 = DisassembleValue(mode, reg, 4, ref pc); break;
|
||||
}
|
||||
info.Args = dir == 0 ? (op2 + ", " + op1) : (op1 + ", " + op2);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void SUBI()
|
||||
{
|
||||
@ -533,30 +436,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void SUBI_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
info.Mnemonic = "subi.b";
|
||||
info.Args = DisassembleImmediate(1, ref pc) + ", " + DisassembleValue(mode, reg, 1, ref pc);
|
||||
break;
|
||||
case 1:
|
||||
info.Mnemonic = "subi.w";
|
||||
info.Args = DisassembleImmediate(2, ref pc) + ", " + DisassembleValue(mode, reg, 2, ref pc);
|
||||
break;
|
||||
case 2:
|
||||
info.Mnemonic = "subi.l";
|
||||
info.Args = DisassembleImmediate(4, ref pc) + ", " + DisassembleValue(mode, reg, 4, ref pc);
|
||||
break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void SUBQ()
|
||||
{
|
||||
@ -627,24 +506,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void SUBQ_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int data = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
data = data == 0 ? 8 : data; // range is 1-8; 0 represents 8
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "subq.b"; info.Args = data + ", " + DisassembleValue(mode, reg, 1, ref pc); break;
|
||||
case 1: info.Mnemonic = "subq.w"; info.Args = data + ", " + DisassembleValue(mode, reg, 2, ref pc); break;
|
||||
case 2: info.Mnemonic = "subq.l"; info.Args = data + ", " + DisassembleValue(mode, reg, 4, ref pc); break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void SUBA()
|
||||
{
|
||||
@ -670,20 +531,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void SUBA_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
|
||||
int aReg = (op >> 9) & 7;
|
||||
int size = (op >> 8) & 1;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
info.Mnemonic = (size == 0) ? "suba.w" : "suba.l";
|
||||
info.Args = DisassembleValue(mode, reg, (size == 0) ? 2 : 4, ref pc) + ", A" + aReg;
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void NEG()
|
||||
{
|
||||
@ -739,32 +586,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void NEG_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int size = (op >> 6) & 0x03;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: // Byte
|
||||
info.Mnemonic = "neg.b";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
break;
|
||||
case 1: // Word
|
||||
info.Mnemonic = "neg.w";
|
||||
info.Args = DisassembleValue(mode, reg, 2, ref pc);
|
||||
break;
|
||||
case 2: // Long
|
||||
info.Mnemonic = "neg.l";
|
||||
info.Args = DisassembleValue(mode, reg, 4, ref pc);
|
||||
break;
|
||||
}
|
||||
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void NBCD()
|
||||
{
|
||||
@ -795,15 +616,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= (mode == 0) ? 6 : 8 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void NBCD_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
info.Mnemonic = "nbcd.b";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ILLEGAL()
|
||||
{
|
||||
@ -811,22 +623,12 @@ namespace cpu.m68000
|
||||
pendingCycles -= 4;
|
||||
}
|
||||
|
||||
void ILLEGAL_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
info.Mnemonic = "illegal";
|
||||
info.Args = "";
|
||||
}
|
||||
|
||||
void ILL()
|
||||
{
|
||||
TrapVector2(4);
|
||||
}
|
||||
|
||||
void ILL_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
info.Mnemonic = "ill";
|
||||
info.Args = "";
|
||||
}
|
||||
|
||||
void STOP()
|
||||
{
|
||||
@ -844,13 +646,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 4;
|
||||
}
|
||||
|
||||
void STOP_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "stop";
|
||||
info.Args = DisassembleImmediate(2, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void TRAPV()
|
||||
{
|
||||
@ -865,11 +660,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void TRAPV_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
info.Mnemonic = "trapv";
|
||||
info.Args = "";
|
||||
}
|
||||
|
||||
void CHK()
|
||||
{
|
||||
@ -894,16 +684,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void CHK_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dreg = (op >> 9) & 7;
|
||||
int mode = (op >> 3) & 0x07;
|
||||
int reg = op & 0x07;
|
||||
info.Mnemonic = "chk.w";
|
||||
info.Args = String.Format("{0}, D{1}", DisassembleValue(mode, reg, 2, ref pc), dreg);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void NEGX()
|
||||
{
|
||||
@ -959,20 +739,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void NEGX_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "negx.b"; info.Args = DisassembleValue(mode, reg, 1, ref pc); break;
|
||||
case 1: info.Mnemonic = "negx.w"; info.Args = DisassembleValue(mode, reg, 2, ref pc); break;
|
||||
case 2: info.Mnemonic = "negx.l"; info.Args = DisassembleValue(mode, reg, 4, ref pc); break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void SBCD0()
|
||||
{
|
||||
@ -1004,15 +770,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 6;
|
||||
}
|
||||
|
||||
void SBCD0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dstReg = (op >> 9) & 0x07;
|
||||
int srcReg = op & 0x07;
|
||||
info.Mnemonic = "sbcd.b";
|
||||
info.Args = DisassembleValue(0, srcReg, 1, ref pc) + "," + DisassembleValue(0, dstReg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void SBCD1()
|
||||
{
|
||||
@ -1060,15 +817,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 18;
|
||||
}
|
||||
|
||||
void SBCD1_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dstReg = (op >> 9) & 0x07;
|
||||
int srcReg = op & 0x07;
|
||||
info.Mnemonic = "sbcd.b";
|
||||
info.Args = DisassembleValue(4, srcReg, 1, ref pc) + "," + DisassembleValue(4, dstReg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ABCD0()
|
||||
{
|
||||
@ -1097,15 +845,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 6;
|
||||
}
|
||||
|
||||
void ABCD0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dstReg = (op >> 9) & 0x07;
|
||||
int srcReg = op & 0x07;
|
||||
info.Mnemonic = "abcd.b";
|
||||
info.Args = DisassembleValue(0, srcReg, 1, ref pc) + "," + DisassembleValue(0, dstReg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ABCD1()
|
||||
{
|
||||
@ -1150,15 +889,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 18;
|
||||
}
|
||||
|
||||
void ABCD1_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dstReg = (op >> 9) & 0x07;
|
||||
int srcReg = op & 0x07;
|
||||
info.Mnemonic = "abcd.b";
|
||||
info.Args = DisassembleValue(4, srcReg, 1, ref pc) + "," + DisassembleValue(4, dstReg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void EXGdd()
|
||||
{
|
||||
@ -1171,15 +901,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 6;
|
||||
}
|
||||
|
||||
void EXGdd_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int reg_a = (op >> 9) & 0x07;
|
||||
int reg_b = op & 0x07;
|
||||
info.Mnemonic = "exg";
|
||||
info.Args = DisassembleValue(0, reg_a, 1, ref pc) + "," + DisassembleValue(0, reg_b, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void EXGaa()
|
||||
{
|
||||
@ -1192,15 +913,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 6;
|
||||
}
|
||||
|
||||
void EXGaa_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int reg_a = (op >> 9) & 0x07;
|
||||
int reg_b = op & 0x07;
|
||||
info.Mnemonic = "exg";
|
||||
info.Args = DisassembleValue(1, reg_a, 1, ref pc) + "," + DisassembleValue(1, reg_b, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void EXGda()
|
||||
{
|
||||
@ -1213,15 +925,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 6;
|
||||
}
|
||||
|
||||
void EXGda_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int reg_a = (op >> 9) & 0x07;
|
||||
int reg_b = op & 0x07;
|
||||
info.Mnemonic = "exg";
|
||||
info.Args = DisassembleValue(0, reg_a, 1, ref pc) + "," + DisassembleValue(1, reg_b, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ADDX0()
|
||||
{
|
||||
@ -1277,29 +980,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ADDX0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dstReg = (op >> 9) & 0x07;
|
||||
int size = (op >> 6) & 0x03;
|
||||
int srcReg = op & 0x07;
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
info.Mnemonic = "addx.b";
|
||||
info.Args = DisassembleValue(0, srcReg, 1, ref pc) + ", D" + dstReg;
|
||||
break;
|
||||
case 1:
|
||||
info.Mnemonic = "addx.w";
|
||||
info.Args = DisassembleValue(0, srcReg, 2, ref pc) + ", D" + dstReg;
|
||||
break;
|
||||
case 2:
|
||||
info.Mnemonic = "addx.l";
|
||||
info.Args = DisassembleValue(0, srcReg, 4, ref pc) + ", D" + dstReg;
|
||||
break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ADDX1()
|
||||
{
|
||||
@ -1375,30 +1055,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void ADDX1_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dstReg = (op >> 9) & 0x07;
|
||||
int size = (op >> 6) & 0x03;
|
||||
int srcReg = op & 0x07;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
info.Mnemonic = "addx.b";
|
||||
info.Args = DisassembleValue(4, srcReg, 1, ref pc) + ", " + DisassembleValue(4, dstReg, 1, ref pc);
|
||||
break;
|
||||
case 1:
|
||||
info.Mnemonic = "addx.w";
|
||||
info.Args = DisassembleValue(4, srcReg, 2, ref pc) + ", " + DisassembleValue(4, dstReg, 2, ref pc);
|
||||
break;
|
||||
case 2:
|
||||
info.Mnemonic = "addx.l";
|
||||
info.Args = DisassembleValue(4, srcReg, 4, ref pc) + ", " + DisassembleValue(4, dstReg, 4, ref pc);
|
||||
break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void SUBX0()
|
||||
{
|
||||
@ -1454,29 +1110,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void SUBX0_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dstReg = (op >> 9) & 0x07;
|
||||
int size = (op >> 6) & 0x03;
|
||||
int srcReg = op & 0x07;
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
info.Mnemonic = "subx.b";
|
||||
info.Args = DisassembleValue(0, srcReg, 1, ref pc) + ", D" + dstReg;
|
||||
break;
|
||||
case 1:
|
||||
info.Mnemonic = "subx.w";
|
||||
info.Args = DisassembleValue(0, srcReg, 2, ref pc) + ", D" + dstReg;
|
||||
break;
|
||||
case 2:
|
||||
info.Mnemonic = "subx.l";
|
||||
info.Args = DisassembleValue(0, srcReg, 4, ref pc) + ", D" + dstReg;
|
||||
break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void SUBX1()
|
||||
{
|
||||
@ -1552,30 +1185,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void SUBX1_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dstReg = (op >> 9) & 0x07;
|
||||
int size = (op >> 6) & 0x03;
|
||||
int srcReg = op & 0x07;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
info.Mnemonic = "subx.b";
|
||||
info.Args = DisassembleValue(4, srcReg, 1, ref pc) + ", " + DisassembleValue(4, dstReg, 1, ref pc);
|
||||
break;
|
||||
case 1:
|
||||
info.Mnemonic = "subx.w";
|
||||
info.Args = DisassembleValue(4, srcReg, 2, ref pc) + ", " + DisassembleValue(4, dstReg, 2, ref pc);
|
||||
break;
|
||||
case 2:
|
||||
info.Mnemonic = "subx.l";
|
||||
info.Args = DisassembleValue(4, srcReg, 4, ref pc) + ", " + DisassembleValue(4, dstReg, 4, ref pc);
|
||||
break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void CMP()
|
||||
{
|
||||
@ -1625,32 +1234,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void CMP_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
|
||||
int dReg = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
info.Mnemonic = "cmp.b";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc) + ", D" + dReg;
|
||||
break;
|
||||
case 1:
|
||||
info.Mnemonic = "cmp.w";
|
||||
info.Args = DisassembleValue(mode, reg, 2, ref pc) + ", D" + dReg;
|
||||
break;
|
||||
case 2:
|
||||
info.Mnemonic = "cmp.l";
|
||||
info.Args = DisassembleValue(mode, reg, 4, ref pc) + ", D" + dReg;
|
||||
break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void CMPA()
|
||||
{
|
||||
@ -1688,28 +1271,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void CMPA_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
|
||||
int aReg = (op >> 9) & 7;
|
||||
int size = (op >> 8) & 1;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
info.Mnemonic = "cmpa.w";
|
||||
info.Args = DisassembleValue(mode, reg, 2, ref pc) + ", A" + aReg;
|
||||
break;
|
||||
case 1:
|
||||
info.Mnemonic = "cmpa.l";
|
||||
info.Args = DisassembleValue(mode, reg, 4, ref pc) + ", A" + aReg;
|
||||
break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void CMPM()
|
||||
{
|
||||
@ -1758,22 +1319,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void CMPM_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int axReg = (op >> 9) & 7;
|
||||
int size = (op >> 6) & 3;
|
||||
int ayReg = (op >> 0) & 7;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "cmpm.b"; break;
|
||||
case 1: info.Mnemonic = "cmpm.w"; break;
|
||||
case 2: info.Mnemonic = "cmpm.l"; break;
|
||||
}
|
||||
info.Args = string.Format("(A{0})+, (A{1})+", ayReg, axReg);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void CMPI()
|
||||
{
|
||||
@ -1825,34 +1370,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void CMPI_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
int immediate;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0:
|
||||
immediate = (byte)ReadOpWord(pc); pc += 2;
|
||||
info.Mnemonic = "cmpi.b";
|
||||
info.Args = String.Format("${0:X}, {1}", (sbyte)immediate, DisassembleValue(mode, reg, 1, ref pc));
|
||||
break;
|
||||
case 1:
|
||||
immediate = ReadOpWord(pc); pc += 2;
|
||||
info.Mnemonic = "cmpi.w";
|
||||
info.Args = String.Format("${0:X}, {1}", (short)immediate, DisassembleValue(mode, reg, 2, ref pc));
|
||||
break;
|
||||
case 2:
|
||||
immediate = ReadOpLong(pc); pc += 4;
|
||||
info.Mnemonic = "cmpi.l";
|
||||
info.Args = String.Format("${0:X}, {1}", immediate, DisassembleValue(mode, reg, 4, ref pc));
|
||||
break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void MULU()
|
||||
{
|
||||
@ -1871,17 +1388,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 54 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void MULU_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int dreg = (op >> 9) & 7;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "mulu";
|
||||
info.Args = String.Format("{0}, D{1}", DisassembleValue(mode, reg, 2, ref pc), dreg);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void MULS()
|
||||
{
|
||||
@ -1900,17 +1406,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 54 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void MULS_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int dreg = (op >> 9) & 7;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "muls";
|
||||
info.Args = String.Format("{0}, D{1}", DisassembleValue(mode, reg, 2, ref pc), dreg);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void DIVU()
|
||||
{
|
||||
@ -1945,17 +1440,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 140 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void DIVU_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int dreg = (op >> 9) & 7;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "divu";
|
||||
info.Args = String.Format("{0}, D{1}", DisassembleValue(mode, reg, 2, ref pc), dreg);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void DIVS()
|
||||
{
|
||||
@ -1990,16 +1474,5 @@ namespace cpu.m68000
|
||||
pendingCycles -= 158 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void DIVS_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int dreg = (op >> 9) & 7;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "divs";
|
||||
info.Args = String.Format("{0}, D{1}", DisassembleValue(mode, reg, 2, ref pc), dreg);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -85,24 +85,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void Bcc_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
sbyte displacement8 = (sbyte)op;
|
||||
int cond = (op >> 8) & 0x0F;
|
||||
|
||||
info.Mnemonic = "b" + DisassembleCondition(cond);
|
||||
if (displacement8 != 0)
|
||||
{
|
||||
info.Args = string.Format("${0:X}", pc + displacement8);
|
||||
}
|
||||
else
|
||||
{
|
||||
info.Args = string.Format("${0:X}", pc + ReadOpWord(pc));
|
||||
pc += 2;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void BRA()
|
||||
{
|
||||
@ -119,21 +101,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 10;
|
||||
}
|
||||
|
||||
void BRA_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "bra";
|
||||
|
||||
sbyte displacement8 = (sbyte)op;
|
||||
if (displacement8 != 0)
|
||||
info.Args = String.Format("${0:X}", pc + displacement8);
|
||||
else
|
||||
{
|
||||
info.Args = String.Format("${0:X}", pc + ReadOpWord(pc));
|
||||
pc += 2;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void BSR()
|
||||
{
|
||||
@ -155,21 +122,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 18;
|
||||
}
|
||||
|
||||
void BSR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "bsr";
|
||||
|
||||
sbyte displacement8 = (sbyte)op;
|
||||
if (displacement8 != 0)
|
||||
info.Args = String.Format("${0:X}", pc + displacement8);
|
||||
else
|
||||
{
|
||||
info.Args = String.Format("${0:X}", pc + ReadOpWord(pc));
|
||||
pc += 2;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void DBcc()
|
||||
{
|
||||
@ -196,15 +148,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void DBcc_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int cond = (op >> 8) & 0x0F;
|
||||
info.Mnemonic = "db" + DisassembleCondition(cond);
|
||||
|
||||
int pc = info.PC + 2;
|
||||
info.Args = String.Format("D{0}, ${1:X}", op & 7, pc + ReadWord(pc));
|
||||
info.Length = 4;
|
||||
}
|
||||
|
||||
void RTS()
|
||||
{
|
||||
@ -213,11 +156,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 16;
|
||||
}
|
||||
|
||||
void RTS_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
info.Mnemonic = "rts";
|
||||
info.Args = "";
|
||||
}
|
||||
|
||||
void RTR()
|
||||
{
|
||||
@ -229,12 +167,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 20;
|
||||
}
|
||||
|
||||
void RTR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
info.Mnemonic = "rtr";
|
||||
info.Args = "";
|
||||
}
|
||||
|
||||
void RESET()
|
||||
{
|
||||
if (S)
|
||||
@ -247,12 +179,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void RESET_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
info.Mnemonic = "reset";
|
||||
info.Args = "";
|
||||
}
|
||||
|
||||
void RTE()
|
||||
{
|
||||
short newSR = ReadWord(A[7].s32);
|
||||
@ -263,12 +189,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 20;
|
||||
}
|
||||
|
||||
void RTE_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
info.Mnemonic = "rte";
|
||||
info.Args = "";
|
||||
}
|
||||
|
||||
void TAS()
|
||||
{
|
||||
int mode = (op >> 3) & 0x07;
|
||||
@ -288,16 +208,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= (mode == 0) ? 4 : 14 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void TAS_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = op & 7;
|
||||
info.Mnemonic = "tas.b";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void TST()
|
||||
{
|
||||
int size = (op >> 6) & 3;
|
||||
@ -316,22 +226,6 @@ namespace cpu.m68000
|
||||
Z = (value == 0);
|
||||
}
|
||||
|
||||
void TST_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int size = (op >> 6) & 3;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
switch (size)
|
||||
{
|
||||
case 0: info.Mnemonic = "tst.b"; info.Args = DisassembleValue(mode, reg, 1, ref pc); break;
|
||||
case 1: info.Mnemonic = "tst.w"; info.Args = DisassembleValue(mode, reg, 2, ref pc); break;
|
||||
case 2: info.Mnemonic = "tst.l"; info.Args = DisassembleValue(mode, reg, 4, ref pc); break;
|
||||
}
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void BTSTi()
|
||||
{
|
||||
int bit = ReadOpWord(PC); PC += 2;
|
||||
@ -354,18 +248,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void BTSTi_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int bit = ReadOpWord(pc); pc += 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = op & 7;
|
||||
|
||||
info.Mnemonic = "btst";
|
||||
info.Args = String.Format("${0:X}, {1}", bit, DisassembleValue(mode, reg, 1, ref pc));
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void BTSTr()
|
||||
{
|
||||
int dReg = (op >> 9) & 7;
|
||||
@ -389,18 +271,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void BTSTr_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dReg = (op >> 9) & 7;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = op & 7;
|
||||
|
||||
info.Mnemonic = "btst";
|
||||
info.Args = String.Format("D{0}, {1}", dReg, DisassembleValue(mode, reg, 1, ref pc));
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void BCHGi()
|
||||
{
|
||||
int bit = ReadOpWord(PC); PC += 2;
|
||||
@ -427,17 +297,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void BCHGi_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int bit = ReadOpWord(pc); pc += 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = op & 7;
|
||||
|
||||
info.Mnemonic = "bchg";
|
||||
info.Args = String.Format("${0:X}, {1}", bit, DisassembleValue(mode, reg, 1, ref pc));
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void BCHGr()
|
||||
{
|
||||
@ -466,18 +325,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void BCHGr_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dReg = (op >> 9) & 7;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = op & 7;
|
||||
|
||||
info.Mnemonic = "bchg";
|
||||
info.Args = String.Format("D{0}, {1}", dReg, DisassembleValue(mode, reg, 1, ref pc));
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void BCLRi()
|
||||
{
|
||||
int bit = ReadOpWord(PC); PC += 2;
|
||||
@ -504,18 +351,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void BCLRi_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int bit = ReadOpWord(pc); pc += 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = op & 7;
|
||||
|
||||
info.Mnemonic = "bclr";
|
||||
info.Args = String.Format("${0:X}, {1}", bit, DisassembleValue(mode, reg, 1, ref pc));
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void BCLRr()
|
||||
{
|
||||
int dReg = (op >> 9) & 7;
|
||||
@ -543,17 +378,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void BCLRr_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dReg = (op >> 9) & 7;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = op & 7;
|
||||
|
||||
info.Mnemonic = "bclr";
|
||||
info.Args = String.Format("D{0}, {1}", dReg, DisassembleValue(mode, reg, 1, ref pc));
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void BSETi()
|
||||
{
|
||||
@ -581,17 +405,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void BSETi_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int bit = ReadOpWord(pc); pc += 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = op & 7;
|
||||
|
||||
info.Mnemonic = "bset";
|
||||
info.Args = String.Format("${0:X}, {1}", bit, DisassembleValue(mode, reg, 1, ref pc));
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void BSETr()
|
||||
{
|
||||
@ -620,17 +433,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void BSETr_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dReg = (op >> 9) & 7;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = op & 7;
|
||||
|
||||
info.Mnemonic = "bset";
|
||||
info.Args = String.Format("D{0}, {1}", dReg, DisassembleValue(mode, reg, 1, ref pc));
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void JMP()
|
||||
{
|
||||
@ -658,15 +460,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void JMP_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
info.Mnemonic = "jmp";
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void JSR()
|
||||
{
|
||||
@ -695,15 +488,6 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void JSR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
info.Mnemonic = "jsr";
|
||||
info.Args = DisassembleAddress(mode, reg, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void LINK()
|
||||
{
|
||||
@ -716,14 +500,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 16;
|
||||
}
|
||||
|
||||
void LINK_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int reg = op & 7;
|
||||
info.Mnemonic = "link";
|
||||
info.Args = "A" + reg + ", " + DisassembleImmediate(2, ref pc); // TODO need a DisassembleSigned or something
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void UNLK()
|
||||
{
|
||||
@ -734,23 +510,12 @@ namespace cpu.m68000
|
||||
pendingCycles -= 12;
|
||||
}
|
||||
|
||||
void UNLK_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int reg = op & 7;
|
||||
info.Mnemonic = "unlk";
|
||||
info.Args = "A" + reg;
|
||||
info.Length = 2;
|
||||
}
|
||||
|
||||
void NOP()
|
||||
{
|
||||
pendingCycles -= 4;
|
||||
}
|
||||
|
||||
void NOP_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
info.Mnemonic = "nop";
|
||||
}
|
||||
|
||||
void Scc() // Set on condition
|
||||
{
|
||||
@ -774,16 +539,5 @@ namespace cpu.m68000
|
||||
}
|
||||
}
|
||||
|
||||
void Scc_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int cond = (op >> 8) & 0x0F;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
|
||||
info.Mnemonic = "s" + DisassembleCondition(cond);
|
||||
info.Args = DisassembleValue(mode, reg, 1, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -40,15 +40,6 @@ namespace cpu.m68000
|
||||
// pendingCycles -= 12 + EACyclesBW[mode, reg];
|
||||
//}
|
||||
|
||||
void MOVEtSR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
info.Mnemonic = "move";
|
||||
info.Args = DisassembleValue(mode, reg, 2, ref pc) + ", SR";
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void MOVEfSR()
|
||||
{
|
||||
@ -58,15 +49,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= (mode == 0) ? 6 : 8 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void MOVEfSR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
info.Mnemonic = "move";
|
||||
info.Args = "SR, " + DisassembleValue(mode, reg, 2, ref pc);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void MOVEUSP()
|
||||
{
|
||||
@ -91,15 +73,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 4;
|
||||
}
|
||||
|
||||
void MOVEUSP_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int dir = (op >> 3) & 1;
|
||||
int reg = op & 7;
|
||||
info.Mnemonic = "move";
|
||||
info.Args = (dir == 0) ? ("A" + reg + ", USP") : ("USP, A" + reg);
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ANDI_SR()
|
||||
{
|
||||
@ -109,13 +82,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 20;
|
||||
}
|
||||
|
||||
void ANDI_SR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "andi";
|
||||
info.Args = DisassembleImmediate(2, ref pc) + ", SR";
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void EORI_SR()
|
||||
{
|
||||
@ -125,13 +91,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 20;
|
||||
}
|
||||
|
||||
void EORI_SR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "eori";
|
||||
info.Args = DisassembleImmediate(2, ref pc) + ", SR";
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void ORI_SR()
|
||||
{
|
||||
@ -141,13 +100,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 20;
|
||||
}
|
||||
|
||||
void ORI_SR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
info.Mnemonic = "ori";
|
||||
info.Args = DisassembleImmediate(2, ref pc) + ", SR";
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void MOVECCR()
|
||||
{
|
||||
@ -162,15 +114,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 12 + EACyclesBW[mode, reg];
|
||||
}
|
||||
|
||||
void MOVECCR_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
int pc = info.PC + 2;
|
||||
int mode = (op >> 3) & 7;
|
||||
int reg = (op >> 0) & 7;
|
||||
info.Mnemonic = "move";
|
||||
info.Args = DisassembleValue(mode, reg, 2, ref pc) + ", CCR";
|
||||
info.Length = pc - info.PC;
|
||||
}
|
||||
|
||||
void TRAP()
|
||||
{
|
||||
@ -179,11 +122,6 @@ namespace cpu.m68000
|
||||
pendingCycles -= 4;
|
||||
}
|
||||
|
||||
void TRAP_Disasm(DisassemblyInfo info)
|
||||
{
|
||||
info.Mnemonic = "trap";
|
||||
info.Args = string.Format("${0:X}", op & 0xF);
|
||||
}
|
||||
|
||||
void TrapVector(int vector)
|
||||
{
|
||||
|
||||
@ -160,15 +160,11 @@ namespace cpu.m68000
|
||||
public Action<int, short> WriteWord;
|
||||
public Action<int, int> WriteLong;
|
||||
|
||||
public delegate void debug_delegate();
|
||||
//public debug_delegate debugger_start_cpu_hook_callback, debugger_stop_cpu_hook_callback;
|
||||
|
||||
// Initialization
|
||||
|
||||
public MC68000()
|
||||
{
|
||||
//倒是已经废弃
|
||||
BuildOpcodeTable();
|
||||
//BuildOpcodeTable();
|
||||
}
|
||||
|
||||
|
||||
@ -233,18 +229,15 @@ namespace cpu.m68000
|
||||
{
|
||||
int prevCycles = pendingCycles;
|
||||
PPC = PC;
|
||||
//debugger_start_cpu_hook_callback();
|
||||
op = (ushort)ReadOpWord(PC); PC += 2;
|
||||
//Opcodes[op]();
|
||||
DoOpCode(op);
|
||||
m68ki_check_interrupts();
|
||||
//debugger_stop_cpu_hook_callback();
|
||||
int delta = prevCycles - pendingCycles;
|
||||
totalExecutedCycles += (ulong)delta;
|
||||
}
|
||||
while (pendingCycles > 0);
|
||||
pendingCycles -= int_cycles;
|
||||
//totalExecutedCycles += (ulong)int_cycles;
|
||||
int_cycles = 0;
|
||||
ran = cycles - pendingCycles;
|
||||
return ran;
|
||||
|
||||
@ -315,83 +315,6 @@ namespace cpu.m68000
|
||||
throw new Exception("Invalid addressing mode!");
|
||||
}
|
||||
|
||||
string DisassembleValue(int mode, int reg, int size, ref int pc)
|
||||
{
|
||||
string value;
|
||||
int addr;
|
||||
switch (mode)
|
||||
{
|
||||
case 0: return "D" + reg; // Dn
|
||||
case 1: return "A" + reg; // An
|
||||
case 2: return "(A" + reg + ")"; // (An)
|
||||
case 3: return "(A" + reg + ")+"; // (An)+
|
||||
case 4: return "-(A" + reg + ")"; // -(An)
|
||||
case 5: value = string.Format("(${0:X},A{1})", ReadOpWord(pc), reg); pc += 2; return value; // (d16,An)
|
||||
case 6: addr = ReadOpWord(pc); pc += 2; return DisassembleIndex("A" + reg, (short)addr); // (d8,An,Xn)
|
||||
case 7:
|
||||
switch (reg)
|
||||
{
|
||||
case 0: value = String.Format("(${0:X})", ReadOpWord(pc)); pc += 2; return value; // (imm).W
|
||||
case 1: value = String.Format("(${0:X})", ReadOpLong(pc)); pc += 4; return value; // (imm).L
|
||||
case 2: value = String.Format("(${0:X})", pc + ReadOpWord(pc)); pc += 2; return value; // (d16,PC)
|
||||
case 3: addr = ReadOpWord(pc); pc += 2; return DisassembleIndex("PC", (short)addr); // (d8,PC,Xn)
|
||||
case 4:
|
||||
switch (size)
|
||||
{
|
||||
case 1: value = String.Format("${0:X}", (byte)ReadOpWord(pc)); pc += 2; return value;
|
||||
case 2: value = String.Format("${0:X}", ReadOpWord(pc)); pc += 2; return value;
|
||||
case 4: value = String.Format("${0:X}", ReadOpLong(pc)); pc += 4; return value;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
throw new Exception("Invalid addressing mode!");
|
||||
}
|
||||
|
||||
string DisassembleImmediate(int size, ref int pc)
|
||||
{
|
||||
int immed;
|
||||
switch (size)
|
||||
{
|
||||
case 1:
|
||||
immed = (byte)ReadOpWord(pc); pc += 2;
|
||||
return String.Format("${0:X}", immed);
|
||||
case 2:
|
||||
immed = (ushort)ReadOpWord(pc); pc += 2;
|
||||
return String.Format("${0:X}", immed);
|
||||
case 4:
|
||||
immed = ReadOpLong(pc); pc += 4;
|
||||
return String.Format("${0:X}", immed);
|
||||
}
|
||||
throw new ArgumentException("Invalid size");
|
||||
}
|
||||
|
||||
string DisassembleAddress(int mode, int reg, ref int pc)
|
||||
{
|
||||
int addr;
|
||||
switch (mode)
|
||||
{
|
||||
case 0: return "INVALID"; // Dn
|
||||
case 1: return "INVALID"; // An
|
||||
case 2: return "(A" + reg + ")"; // (An)
|
||||
case 3: return "(A" + reg + ")+"; // (An)+
|
||||
case 4: return "-(A" + reg + ")"; // -(An)
|
||||
case 5: addr = ReadOpWord(pc); pc += 2; return String.Format("(${0:X},A{1})", (short)addr, reg); // (d16,An)
|
||||
case 6: addr = ReadOpWord(pc); pc += 2; return DisassembleIndex("A" + reg, (short)addr); // (d8,An,Xn)
|
||||
case 7:
|
||||
switch (reg)
|
||||
{
|
||||
case 0: addr = ReadOpWord(pc); pc += 2; return String.Format("${0:X}.w", addr); // (imm).w
|
||||
case 1: addr = ReadOpLong(pc); pc += 4; return String.Format("${0:X}.l", addr); // (imm).l
|
||||
case 2: addr = ReadOpWord(pc); pc += 2; return String.Format("(${0:X},PC)", addr); // (d16,PC)
|
||||
case 3: addr = ReadOpWord(pc); pc += 2; return DisassembleIndex("PC", (short)addr); // (d8,PC,Xn)
|
||||
case 4: return "INVALID"; // immediate
|
||||
}
|
||||
break;
|
||||
}
|
||||
throw new Exception("Invalid addressing mode!");
|
||||
}
|
||||
|
||||
void WriteValueB(int mode, int reg, sbyte value)
|
||||
{
|
||||
@ -597,27 +520,5 @@ namespace cpu.m68000
|
||||
return displacement + indexReg;
|
||||
}
|
||||
|
||||
string DisassembleIndex(string baseRegister, short extension)
|
||||
{
|
||||
int d_a = (extension >> 15) & 0x1;
|
||||
int reg = (extension >> 12) & 0x7;
|
||||
int size = (extension >> 11) & 0x1;
|
||||
int scale = (extension >> 9) & 0x3;
|
||||
sbyte displacement = (sbyte)extension;
|
||||
|
||||
string scaleFactor;
|
||||
switch (scale)
|
||||
{
|
||||
case 0: scaleFactor = ""; break;
|
||||
case 1: scaleFactor = "2"; break;
|
||||
case 2: scaleFactor = "4"; break;
|
||||
default: scaleFactor = "8"; break;
|
||||
}
|
||||
|
||||
string offsetRegister = (d_a == 0) ? "D" : "A";
|
||||
string sizeStr = size == 0 ? ".w" : ".l";
|
||||
string displacementStr = displacement == 0 ? "" : ("," + (displacement >= 0 ? "$" + displacement.ToString("X") : "-$" + (-displacement).ToString("X")));
|
||||
return string.Format("({0},{1}{2}{3}{4}{5})", baseRegister, scaleFactor, offsetRegister, reg, sizeStr, displacementStr);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,970 +0,0 @@
|
||||
using MAME.Core;
|
||||
using System;
|
||||
using System.Collections.Generic;
|
||||
|
||||
namespace cpu.m68000
|
||||
{
|
||||
partial class MC68000
|
||||
{
|
||||
void BuildOpcodeTable()
|
||||
{
|
||||
//Assign("ill", ILL, "", "Data8", "Data8");//
|
||||
//Assign("ori2ccr", ORI_CCR, "0000000000111100");//
|
||||
//Assign("ori2sr", ORI_SR, "0000000001111100");
|
||||
//Assign("ori", ORI, "00000000", "Size2_1", "OAmXn");
|
||||
//Assign("andi2ccr", ANDI_CCR, "0000001000111100");//
|
||||
//Assign("andi2sr", ANDI_SR, "0000001001111100");
|
||||
//Assign("andi", ANDI, "00000010", "Size2_1", "OAmXn");
|
||||
//Assign("subi", SUBI, "00000100", "Size2_1", "OAmXn");
|
||||
//Assign("addi", ADDI, "00000110", "Size2_1", "OAmXn");
|
||||
//Assign("eori2ccr", EORI_CCR, "0000101000111100");//
|
||||
//Assign("eori2sr", EORI_SR, "0000101001111100");
|
||||
//Assign("eori", EORI, "00001010", "Size2_1", "OAmXn");
|
||||
//Assign("cmpi", CMPI, "00001100", "Size2_1", "OAmXn");
|
||||
//Assign("btst", BTSTi, "0000100000", "BAmXn");
|
||||
//Assign("bchg", BCHGi, "0000100001", "OAmXn");
|
||||
//Assign("bclr", BCLRi, "0000100010", "OAmXn");
|
||||
//Assign("bset", BSETi, "0000100011", "OAmXn");
|
||||
//Assign("btst", BTSTr, "0000", "Xn", "100", "AmXn");
|
||||
//Assign("bchg", BCHGr, "0000", "Xn", "101", "OAmXn");
|
||||
//Assign("bclr", BCLRr, "0000", "Xn", "110", "OAmXn");
|
||||
//Assign("bset", BSETr, "0000", "Xn", "111", "OAmXn");
|
||||
//Assign("movep", MOVEP, "0000", "Xn", "1", "Data1", "Size1", "001", "Xn");//
|
||||
//Assign("movea", MOVEA, "00", "Size2_2", "Xn", "001", "AmXn");
|
||||
//Assign("move", MOVE, "00", "01", "OXnAm", "MAmXn");
|
||||
//Assign("move", MOVE, "00", "Size2_2", "OXnAm", "AmXn");
|
||||
//Assign("movefsr", MOVEfSR, "0100000011", "OAmXn");
|
||||
//Assign("moveccr", MOVECCR, "0100010011", "MAmXn");
|
||||
//Assign("move2sr", MOVEtSR, "0100011011", "MAmXn");
|
||||
//Assign("negx", NEGX, "01000000", "Size2_1", "OAmXn");//
|
||||
//Assign("clr", CLR, "01000010", "Size2_1", "OAmXn");
|
||||
//Assign("neg", NEG, "01000100", "Size2_1", "OAmXn");
|
||||
//Assign("not", NOT, "01000110", "Size2_1", "OAmXn");
|
||||
//Assign("ext", EXT, "010010001", "Size1", "000", "Xn");
|
||||
//Assign("nbcd", NBCD, "0100100000", "OAmXn");//
|
||||
//Assign("swap", SWAP, "0100100001000", "Xn");
|
||||
//Assign("pea", PEA, "0100100001", "LAmXn");
|
||||
//Assign("illegal", ILLEGAL, "0100101011111100");//
|
||||
//Assign("tas", TAS, "0100101011", "OAmXn");//
|
||||
//Assign("tst", TST, "01001010", "Size2_1", "OAmXn");
|
||||
//Assign("trap", TRAP, "010011100100", "Data4");
|
||||
//Assign("link", LINK, "0100111001010", "Xn");
|
||||
//Assign("unlk", UNLK, "0100111001011", "Xn");
|
||||
//Assign("moveusp", MOVEUSP, "010011100110", "Data1", "Xn");
|
||||
//Assign("reset", RESET, "0100111001110000");//
|
||||
//Assign("nop", NOP, "0100111001110001");
|
||||
//Assign("stop", STOP, "0100111001110010");//
|
||||
//Assign("rte", RTE, "0100111001110011");
|
||||
//Assign("rts", RTS, "0100111001110101");
|
||||
//Assign("trapv", TRAPV, "0100111001110110");//
|
||||
//Assign("rtr", RTR, "0100111001110111");
|
||||
//Assign("jsr", JSR, "0100111010", "LAmXn");
|
||||
//Assign("jmp", JMP, "0100111011", "LAmXn");
|
||||
//Assign("movem", MOVEM0, "010010001", "Size1", "M2AmXn");
|
||||
//Assign("movem", MOVEM1, "010011001", "Size1", "M3AmXn");
|
||||
//Assign("lea", LEA, "0100", "Xn", "111", "LAmXn");
|
||||
//Assign("chk", CHK, "0100", "Xn", "110", "MAmXn");//
|
||||
//Assign("addq", ADDQ, "0101", "Data3", "0", "00", "OAmXn");
|
||||
//Assign("addq", ADDQ, "0101", "Data3", "0", "Size2_3", "A2AmXn");
|
||||
//Assign("subq", SUBQ, "0101", "Data3", "1", "00", "OAmXn");
|
||||
//Assign("subq", SUBQ, "0101", "Data3", "1", "Size2_3", "A2AmXn");
|
||||
//Assign("scc", Scc, "0101", "CondAll", "11", "OAmXn");
|
||||
//Assign("dbcc", DBcc, "0101", "CondAll", "11001", "Xn");
|
||||
//Assign("bra", BRA, "01100000", "Data8");
|
||||
//Assign("bsr", BSR, "01100001", "Data8");
|
||||
//Assign("bcc", Bcc, "0110", "CondMain", "Data8");
|
||||
//Assign("moveq", MOVEQ, "0111", "Xn", "0", "Data8");
|
||||
//Assign("divu", DIVU, "1000", "Xn", "011", "MAmXn");
|
||||
//Assign("divs", DIVS, "1000", "Xn", "111", "MAmXn");
|
||||
//Assign("sbcd", SBCD0, "1000", "Xn", "100000", "Xn");//
|
||||
//Assign("sbcd", SBCD1, "1000", "Xn", "100001", "Xn");//
|
||||
//Assign("or", OR0, "1000", "Xn", "0", "Size2_1", "MAmXn");
|
||||
//Assign("or", OR1, "1000", "Xn", "1", "Size2_1", "O2AmXn");
|
||||
//Assign("sub", SUB0, "1001", "Xn", "0", "00", "MAmXn");
|
||||
//Assign("sub", SUB0, "1001", "Xn", "0", "Size2_3", "AmXn");
|
||||
//Assign("sub", SUB1, "1001", "Xn", "1", "00", "O2AmXn");
|
||||
//Assign("sub", SUB1, "1001", "Xn", "1", "Size2_3", "A2AmXn");
|
||||
//Assign("subx", SUBX0, "1001", "Xn", "1", "Size2_1", "000", "Xn");//
|
||||
//Assign("subx", SUBX1, "1001", "Xn", "1", "Size2_1", "001", "Xn");//
|
||||
//Assign("suba", SUBA, "1001", "Xn", "Size1", "11", "AmXn");
|
||||
//Assign("eor", EOR, "1011", "Xn", "1", "Size2_1", "OAmXn");
|
||||
//Assign("cmpm", CMPM, "1011", "Xn", "1", "Size2_1", "001", "Xn");
|
||||
//Assign("cmp", CMP, "1011", "Xn", "0", "00", "MAmXn");
|
||||
//Assign("cmp", CMP, "1011", "Xn", "0", "Size2_3", "AmXn");
|
||||
//Assign("cmpa", CMPA, "1011", "Xn", "Size1", "11", "AmXn");
|
||||
//Assign("mulu", MULU, "1100", "Xn", "011", "MAmXn");
|
||||
//Assign("muls", MULS, "1100", "Xn", "111", "MAmXn");
|
||||
//Assign("abcd", ABCD0, "1100", "Xn", "100000", "Xn");//
|
||||
//Assign("abcd", ABCD1, "1100", "Xn", "100001", "Xn");//
|
||||
//Assign("exg", EXGdd, "1100", "Xn", "101000", "Xn");//
|
||||
//Assign("exg", EXGaa, "1100", "Xn", "101001", "Xn");//
|
||||
//Assign("exg", EXGda, "1100", "Xn", "110001", "Xn");//
|
||||
//Assign("and", AND0, "1100", "Xn", "0", "Size2_1", "MAmXn");
|
||||
//Assign("and", AND1, "1100", "Xn", "1", "Size2_1", "O2AmXn");
|
||||
//Assign("add", ADD0, "1101", "Xn", "0", "00", "MAmXn");
|
||||
//Assign("add", ADD0, "1101", "Xn", "0", "Size2_3", "AmXn");
|
||||
//Assign("add", ADD1, "1101", "Xn", "1", "Size2_1", "O2AmXn");
|
||||
//Assign("addx", ADDX0, "1101", "Xn", "1", "Size2_1", "000", "Xn");//
|
||||
//Assign("addx", ADDX1, "1101", "Xn", "1", "Size2_1", "001", "Xn");//
|
||||
//Assign("adda", ADDA, "1101", "Xn", "Size1", "11", "AmXn");
|
||||
//Assign("asl", ASLd0, "1110000111", "O2AmXn");//
|
||||
//Assign("asr", ASRd0, "1110000011", "O2AmXn");//
|
||||
//Assign("lsl", LSLd0, "1110001111", "O2AmXn");//
|
||||
//Assign("lsr", LSRd0, "1110001011", "O2AmXn");//
|
||||
//Assign("roxl", ROXLd0, "1110010111", "O2AmXn");//
|
||||
//Assign("roxr", ROXRd0, "1110010011", "O2AmXn");//
|
||||
//Assign("rol", ROLd0, "1110011111", "O2AmXn");//
|
||||
//Assign("ror", RORd0, "1110011011", "O2AmXn");//
|
||||
//Assign("asl", ASLd, "1110", "Data3", "1", "Size2_1", "Data1", "00", "Xn");
|
||||
//Assign("asr", ASRd, "1110", "Data3", "0", "Size2_1", "Data1", "00", "Xn");
|
||||
//Assign("lsl", LSLd, "1110", "Data3", "1", "Size2_1", "Data1", "01", "Xn");
|
||||
//Assign("lsr", LSRd, "1110", "Data3", "0", "Size2_1", "Data1", "01", "Xn");
|
||||
//Assign("roxl", ROXLd, "1110", "Data3", "1", "Size2_1", "Data1", "10", "Xn");
|
||||
//Assign("roxr", ROXRd, "1110", "Data3", "0", "Size2_1", "Data1", "10", "Xn");
|
||||
//Assign("rol", ROLd, "1110", "Data3", "1", "Size2_1", "Data1", "11", "Xn");
|
||||
//Assign("ror", RORd, "1110", "Data3", "0", "Size2_1", "Data1", "11", "Xn");
|
||||
|
||||
|
||||
//string[] temp = new string[Opcodes.Length];
|
||||
//HashSet<string> seen = new HashSet<string>();
|
||||
//var sb = ObjectPoolAuto.AcquireStringBuilder();
|
||||
//var sb2 = ObjectPoolAuto.AcquireStringBuilder();
|
||||
//sb.Append("[");
|
||||
//for (int i = 0; i < Opcodes.Length; i++)
|
||||
//{
|
||||
// temp[i] = Opcodes[i].Method.Name;
|
||||
// sb.Append("MC68000Code.");
|
||||
// sb.Append(temp[i]);
|
||||
// sb.Append(",");
|
||||
// if (!seen.Contains(temp[i]))
|
||||
// {
|
||||
// seen.Add(temp[i]);
|
||||
// }
|
||||
//}
|
||||
//sb.Append("]");
|
||||
|
||||
//sb2.Append("[");
|
||||
//foreach (var s in seen)
|
||||
//{
|
||||
// sb2.Append(s);
|
||||
// sb2.Append(",");
|
||||
//}
|
||||
//sb2.Append("]");
|
||||
|
||||
//var all = sb.ToString();
|
||||
//var all2 = sb2.ToString();
|
||||
//ObjectPoolAuto.Release(sb);
|
||||
}
|
||||
|
||||
//void Assign(string instr, Action exec, string root, params string[] bitfield)
|
||||
//{
|
||||
// List<string> opList = new List<string>();
|
||||
// opList.Add(root);
|
||||
// foreach (var component in bitfield)
|
||||
// {
|
||||
// if (IsBinary(component)) AppendConstant(opList, component);
|
||||
// else if (component == "Size1") opList = AppendPermutations(opList, Size1);
|
||||
// else if (component == "Size2_0") opList = AppendPermutations(opList, Size2_0);
|
||||
// else if (component == "Size2_1") opList = AppendPermutations(opList, Size2_1);
|
||||
// else if (component == "Size2_2") opList = AppendPermutations(opList, Size2_2);
|
||||
// else if (component == "Size2_3") opList = AppendPermutations(opList, Size2_3);
|
||||
// else if (component == "OXnAm") opList = AppendPermutations(opList, OXn3Am3);//0,2-6,7_0-7_1
|
||||
// else if (component == "AmXn") opList = AppendPermutations(opList, Am3Xn3);//0-6,7_0-7_4
|
||||
// else if (component == "OAmXn") opList = AppendPermutations(opList, OAm3Xn3);//0,2-6,7_0-7_1
|
||||
// else if (component == "BAmXn") opList = AppendPermutations(opList, BAm3Xn3);//0,2-6,7_0-7_3
|
||||
// else if (component == "MAmXn") opList = AppendPermutations(opList, MAm3Xn3);//0,2-6,7_0-7_4
|
||||
// else if (component == "AAmXn") opList = AppendPermutations(opList, AAm3Xn3);//1-6,7_0-7_4
|
||||
// else if (component == "LAmXn") opList = AppendPermutations(opList, LAm3Xn3);//2,5-6,7_0-7_3
|
||||
// else if (component == "M2AmXn") opList = AppendPermutations(opList, M2Am3Xn3);//2,4-6,7_0-7_1
|
||||
// else if (component == "M3AmXn") opList = AppendPermutations(opList, M3Am3Xn3);//2-3,5-6,7_0-7_3
|
||||
// else if (component == "A2AmXn") opList = AppendPermutations(opList, A2Am3Xn3);//0-6,7_0-7_1
|
||||
// else if (component == "O2AmXn") opList = AppendPermutations(opList, O2Am3Xn3);//2-6,7_0-7_1
|
||||
// else if (component == "Xn") opList = AppendPermutations(opList, Xn3);
|
||||
// else if (component == "CondMain") opList = AppendPermutations(opList, ConditionMain);
|
||||
// else if (component == "CondAll") opList = AppendPermutations(opList, ConditionAll);
|
||||
// else if (component == "Data1") opList = AppendData(opList, 1);
|
||||
// else if (component == "Data3") opList = AppendData(opList, 3);
|
||||
// else if (component == "Data4") opList = AppendData(opList, 4);
|
||||
// else if (component == "Data8") opList = AppendData(opList, 8);
|
||||
// }
|
||||
// foreach (var opcode in opList)
|
||||
// {
|
||||
// int opc = Convert.ToInt32(opcode, 2);
|
||||
// Opcodes[opc] = exec;
|
||||
// }
|
||||
//}
|
||||
void Assign(string instr, Action exec, string root, params string[] bitfield)
|
||||
{
|
||||
//List<string> opList = ObjectPoolAuto.AcquireList<string>();
|
||||
//opList.Add(root);
|
||||
//foreach (var component in bitfield)
|
||||
//{
|
||||
// if (IsBinary(component)) AppendConstant(ref opList, component);
|
||||
// else if (component == "Size1") AppendPermutations(ref opList, Size1);
|
||||
// else if (component == "Size2_0") AppendPermutations(ref opList, Size2_0);
|
||||
// else if (component == "Size2_1") AppendPermutations(ref opList, Size2_1);
|
||||
// else if (component == "Size2_2") AppendPermutations(ref opList, Size2_2);
|
||||
// else if (component == "Size2_3") AppendPermutations(ref opList, Size2_3);
|
||||
// else if (component == "OXnAm") AppendPermutations(ref opList, OXn3Am3);//0,2-6,7_0-7_1
|
||||
// else if (component == "AmXn") AppendPermutations(ref opList, Am3Xn3);//0-6,7_0-7_4
|
||||
// else if (component == "OAmXn") AppendPermutations(ref opList, OAm3Xn3);//0,2-6,7_0-7_1
|
||||
// else if (component == "BAmXn") AppendPermutations(ref opList, BAm3Xn3);//0,2-6,7_0-7_3
|
||||
// else if (component == "MAmXn") AppendPermutations(ref opList, MAm3Xn3);//0,2-6,7_0-7_4
|
||||
// else if (component == "AAmXn") AppendPermutations(ref opList, AAm3Xn3);//1-6,7_0-7_4
|
||||
// else if (component == "LAmXn") AppendPermutations(ref opList, LAm3Xn3);//2,5-6,7_0-7_3
|
||||
// else if (component == "M2AmXn") AppendPermutations(ref opList, M2Am3Xn3);//2,4-6,7_0-7_1
|
||||
// else if (component == "M3AmXn") AppendPermutations(ref opList, M3Am3Xn3);//2-3,5-6,7_0-7_3
|
||||
// else if (component == "A2AmXn") AppendPermutations(ref opList, A2Am3Xn3);//0-6,7_0-7_1
|
||||
// else if (component == "O2AmXn") AppendPermutations(ref opList, O2Am3Xn3);//2-6,7_0-7_1
|
||||
// else if (component == "Xn") AppendPermutations(ref opList, Xn3);
|
||||
// else if (component == "CondMain") AppendPermutations(ref opList, ConditionMain);
|
||||
// else if (component == "CondAll") AppendPermutations(ref opList, ConditionAll);
|
||||
// else if (component == "Data1") AppendData(ref opList, 1);
|
||||
// else if (component == "Data3") AppendData(ref opList, 3);
|
||||
// else if (component == "Data4") AppendData(ref opList, 4);
|
||||
// else if (component == "Data8") AppendData(ref opList, 8);
|
||||
//}
|
||||
//foreach (var opcode in opList)
|
||||
//{
|
||||
// int opc = Convert.ToInt32(opcode, 2);
|
||||
// Opcodes[opc] = exec;
|
||||
//}
|
||||
//ObjectPoolAuto.Release(opList);
|
||||
}
|
||||
|
||||
void AppendConstant(ref List<string> ops, string constant)
|
||||
{
|
||||
for (int i = 0; i < ops.Count; i++)
|
||||
ops[i] = ops[i] + constant;
|
||||
}
|
||||
|
||||
//List<string> AppendPermutations(List<string> ops, string[] permutations)
|
||||
//{
|
||||
// List<string> output = new List<string>();
|
||||
|
||||
// foreach (var input in ops)
|
||||
// foreach (var perm in permutations)
|
||||
// output.Add(input + perm);
|
||||
|
||||
// return output;
|
||||
//}
|
||||
|
||||
void AppendPermutations(ref List<string> ops, string[] permutations)
|
||||
{
|
||||
List<string> output = ObjectPoolAuto.AcquireList<string>();
|
||||
foreach (var input in ops)
|
||||
foreach (var perm in permutations)
|
||||
output.Add(input + perm);
|
||||
ops.Clear();
|
||||
ops.AddRange(output);
|
||||
ObjectPoolAuto.Release(output);
|
||||
}
|
||||
|
||||
//List<string> AppendData(List<string> ops, int bits)
|
||||
//{
|
||||
// List<string> output = new List<string>();
|
||||
|
||||
// foreach (var input in ops)
|
||||
// for (int i = 0; i < BinaryExp(bits); i++)
|
||||
// output.Add(input + Convert.ToString(i, 2).PadLeft(bits, '0'));
|
||||
|
||||
// return output;
|
||||
//}
|
||||
|
||||
|
||||
void AppendData(ref List<string> ops, int bits)
|
||||
{
|
||||
List<string> output = ObjectPoolAuto.AcquireList<string>();
|
||||
foreach (var input in ops)
|
||||
for (int i = 0; i < BinaryExp(bits); i++)
|
||||
{
|
||||
//output.Add(input + Convert.ToString(i, 2).PadLeft(bits, '0'));
|
||||
var sb = ObjectPoolAuto.AcquireStringBuilder();
|
||||
sb.Append(input);
|
||||
sb.Append(Convert.ToString(i, 2).PadLeft(bits, '0'));
|
||||
output.Add(sb.ToString());
|
||||
ObjectPoolAuto.Release(sb);
|
||||
}
|
||||
ops.Clear();
|
||||
ops.AddRange(output);
|
||||
ObjectPoolAuto.Release(output);
|
||||
}
|
||||
|
||||
int BinaryExp(int bits)
|
||||
{
|
||||
int res = 1;
|
||||
for (int i = 0; i < bits; i++)
|
||||
res *= 2;
|
||||
return res;
|
||||
}
|
||||
|
||||
bool IsBinary(string str)
|
||||
{
|
||||
for (int i = 0; i < str.Length; i++)
|
||||
{
|
||||
char c = str[i];
|
||||
if (c == '0' || c == '1')
|
||||
continue;
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
#region Tables
|
||||
|
||||
static readonly string[] Size2_0 = { "01", "11", "10" };
|
||||
static readonly string[] Size2_1 = { "00", "01", "10" };
|
||||
static readonly string[] Size2_2 = { "11", "10" };
|
||||
static readonly string[] Size2_3 = { "01", "10" };
|
||||
static readonly string[] Size1 = { "0", "1" };
|
||||
static readonly string[] Xn3 = { "000", "001", "010", "011", "100", "101", "110", "111" };
|
||||
|
||||
static readonly string[] OXn3Am3 = {
|
||||
"000000", // Dn Data register
|
||||
"001000",
|
||||
"010000",
|
||||
"011000",
|
||||
"100000",
|
||||
"101000",
|
||||
"110000",
|
||||
"111000",
|
||||
|
||||
"000010", // (An) Address
|
||||
"001010",
|
||||
"010010",
|
||||
"011010",
|
||||
"100010",
|
||||
"101010",
|
||||
"110010",
|
||||
"111010",
|
||||
|
||||
"000011", // (An)+ Address with Postincrement
|
||||
"001011",
|
||||
"010011",
|
||||
"011011",
|
||||
"100011",
|
||||
"101011",
|
||||
"110011",
|
||||
"111011",
|
||||
|
||||
"000100", // -(An) Address with Predecrement
|
||||
"001100",
|
||||
"010100",
|
||||
"011100",
|
||||
"100100",
|
||||
"101100",
|
||||
"110100",
|
||||
"111100",
|
||||
|
||||
"000101", // (d16, An) Address with Displacement
|
||||
"001101",
|
||||
"010101",
|
||||
"011101",
|
||||
"100101",
|
||||
"101101",
|
||||
"110101",
|
||||
"111101",
|
||||
|
||||
"000110", // (d8, An, Xn) Address with Index
|
||||
"001110",
|
||||
"010110",
|
||||
"011110",
|
||||
"100110",
|
||||
"101110",
|
||||
"110110",
|
||||
"111110",
|
||||
|
||||
"000111", // (xxx).W Absolute Short
|
||||
"001111", // (xxx).L Absolute Long
|
||||
};
|
||||
|
||||
static readonly string[] Am3Xn3 = {
|
||||
"000000", // Dn Data register
|
||||
"000001",
|
||||
"000010",
|
||||
"000011",
|
||||
"000100",
|
||||
"000101",
|
||||
"000110",
|
||||
"000111",
|
||||
|
||||
"001000", // An Address register
|
||||
"001001",
|
||||
"001010",
|
||||
"001011",
|
||||
"001100",
|
||||
"001101",
|
||||
"001110",
|
||||
"001111",
|
||||
|
||||
"010000", // (An) Address
|
||||
"010001",
|
||||
"010010",
|
||||
"010011",
|
||||
"010100",
|
||||
"010101",
|
||||
"010110",
|
||||
"010111",
|
||||
|
||||
"011000", // (An)+ Address with Postincrement
|
||||
"011001",
|
||||
"011010",
|
||||
"011011",
|
||||
"011100",
|
||||
"011101",
|
||||
"011110",
|
||||
"011111",
|
||||
|
||||
"100000", // -(An) Address with Predecrement
|
||||
"100001",
|
||||
"100010",
|
||||
"100011",
|
||||
"100100",
|
||||
"100101",
|
||||
"100110",
|
||||
"100111",
|
||||
|
||||
"101000", // (d16, An) Address with Displacement
|
||||
"101001",
|
||||
"101010",
|
||||
"101011",
|
||||
"101100",
|
||||
"101101",
|
||||
"101110",
|
||||
"101111",
|
||||
|
||||
"110000", // (d8, An, Xn) Address with Index
|
||||
"110001",
|
||||
"110010",
|
||||
"110011",
|
||||
"110100",
|
||||
"110101",
|
||||
"110110",
|
||||
"110111",
|
||||
|
||||
"111010", // (d16, PC) PC with Displacement
|
||||
"111011", // (d8, PC, Xn) PC with Index
|
||||
"111000", // (xxx).W Absolute Short
|
||||
"111001", // (xxx).L Absolute Long
|
||||
"111100", // #imm Immediate
|
||||
};
|
||||
|
||||
static readonly string[] OAm3Xn3 = {
|
||||
"000000", // Dn Data register
|
||||
"000001",
|
||||
"000010",
|
||||
"000011",
|
||||
"000100",
|
||||
"000101",
|
||||
"000110",
|
||||
"000111",
|
||||
|
||||
"010000", // (An) Address
|
||||
"010001",
|
||||
"010010",
|
||||
"010011",
|
||||
"010100",
|
||||
"010101",
|
||||
"010110",
|
||||
"010111",
|
||||
|
||||
"011000", // (An)+ Address with Postincrement
|
||||
"011001",
|
||||
"011010",
|
||||
"011011",
|
||||
"011100",
|
||||
"011101",
|
||||
"011110",
|
||||
"011111",
|
||||
|
||||
"100000", // -(An) Address with Predecrement
|
||||
"100001",
|
||||
"100010",
|
||||
"100011",
|
||||
"100100",
|
||||
"100101",
|
||||
"100110",
|
||||
"100111",
|
||||
|
||||
"101000", // (d16, An) Address with Displacement
|
||||
"101001",
|
||||
"101010",
|
||||
"101011",
|
||||
"101100",
|
||||
"101101",
|
||||
"101110",
|
||||
"101111",
|
||||
|
||||
"110000", // (d8, An, Xn) Address with Index
|
||||
"110001",
|
||||
"110010",
|
||||
"110011",
|
||||
"110100",
|
||||
"110101",
|
||||
"110110",
|
||||
"110111",
|
||||
|
||||
"111000", // (xxx).W Absolute Short
|
||||
"111001", // (xxx).L Absolute Long
|
||||
};
|
||||
|
||||
static readonly string[] BAm3Xn3 = {
|
||||
"000000", // Dn Data register
|
||||
"000001",
|
||||
"000010",
|
||||
"000011",
|
||||
"000100",
|
||||
"000101",
|
||||
"000110",
|
||||
"000111",
|
||||
|
||||
"010000", // (An) Address
|
||||
"010001",
|
||||
"010010",
|
||||
"010011",
|
||||
"010100",
|
||||
"010101",
|
||||
"010110",
|
||||
"010111",
|
||||
|
||||
"011000", // (An)+ Address with Postincrement
|
||||
"011001",
|
||||
"011010",
|
||||
"011011",
|
||||
"011100",
|
||||
"011101",
|
||||
"011110",
|
||||
"011111",
|
||||
|
||||
"100000", // -(An) Address with Predecrement
|
||||
"100001",
|
||||
"100010",
|
||||
"100011",
|
||||
"100100",
|
||||
"100101",
|
||||
"100110",
|
||||
"100111",
|
||||
|
||||
"101000", // (d16, An) Address with Displacement
|
||||
"101001",
|
||||
"101010",
|
||||
"101011",
|
||||
"101100",
|
||||
"101101",
|
||||
"101110",
|
||||
"101111",
|
||||
|
||||
"110000", // (d8, An, Xn) Address with Index
|
||||
"110001",
|
||||
"110010",
|
||||
"110011",
|
||||
"110100",
|
||||
"110101",
|
||||
"110110",
|
||||
"110111",
|
||||
|
||||
"111010", // (d16, PC) PC with Displacement
|
||||
"111011", // (d8, PC, Xn) PC with Index
|
||||
"111000", // (xxx).W Absolute Short
|
||||
"111001", // (xxx).L Absolute Long
|
||||
};
|
||||
|
||||
static readonly string[] MAm3Xn3 = {
|
||||
"000000", // Dn Data register
|
||||
"000001",
|
||||
"000010",
|
||||
"000011",
|
||||
"000100",
|
||||
"000101",
|
||||
"000110",
|
||||
"000111",
|
||||
|
||||
"010000", // (An) Address
|
||||
"010001",
|
||||
"010010",
|
||||
"010011",
|
||||
"010100",
|
||||
"010101",
|
||||
"010110",
|
||||
"010111",
|
||||
|
||||
"011000", // (An)+ Address with Postincrement
|
||||
"011001",
|
||||
"011010",
|
||||
"011011",
|
||||
"011100",
|
||||
"011101",
|
||||
"011110",
|
||||
"011111",
|
||||
|
||||
"100000", // -(An) Address with Predecrement
|
||||
"100001",
|
||||
"100010",
|
||||
"100011",
|
||||
"100100",
|
||||
"100101",
|
||||
"100110",
|
||||
"100111",
|
||||
|
||||
"101000", // (d16, An) Address with Displacement
|
||||
"101001",
|
||||
"101010",
|
||||
"101011",
|
||||
"101100",
|
||||
"101101",
|
||||
"101110",
|
||||
"101111",
|
||||
|
||||
"110000", // (d8, An, Xn) Address with Index
|
||||
"110001",
|
||||
"110010",
|
||||
"110011",
|
||||
"110100",
|
||||
"110101",
|
||||
"110110",
|
||||
"110111",
|
||||
|
||||
"111010", // (d16, PC) PC with Displacement
|
||||
"111011", // (d8, PC, Xn) PC with Index
|
||||
"111000", // (xxx).W Absolute Short
|
||||
"111001", // (xxx).L Absolute Long
|
||||
"111100", // #imm Immediate
|
||||
};
|
||||
|
||||
static readonly string[] AAm3Xn3 = {
|
||||
"001000", // An Address register
|
||||
"001001",
|
||||
"001010",
|
||||
"001011",
|
||||
"001100",
|
||||
"001101",
|
||||
"001110",
|
||||
"001111",
|
||||
|
||||
"010000", // (An) Address
|
||||
"010001",
|
||||
"010010",
|
||||
"010011",
|
||||
"010100",
|
||||
"010101",
|
||||
"010110",
|
||||
"010111",
|
||||
|
||||
"011000", // (An)+ Address with Postincrement
|
||||
"011001",
|
||||
"011010",
|
||||
"011011",
|
||||
"011100",
|
||||
"011101",
|
||||
"011110",
|
||||
"011111",
|
||||
|
||||
"100000", // -(An) Address with Predecrement
|
||||
"100001",
|
||||
"100010",
|
||||
"100011",
|
||||
"100100",
|
||||
"100101",
|
||||
"100110",
|
||||
"100111",
|
||||
|
||||
"101000", // (d16, An) Address with Displacement
|
||||
"101001",
|
||||
"101010",
|
||||
"101011",
|
||||
"101100",
|
||||
"101101",
|
||||
"101110",
|
||||
"101111",
|
||||
|
||||
"110000", // (d8, An, Xn) Address with Index
|
||||
"110001",
|
||||
"110010",
|
||||
"110011",
|
||||
"110100",
|
||||
"110101",
|
||||
"110110",
|
||||
"110111",
|
||||
|
||||
"111010", // (d16, PC) PC with Displacement
|
||||
"111011", // (d8, PC, Xn) PC with Index
|
||||
"111000", // (xxx).W Absolute Short
|
||||
"111001", // (xxx).L Absolute Long
|
||||
"111100", // #imm Immediate
|
||||
};
|
||||
|
||||
static readonly string[] LAm3Xn3 = {
|
||||
"010000", // (An) Address
|
||||
"010001",
|
||||
"010010",
|
||||
"010011",
|
||||
"010100",
|
||||
"010101",
|
||||
"010110",
|
||||
"010111",
|
||||
|
||||
"101000", // (d16, An) Address with Displacement
|
||||
"101001",
|
||||
"101010",
|
||||
"101011",
|
||||
"101100",
|
||||
"101101",
|
||||
"101110",
|
||||
"101111",
|
||||
|
||||
"110000", // (d8, An, Xn) Address with Index
|
||||
"110001",
|
||||
"110010",
|
||||
"110011",
|
||||
"110100",
|
||||
"110101",
|
||||
"110110",
|
||||
"110111",
|
||||
|
||||
"111010", // (d16, PC) PC with Displacement
|
||||
"111011", // (d8, PC, Xn) PC with Index
|
||||
"111000", // (xxx).W Absolute Short
|
||||
"111001", // (xxx).L Absolute Long
|
||||
};
|
||||
|
||||
static readonly string[] M2Am3Xn3 = {
|
||||
"010000", // (An) Address
|
||||
"010001",
|
||||
"010010",
|
||||
"010011",
|
||||
"010100",
|
||||
"010101",
|
||||
"010110",
|
||||
"010111",
|
||||
|
||||
"100000", // -(An) Address with Predecrement
|
||||
"100001",
|
||||
"100010",
|
||||
"100011",
|
||||
"100100",
|
||||
"100101",
|
||||
"100110",
|
||||
"100111",
|
||||
|
||||
"101000", // (d16, An) Address with Displacement
|
||||
"101001",
|
||||
"101010",
|
||||
"101011",
|
||||
"101100",
|
||||
"101101",
|
||||
"101110",
|
||||
"101111",
|
||||
|
||||
"110000", // (d8, An, Xn) Address with Index
|
||||
"110001",
|
||||
"110010",
|
||||
"110011",
|
||||
"110100",
|
||||
"110101",
|
||||
"110110",
|
||||
"110111",
|
||||
|
||||
"111000", // (xxx).W Absolute Short
|
||||
"111001", // (xxx).L Absolute Long
|
||||
};
|
||||
|
||||
static readonly string[] M3Am3Xn3 = {
|
||||
"010000", // (An) Address
|
||||
"010001",
|
||||
"010010",
|
||||
"010011",
|
||||
"010100",
|
||||
"010101",
|
||||
"010110",
|
||||
"010111",
|
||||
|
||||
"011000", // (An)+ Address with Postincrement
|
||||
"011001",
|
||||
"011010",
|
||||
"011011",
|
||||
"011100",
|
||||
"011101",
|
||||
"011110",
|
||||
"011111",
|
||||
|
||||
"101000", // (d16, An) Address with Displacement
|
||||
"101001",
|
||||
"101010",
|
||||
"101011",
|
||||
"101100",
|
||||
"101101",
|
||||
"101110",
|
||||
"101111",
|
||||
|
||||
"110000", // (d8, An, Xn) Address with Index
|
||||
"110001",
|
||||
"110010",
|
||||
"110011",
|
||||
"110100",
|
||||
"110101",
|
||||
"110110",
|
||||
"110111",
|
||||
|
||||
"111010", // (d16, PC) PC with Displacement
|
||||
"111011", // (d8, PC, Xn) PC with Index
|
||||
"111000", // (xxx).W Absolute Short
|
||||
"111001", // (xxx).L Absolute Long
|
||||
};
|
||||
|
||||
static readonly string[] A2Am3Xn3 = {
|
||||
"000000", // Dn Data register
|
||||
"000001",
|
||||
"000010",
|
||||
"000011",
|
||||
"000100",
|
||||
"000101",
|
||||
"000110",
|
||||
"000111",
|
||||
|
||||
"001000", // An Address register
|
||||
"001001",
|
||||
"001010",
|
||||
"001011",
|
||||
"001100",
|
||||
"001101",
|
||||
"001110",
|
||||
"001111",
|
||||
|
||||
"010000", // (An) Address
|
||||
"010001",
|
||||
"010010",
|
||||
"010011",
|
||||
"010100",
|
||||
"010101",
|
||||
"010110",
|
||||
"010111",
|
||||
|
||||
"011000", // (An)+ Address with Postincrement
|
||||
"011001",
|
||||
"011010",
|
||||
"011011",
|
||||
"011100",
|
||||
"011101",
|
||||
"011110",
|
||||
"011111",
|
||||
|
||||
"100000", // -(An) Address with Predecrement
|
||||
"100001",
|
||||
"100010",
|
||||
"100011",
|
||||
"100100",
|
||||
"100101",
|
||||
"100110",
|
||||
"100111",
|
||||
|
||||
"101000", // (d16, An) Address with Displacement
|
||||
"101001",
|
||||
"101010",
|
||||
"101011",
|
||||
"101100",
|
||||
"101101",
|
||||
"101110",
|
||||
"101111",
|
||||
|
||||
"110000", // (d8, An, Xn) Address with Index
|
||||
"110001",
|
||||
"110010",
|
||||
"110011",
|
||||
"110100",
|
||||
"110101",
|
||||
"110110",
|
||||
"110111",
|
||||
|
||||
"111000", // (xxx).W Absolute Short
|
||||
"111001", // (xxx).L Absolute Long
|
||||
};
|
||||
|
||||
static readonly string[] O2Am3Xn3 = {
|
||||
"010000", // (An) Address
|
||||
"010001",
|
||||
"010010",
|
||||
"010011",
|
||||
"010100",
|
||||
"010101",
|
||||
"010110",
|
||||
"010111",
|
||||
|
||||
"011000", // (An)+ Address with Postincrement
|
||||
"011001",
|
||||
"011010",
|
||||
"011011",
|
||||
"011100",
|
||||
"011101",
|
||||
"011110",
|
||||
"011111",
|
||||
|
||||
"100000", // -(An) Address with Predecrement
|
||||
"100001",
|
||||
"100010",
|
||||
"100011",
|
||||
"100100",
|
||||
"100101",
|
||||
"100110",
|
||||
"100111",
|
||||
|
||||
"101000", // (d16, An) Address with Displacement
|
||||
"101001",
|
||||
"101010",
|
||||
"101011",
|
||||
"101100",
|
||||
"101101",
|
||||
"101110",
|
||||
"101111",
|
||||
|
||||
"110000", // (d8, An, Xn) Address with Index
|
||||
"110001",
|
||||
"110010",
|
||||
"110011",
|
||||
"110100",
|
||||
"110101",
|
||||
"110110",
|
||||
"110111",
|
||||
|
||||
"111000", // (xxx).W Absolute Short
|
||||
"111001", // (xxx).L Absolute Long
|
||||
};
|
||||
|
||||
static readonly string[] ConditionMain = {
|
||||
"0010", // HI Higher (unsigned)
|
||||
"0011", // LS Lower or Same (unsigned)
|
||||
"0100", // CC Carry Clear (aka Higher or Same, unsigned)
|
||||
"0101", // CS Carry Set (aka Lower, unsigned)
|
||||
"0110", // NE Not Equal
|
||||
"0111", // EQ Equal
|
||||
"1000", // VC Overflow Clear
|
||||
"1001", // VS Overflow Set
|
||||
"1010", // PL Plus
|
||||
"1011", // MI Minus
|
||||
"1100", // GE Greater or Equal (signed)
|
||||
"1101", // LT Less Than (signed)
|
||||
"1110", // GT Greater Than (signed)
|
||||
"1111" // LE Less or Equal (signed)
|
||||
};
|
||||
|
||||
static readonly string[] ConditionAll = {
|
||||
"0000", // T True
|
||||
"0001", // F False
|
||||
"0010", // HI Higher (unsigned)
|
||||
"0011", // LS Lower or Same (unsigned)
|
||||
"0100", // CC Carry Clear (aka Higher or Same, unsigned)
|
||||
"0101", // CS Carry Set (aka Lower, unsigned)
|
||||
"0110", // NE Not Equal
|
||||
"0111", // EQ Equal
|
||||
"1000", // VC Overflow Clear
|
||||
"1001", // VS Overflow Set
|
||||
"1010", // PL Plus
|
||||
"1011", // MI Minus
|
||||
"1100", // GE Greater or Equal (signed)
|
||||
"1101", // LT Less Than (signed)
|
||||
"1110", // GT Greater Than (signed)
|
||||
"1111" // LE Less or Equal (signed)
|
||||
};
|
||||
|
||||
#endregion
|
||||
}
|
||||
}
|
||||
@ -1,11 +0,0 @@
|
||||
fileFormatVersion: 2
|
||||
guid: 3f558f03c67bd724291c979f90d0acff
|
||||
MonoImporter:
|
||||
externalObjects: {}
|
||||
serializedVersion: 2
|
||||
defaultReferences: []
|
||||
executionOrder: 0
|
||||
icon: {instanceID: 0}
|
||||
userData:
|
||||
assetBundleName:
|
||||
assetBundleVariant:
|
||||
@ -564,7 +564,6 @@ namespace cpu.m6805
|
||||
Interrupt();
|
||||
}
|
||||
}
|
||||
//debugger_instruction_hook(Machine, PC);
|
||||
ireg = ReadOp(pc.LowWord++);
|
||||
switch (ireg)
|
||||
{
|
||||
|
||||
@ -1,604 +0,0 @@
|
||||
namespace cpu.m6809
|
||||
{
|
||||
public partial class M6809
|
||||
{
|
||||
public class opcodeinfo
|
||||
{
|
||||
public byte opcode;
|
||||
public int length;
|
||||
public string name;
|
||||
public m6809_addressing_modes mode;
|
||||
public uint flags;
|
||||
public opcodeinfo(byte _opcode, int _length, string _name, m6809_addressing_modes _mode)
|
||||
{
|
||||
opcode = _opcode;
|
||||
length = _length;
|
||||
name = _name;
|
||||
mode = _mode;
|
||||
}
|
||||
public opcodeinfo(byte _opcode, int _length, string _name, m6809_addressing_modes _mode, uint _flags)
|
||||
{
|
||||
opcode = _opcode;
|
||||
length = _length;
|
||||
name = _name;
|
||||
mode = _mode;
|
||||
flags = _flags;
|
||||
}
|
||||
}
|
||||
public static uint DASMFLAG_STEP_OVER = 0x20000000, DASMFLAG_SUPPORTED = 0x80000000;
|
||||
public enum m6809_addressing_modes
|
||||
{
|
||||
INH, // Inherent
|
||||
DIR, // Direct
|
||||
IND, // Indexed
|
||||
REL, // Relative (8 bit)
|
||||
LREL, // Long relative (16 bit)
|
||||
EXT, // Extended
|
||||
IMM, // Immediate
|
||||
IMM_RR, // Register-to-register
|
||||
PG1, // Switch to page 1 opcodes
|
||||
PG2 // Switch to page 2 opcodes
|
||||
}
|
||||
public opcodeinfo[] m6809_pg0opcodes = new opcodeinfo[]{
|
||||
new opcodeinfo(0x00, 2, "NEG",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x03, 2, "COM",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x04, 2, "LSR",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x06, 2, "ROR",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x07, 2, "ASR",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x08, 2, "ASL",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x09, 2, "ROL",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x0A, 2, "DEC",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x0C, 2, "INC",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x0D, 2, "TST",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x0E, 2, "JMP",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x0F, 2, "CLR",m6809_addressing_modes.DIR),
|
||||
|
||||
new opcodeinfo(0x10, 1, "page1",m6809_addressing_modes.PG1),
|
||||
new opcodeinfo(0x11, 1, "page2",m6809_addressing_modes.PG2),
|
||||
new opcodeinfo(0x12, 1, "NOP",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x13, 1, "SYNC",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x16, 3, "LBRA",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x17, 3, "LBSR",m6809_addressing_modes.LREL,DASMFLAG_STEP_OVER),
|
||||
new opcodeinfo(0x19, 1, "DAA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x1A, 2, "ORCC",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x1C, 2, "ANDCC",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x1D, 1, "SEX",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x1E, 2, "EXG",m6809_addressing_modes.IMM_RR),
|
||||
new opcodeinfo(0x1F, 2, "TFR",m6809_addressing_modes.IMM_RR),
|
||||
|
||||
new opcodeinfo(0x20, 2, "BRA",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x21, 2, "BRN",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x22, 2, "BHI",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x23, 2, "BLS",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x24, 2, "BCC",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x25, 2, "BCS",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x26, 2, "BNE",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x27, 2, "BEQ",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x28, 2, "BVC",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x29, 2, "BVS",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x2A, 2, "BPL",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x2B, 2, "BMI",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x2C, 2, "BGE",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x2D, 2, "BLT",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x2E, 2, "BGT",m6809_addressing_modes.REL),
|
||||
new opcodeinfo(0x2F, 2, "BLE",m6809_addressing_modes.REL),
|
||||
|
||||
new opcodeinfo(0x30, 2, "LEAX",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x31, 2, "LEAY",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x32, 2, "LEAS",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x33, 2, "LEAU",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x34, 2, "PSHS",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x35, 2, "PULS",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x36, 2, "PSHU",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x37, 2, "PULU",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x39, 1, "RTS",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x3A, 1, "ABX",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x3B, 1, "RTI",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x3C, 2, "CWAI",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x3D, 1, "MUL",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x3F, 1, "SWI",m6809_addressing_modes.INH),
|
||||
|
||||
new opcodeinfo(0x40, 1, "NEGA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x43, 1, "COMA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x44, 1, "LSRA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x46, 1, "RORA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x47, 1, "ASRA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x48, 1, "ASLA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x49, 1, "ROLA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x4A, 1, "DECA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x4C, 1, "INCA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x4D, 1, "TSTA",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x4F, 1, "CLRA",m6809_addressing_modes.INH),
|
||||
|
||||
new opcodeinfo(0x50, 1, "NEGB",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x53, 1, "COMB",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x54, 1, "LSRB",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x56, 1, "RORB",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x57, 1, "ASRB",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x58, 1, "ASLB",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x59, 1, "ROLB",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x5A, 1, "DECB",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x5C, 1, "INCB",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x5D, 1, "TSTB",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x5F, 1, "CLRB",m6809_addressing_modes.INH),
|
||||
|
||||
new opcodeinfo(0x60, 2, "NEG",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x63, 2, "COM",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x64, 2, "LSR",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x66, 2, "ROR",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x67, 2, "ASR",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x68, 2, "ASL",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x69, 2, "ROL",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x6A, 2, "DEC",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x6C, 2, "INC",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x6D, 2, "TST",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x6E, 2, "JMP",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0x6F, 2, "CLR",m6809_addressing_modes.IND),
|
||||
|
||||
new opcodeinfo(0x70, 3, "NEG",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x73, 3, "COM",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x74, 3, "LSR",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x76, 3, "ROR",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x77, 3, "ASR",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x78, 3, "ASL",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x79, 3, "ROL",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x7A, 3, "DEC",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x7C, 3, "INC",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x7D, 3, "TST",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x7E, 3, "JMP",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0x7F, 3, "CLR",m6809_addressing_modes.EXT),
|
||||
|
||||
new opcodeinfo(0x80, 2, "SUBA",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x81, 2, "CMPA",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x82, 2, "SBCA",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x83, 3, "SUBD",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x84, 2, "ANDA",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x85, 2, "BITA",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x86, 2, "LDA",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x88, 2, "EORA",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x89, 2, "ADCA",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x8A, 2, "ORA",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x8B, 2, "ADDA",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x8C, 3, "CMPX",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x8D, 2, "BSR",m6809_addressing_modes.REL,DASMFLAG_STEP_OVER),
|
||||
new opcodeinfo(0x8E, 3, "LDX",m6809_addressing_modes.IMM),
|
||||
|
||||
new opcodeinfo(0x90, 2, "SUBA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x91, 2, "CMPA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x92, 2, "SBCA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x93, 2, "SUBD",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x94, 2, "ANDA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x95, 2, "BITA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x96, 2, "LDA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x97, 2, "STA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x98, 2, "EORA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x99, 2, "ADCA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x9A, 2, "ORA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x9B, 2, "ADDA",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x9C, 2, "CMPX",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x9D, 2, "JSR",m6809_addressing_modes.DIR,DASMFLAG_STEP_OVER),
|
||||
new opcodeinfo(0x9E, 2, "LDX",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x9F, 2, "STX",m6809_addressing_modes.DIR),
|
||||
|
||||
new opcodeinfo(0xA0, 2, "SUBA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xA1, 2, "CMPA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xA2, 2, "SBCA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xA3, 2, "SUBD",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xA4, 2, "ANDA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xA5, 2, "BITA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xA6, 2, "LDA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xA7, 2, "STA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xA8, 2, "EORA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xA9, 2, "ADCA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xAA, 2, "ORA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xAB, 2, "ADDA",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xAC, 2, "CMPX",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xAD, 2, "JSR",m6809_addressing_modes.IND,DASMFLAG_STEP_OVER),
|
||||
new opcodeinfo(0xAE, 2, "LDX",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xAF, 2, "STX",m6809_addressing_modes.IND),
|
||||
|
||||
new opcodeinfo(0xB0, 3, "SUBA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xB1, 3, "CMPA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xB2, 3, "SBCA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xB3, 3, "SUBD",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xB4, 3, "ANDA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xB5, 3, "BITA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xB6, 3, "LDA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xB7, 3, "STA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xB8, 3, "EORA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xB9, 3, "ADCA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xBA, 3, "ORA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xBB, 3, "ADDA",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xBC, 3, "CMPX",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xBD, 3, "JSR",m6809_addressing_modes.EXT,DASMFLAG_STEP_OVER),
|
||||
new opcodeinfo(0xBE, 3, "LDX",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xBF, 3, "STX",m6809_addressing_modes.EXT),
|
||||
|
||||
new opcodeinfo(0xC0, 2, "SUBB",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xC1, 2, "CMPB",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xC2, 2, "SBCB",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xC3, 3, "ADDD",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xC4, 2, "ANDB",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xC5, 2, "BITB",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xC6, 2, "LDB",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xC8, 2, "EORB",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xC9, 2, "ADCB",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xCA, 2, "ORB",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xCB, 2, "ADDB",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xCC, 3, "LDD",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xCE, 3, "LDU",m6809_addressing_modes.IMM),
|
||||
|
||||
new opcodeinfo(0xD0, 2, "SUBB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xD1, 2, "CMPB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xD2, 2, "SBCB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xD3, 2, "ADDD",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xD4, 2, "ANDB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xD5, 2, "BITB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xD6, 2, "LDB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xD7, 2, "STB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xD8, 2, "EORB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xD9, 2, "ADCB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xDA, 2, "ORB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xDB, 2, "ADDB",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xDC, 2, "LDD",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xDD, 2, "STD",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xDE, 2, "LDU",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xDF, 2, "STU",m6809_addressing_modes.DIR),
|
||||
|
||||
new opcodeinfo(0xE0, 2, "SUBB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xE1, 2, "CMPB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xE2, 2, "SBCB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xE3, 2, "ADDD",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xE4, 2, "ANDB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xE5, 2, "BITB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xE6, 2, "LDB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xE7, 2, "STB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xE8, 2, "EORB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xE9, 2, "ADCB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xEA, 2, "ORB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xEB, 2, "ADDB",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xEC, 2, "LDD",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xED, 2, "STD",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xEE, 2, "LDU",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xEF, 2, "STU",m6809_addressing_modes.IND),
|
||||
|
||||
new opcodeinfo(0xF0, 3, "SUBB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xF1, 3, "CMPB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xF2, 3, "SBCB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xF3, 3, "ADDD",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xF4, 3, "ANDB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xF5, 3, "BITB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xF6, 3, "LDB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xF7, 3, "STB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xF8, 3, "EORB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xF9, 3, "ADCB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xFA, 3, "ORB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xFB, 3, "ADDB",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xFC, 3, "LDD",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xFD, 3, "STD",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xFE, 3, "LDU",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xFF, 3, "STU",m6809_addressing_modes.EXT),
|
||||
};
|
||||
public opcodeinfo[] m6809_pg1opcodes = new opcodeinfo[]{
|
||||
new opcodeinfo(0x21, 4, "LBRN",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x22, 4, "LBHI",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x23, 4, "LBLS",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x24, 4, "LBCC",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x25, 4, "LBCS",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x26, 4, "LBNE",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x27, 4, "LBEQ",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x28, 4, "LBVC",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x29, 4, "LBVS",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x2A, 4, "LBPL",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x2B, 4, "LBMI",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x2C, 4, "LBGE",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x2D, 4, "LBLT",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x2E, 4, "LBGT",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x2F, 4, "LBLE",m6809_addressing_modes.LREL),
|
||||
new opcodeinfo(0x3F, 2, "SWI2",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x83, 4, "CMPD",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x8C, 4, "CMPY",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x8E, 4, "LDY",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x93, 3, "CMPD",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x9C, 3, "CMPY",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x9E, 3, "LDY",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x9F, 3, "STY",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xA3, 3, "CMPD",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xAC, 3, "CMPY",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xAE, 3, "LDY",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xAF, 3, "STY",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xB3, 4, "CMPD",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xBC, 4, "CMPY",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xBE, 4, "LDY",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xBF, 4, "STY",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xCE, 4, "LDS",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0xDE, 3, "LDS",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xDF, 3, "STS",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xEE, 3, "LDS",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xEF, 3, "STS",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xFE, 4, "LDS",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xFF, 4, "STS",m6809_addressing_modes.EXT)
|
||||
};
|
||||
public opcodeinfo[] m6809_pg2opcodes = new opcodeinfo[]{
|
||||
new opcodeinfo(0x3F, 2, "SWI3",m6809_addressing_modes.INH),
|
||||
new opcodeinfo(0x83, 4, "CMPU",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x8C, 4, "CMPS",m6809_addressing_modes.IMM),
|
||||
new opcodeinfo(0x93, 3, "CMPU",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0x9C, 3, "CMPS",m6809_addressing_modes.DIR),
|
||||
new opcodeinfo(0xA3, 3, "CMPU",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xAC, 3, "CMPS",m6809_addressing_modes.IND),
|
||||
new opcodeinfo(0xB3, 4, "CMPU",m6809_addressing_modes.EXT),
|
||||
new opcodeinfo(0xBC, 4, "CMPS",m6809_addressing_modes.EXT)
|
||||
};
|
||||
public opcodeinfo[][] m6809_pgpointers;
|
||||
public int[] m6809_numops;
|
||||
public static string[] m6809_regs = new string[] { "X", "Y", "U", "S", "PC" };
|
||||
public static string[] m6809_regs_te = new string[]
|
||||
{
|
||||
"D", "X", "Y", "U", "S", "PC", "inv", "inv",
|
||||
"A", "B", "CC", "DP", "inv", "inv", "inv", "inv"
|
||||
};
|
||||
public byte op;
|
||||
public void DisassemblerInit()
|
||||
{
|
||||
m6809_pgpointers = new opcodeinfo[3][] { m6809_pg0opcodes, m6809_pg1opcodes, m6809_pg2opcodes };
|
||||
m6809_numops = new int[3] { m6809_pg0opcodes.Length, m6809_pg1opcodes.Length, m6809_pg2opcodes.Length };
|
||||
}
|
||||
public string m6809_dasm(int ppc)
|
||||
{
|
||||
string buffer = "";
|
||||
|
||||
byte opcode, pb, pbm, reg;
|
||||
m6809_addressing_modes mode;
|
||||
byte[] operandarray;
|
||||
int ea;
|
||||
uint flags;
|
||||
int numoperands, offset;
|
||||
int i, j, i1, page = 0;
|
||||
ushort p = (ushort)ppc;
|
||||
if (ppc == 0xc010)
|
||||
{
|
||||
i1 = 1;
|
||||
}
|
||||
buffer = ReadOp(p).ToString("X2");
|
||||
bool indirect, opcode_found = false;
|
||||
do
|
||||
{
|
||||
opcode = ReadOp(p);
|
||||
p++;
|
||||
for (i = 0; i < m6809_numops[page]; i++)
|
||||
if (m6809_pgpointers[page][i].opcode == opcode)
|
||||
break;
|
||||
if (i < m6809_numops[page])
|
||||
opcode_found = true;
|
||||
else
|
||||
{
|
||||
buffer += " Illegal Opcode";
|
||||
return buffer;
|
||||
}
|
||||
if (m6809_pgpointers[page][i].mode >= m6809_addressing_modes.PG1)
|
||||
{
|
||||
page = m6809_pgpointers[page][i].mode - m6809_addressing_modes.PG1 + 1;
|
||||
opcode_found = false;
|
||||
}
|
||||
} while (!opcode_found);
|
||||
if (page == 0)
|
||||
numoperands = m6809_pgpointers[page][i].length - 1;
|
||||
else
|
||||
numoperands = m6809_pgpointers[page][i].length - 2;
|
||||
operandarray = new byte[numoperands];
|
||||
for (j = 0; j < numoperands; j++)
|
||||
{
|
||||
operandarray[j] = ReadOpArg((ushort)(p + j));
|
||||
}
|
||||
p += (ushort)numoperands;
|
||||
ppc += numoperands;
|
||||
mode = m6809_pgpointers[page][i].mode;
|
||||
flags = m6809_pgpointers[page][i].flags;
|
||||
|
||||
buffer += m6809_pgpointers[page][i].name.PadLeft(6);
|
||||
switch (mode)
|
||||
{
|
||||
case m6809_addressing_modes.INH:
|
||||
switch (opcode)
|
||||
{
|
||||
case 0x34: // PSHS
|
||||
case 0x36: // PSHU
|
||||
pb = operandarray[0];
|
||||
if ((pb & 0x80) != 0)
|
||||
buffer += "PC";
|
||||
if ((pb & 0x40) != 0)
|
||||
buffer += (((pb & 0x80) != 0) ? "," : "") + ((opcode == 0x34) ? "U" : "S");
|
||||
if ((pb & 0x20) != 0)
|
||||
buffer += (((pb & 0xc0) != 0) ? "," : "") + "Y";
|
||||
if ((pb & 0x10) != 0)
|
||||
buffer += (((pb & 0xe0) != 0) ? "," : "") + "X";
|
||||
if ((pb & 0x08) != 0)
|
||||
buffer += (((pb & 0xf0) != 0) ? "," : "") + "DP";
|
||||
if ((pb & 0x04) != 0)
|
||||
buffer += (((pb & 0xf8) != 0) ? "," : "") + "B";
|
||||
if ((pb & 0x02) != 0)
|
||||
buffer += (((pb & 0xfc) != 0) ? "," : "") + "A";
|
||||
if ((pb & 0x01) != 0)
|
||||
buffer += (((pb & 0xfe) != 0) ? "," : "") + "CC";
|
||||
break;
|
||||
case 0x35: // PULS
|
||||
case 0x37: // PULU
|
||||
pb = operandarray[0];
|
||||
if ((pb & 0x01) != 0)
|
||||
buffer += "CC";
|
||||
if ((pb & 0x02) != 0)
|
||||
buffer += (((pb & 0x01) != 0) ? "," : "") + "A";
|
||||
if ((pb & 0x04) != 0)
|
||||
buffer += (((pb & 0x03) != 0) ? "," : "") + "B";
|
||||
if ((pb & 0x08) != 0)
|
||||
buffer += (((pb & 0x07) != 0) ? "," : "") + "DP";
|
||||
if ((pb & 0x10) != 0)
|
||||
buffer += (((pb & 0x0f) != 0) ? "," : "") + "X";
|
||||
if ((pb & 0x20) != 0)
|
||||
buffer += (((pb & 0x1f) != 0) ? "," : "") + "Y";
|
||||
if ((pb & 0x40) != 0)
|
||||
buffer += (((pb & 0x3f) != 0) ? "," : "") + ((opcode == 0x35) ? "U" : "S");
|
||||
if ((pb & 0x80) != 0)
|
||||
buffer += (((pb & 0x7f) != 0) ? "," : "") + "PC ; (PUL? PC=RTS)";
|
||||
break;
|
||||
default:
|
||||
// No operands
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case m6809_addressing_modes.DIR:
|
||||
ea = operandarray[0];
|
||||
buffer += ea.ToString("X2");
|
||||
break;
|
||||
|
||||
case m6809_addressing_modes.REL:
|
||||
offset = (sbyte)operandarray[0];
|
||||
buffer += ((ppc + offset) & 0xffff).ToString("X4");
|
||||
break;
|
||||
|
||||
case m6809_addressing_modes.LREL:
|
||||
offset = (short)((operandarray[0] << 8) + operandarray[1]);
|
||||
buffer += ((ppc + offset) & 0xffff).ToString("X4");
|
||||
break;
|
||||
|
||||
case m6809_addressing_modes.EXT:
|
||||
ea = ((operandarray[0] << 8) + operandarray[1]);
|
||||
buffer += ea.ToString("X4");
|
||||
break;
|
||||
|
||||
case m6809_addressing_modes.IND:
|
||||
pb = operandarray[0];
|
||||
reg = (byte)((pb >> 5) & 3);
|
||||
pbm = (byte)(pb & 0x8f);
|
||||
indirect = ((pb & 0x90) == 0x90) ? true : false;
|
||||
// open brackets if indirect
|
||||
if (indirect && pbm != 0x80 && pbm != 0x82)
|
||||
buffer += "[";
|
||||
switch (pbm)
|
||||
{
|
||||
case 0x80: // ,R+
|
||||
if (indirect)
|
||||
buffer = "Illegal Postbyte";
|
||||
else
|
||||
buffer += "," + m6809_regs[reg] + "+";
|
||||
break;
|
||||
|
||||
case 0x81: // ,R++
|
||||
buffer += "," + m6809_regs[reg] + "++";
|
||||
break;
|
||||
|
||||
case 0x82: // ,-R
|
||||
if (indirect)
|
||||
buffer = "Illegal Postbyte";
|
||||
else
|
||||
buffer += ",-" + m6809_regs[reg];
|
||||
break;
|
||||
|
||||
case 0x83: // ,--R
|
||||
buffer += ",--" + m6809_regs[reg];
|
||||
break;
|
||||
|
||||
case 0x84: // ,R
|
||||
buffer += "," + m6809_regs[reg];
|
||||
break;
|
||||
|
||||
case 0x85: // (+/- B),R
|
||||
buffer += "B," + m6809_regs[reg];
|
||||
break;
|
||||
|
||||
case 0x86: // (+/- A),R
|
||||
buffer += "A," + m6809_regs[reg];
|
||||
break;
|
||||
|
||||
case 0x87:
|
||||
buffer = "Illegal Postbyte";
|
||||
break;
|
||||
|
||||
case 0x88: // (+/- 7 bit offset),R
|
||||
offset = (sbyte)ReadOpArg(p);
|
||||
p++;
|
||||
buffer += ((offset < 0) ? "-" : "");
|
||||
buffer += ((offset < 0) ? -offset : offset).ToString("X2");
|
||||
buffer += m6809_regs[reg];
|
||||
break;
|
||||
|
||||
case 0x89: // (+/- 15 bit offset),R
|
||||
offset = (short)((ReadOpArg(p) << 8) + ReadOpArg((ushort)(p + 1)));
|
||||
p += 2;
|
||||
buffer += ((offset < 0) ? "-" : "");
|
||||
buffer += ((offset < 0) ? -offset : offset).ToString("X4");
|
||||
buffer += m6809_regs[reg];
|
||||
break;
|
||||
|
||||
case 0x8a:
|
||||
buffer = "Illegal Postbyte";
|
||||
break;
|
||||
|
||||
case 0x8b: // (+/- D),R
|
||||
buffer += "D," + m6809_regs[reg];
|
||||
break;
|
||||
|
||||
case 0x8c: // (+/- 7 bit offset),PC
|
||||
offset = (sbyte)ReadOpArg(p);
|
||||
p++;
|
||||
buffer += ((offset < 0) ? "-" : "");
|
||||
buffer += "$" + ((offset < 0) ? -offset : offset).ToString("X2") + ",PC";
|
||||
break;
|
||||
|
||||
case 0x8d: // (+/- 15 bit offset),PC
|
||||
offset = (short)((ReadOpArg(p) << 8) + ReadOpArg((ushort)(p + 1)));
|
||||
p += 2;
|
||||
buffer += ((offset < 0) ? "-" : "");
|
||||
buffer += "$" + ((offset < 0) ? -offset : offset).ToString("X4") + ",PC";
|
||||
break;
|
||||
|
||||
case 0x8e:
|
||||
buffer = "Illegal Postbyte";
|
||||
break;
|
||||
|
||||
case 0x8f: // address
|
||||
ea = (short)((ReadOpArg(p) << 8) + ReadOpArg((ushort)(p + 1)));
|
||||
p += 2;
|
||||
buffer += "$" + ea.ToString("X4");
|
||||
break;
|
||||
|
||||
default: // (+/- 4 bit offset),R
|
||||
offset = pb & 0x1f;
|
||||
if (offset > 15)
|
||||
offset = offset - 32;
|
||||
buffer += ((offset < 0) ? "-" : "");
|
||||
buffer += "$" + ((offset < 0) ? -offset : offset).ToString("X") + ",";
|
||||
buffer += m6809_regs[reg];
|
||||
break;
|
||||
}
|
||||
|
||||
// close brackets if indirect
|
||||
if (indirect && pbm != 0x80 && pbm != 0x82)
|
||||
buffer += "]";
|
||||
break;
|
||||
|
||||
case m6809_addressing_modes.IMM:
|
||||
if (numoperands == 2)
|
||||
{
|
||||
ea = (operandarray[0] << 8) + operandarray[1];
|
||||
buffer += "#$" + ea.ToString("X4");
|
||||
}
|
||||
else
|
||||
if (numoperands == 1)
|
||||
{
|
||||
ea = operandarray[0];
|
||||
buffer += "#$" + ea.ToString("X2");
|
||||
}
|
||||
break;
|
||||
|
||||
case m6809_addressing_modes.IMM_RR:
|
||||
pb = operandarray[0];
|
||||
buffer += m6809_regs_te[(pb >> 4) & 0xf] + "," + m6809_regs_te[pb & 0xf];
|
||||
break;
|
||||
}
|
||||
return buffer;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,11 +0,0 @@
|
||||
fileFormatVersion: 2
|
||||
guid: 05a5a82c4182e0f4082c1e8329ddde79
|
||||
MonoImporter:
|
||||
externalObjects: {}
|
||||
serializedVersion: 2
|
||||
defaultReferences: []
|
||||
executionOrder: 0
|
||||
icon: {instanceID: 0}
|
||||
userData:
|
||||
assetBundleName:
|
||||
assetBundleVariant:
|
||||
@ -24,8 +24,6 @@ namespace cpu.m6809
|
||||
public Action<ushort, byte> WriteIO;
|
||||
public delegate int irq_delegate(int irqline);
|
||||
public irq_delegate irq_callback;
|
||||
public delegate void debug_delegate();
|
||||
//public debug_delegate debugger_start_cpu_hook_callback, debugger_stop_cpu_hook_callback;
|
||||
private ulong totalExecutedCycles;
|
||||
private int pendingCycles;
|
||||
public override ulong TotalExecutedCycles
|
||||
@ -563,7 +561,6 @@ namespace cpu.m6809
|
||||
extra_cycles = 0;
|
||||
if ((int_state & (M6809_CWAI | M6809_SYNC)) != 0)
|
||||
{
|
||||
//debugger_instruction_hook(Machine, PCD);
|
||||
pendingCycles = 0;
|
||||
}
|
||||
else
|
||||
@ -572,13 +569,10 @@ namespace cpu.m6809
|
||||
{
|
||||
int prevCycles = pendingCycles;
|
||||
PPC = PC;
|
||||
//debugger_instruction_hook(Machine, PCD);
|
||||
ireg = ReadOp(PC.LowWord);
|
||||
PC.LowWord++;
|
||||
//debugger_start_cpu_hook_callback();
|
||||
insn[ireg]();
|
||||
pendingCycles -= cycles_6809[ireg];
|
||||
//debugger_stop_cpu_hook_callback();
|
||||
int delta = prevCycles - pendingCycles;
|
||||
totalExecutedCycles += (ulong)delta;
|
||||
} while (pendingCycles > 0);
|
||||
|
||||
@ -1,693 +0,0 @@
|
||||
//http://www.zophar.net/fileuploads/2/10819kouzv/z80undoc.html
|
||||
|
||||
//TODO: ex. (IX+00h) could be turned into (IX)
|
||||
|
||||
//usage:
|
||||
//VgMuseum.Z80.Disassembler disasm = new Disassembler();
|
||||
//ushort pc = RegPC.Word;
|
||||
//string str = disasm.Disassemble(() => ReadMemory(pc++));
|
||||
//EmuLogger.Log(str);
|
||||
|
||||
//please note that however much youre tempted to, timings can't be put in a table here because they depend on how the instruction executes at runtime
|
||||
|
||||
using System;
|
||||
|
||||
namespace cpu.z80
|
||||
{
|
||||
public class Disassembler
|
||||
{
|
||||
public static sbyte[,] opcodeSizes = new sbyte[9, 256];
|
||||
|
||||
public static void GenerateOpcodeSizes()
|
||||
{
|
||||
Disassembler disasm = new Disassembler();
|
||||
|
||||
for (int i = 0; i < 256; i++)
|
||||
{
|
||||
int pc = 0;
|
||||
byte[] opcode = { (byte)i, 0, 0, 0 };
|
||||
disasm.Disassemble(() => opcode[pc++]);
|
||||
opcodeSizes[0, i] = (sbyte)pc;
|
||||
}
|
||||
|
||||
opcodeSizes[0, 0xCB] = -1;
|
||||
opcodeSizes[0, 0xED] = -2;
|
||||
opcodeSizes[0, 0xDD] = -3;
|
||||
opcodeSizes[0, 0xFD] = -4;
|
||||
|
||||
for (int i = 0; i < 256; i++)
|
||||
{
|
||||
int pc = 0;
|
||||
byte[] opcode = { 0xCB, (byte)i, 0, 0, 0 };
|
||||
disasm.Disassemble(() => opcode[pc++]);
|
||||
opcodeSizes[1, i] = (sbyte)pc;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 256; i++)
|
||||
{
|
||||
int pc = 0;
|
||||
byte[] opcode = { 0xED, (byte)i, 0, 0, 0 };
|
||||
disasm.Disassemble(() => opcode[pc++]);
|
||||
opcodeSizes[2, i] = (sbyte)pc;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 256; i++)
|
||||
{
|
||||
int pc = 0;
|
||||
byte[] opcode = { 0xDD, (byte)i, 0, 0, 0 };
|
||||
disasm.Disassemble(() => opcode[pc++]);
|
||||
opcodeSizes[3, i] = (sbyte)pc;
|
||||
}
|
||||
|
||||
opcodeSizes[3, 0xCB] = -5;
|
||||
opcodeSizes[3, 0xED] = -2;
|
||||
|
||||
for (int i = 0; i < 256; i++)
|
||||
{
|
||||
int pc = 0;
|
||||
byte[] opcode = { 0xFD, (byte)i, 0, 0, 0 };
|
||||
disasm.Disassemble(() => opcode[pc++]);
|
||||
opcodeSizes[4, i] = (sbyte)pc;
|
||||
}
|
||||
|
||||
opcodeSizes[4, 0xCB] = -6;
|
||||
opcodeSizes[4, 0xED] = -2;
|
||||
|
||||
|
||||
for (int i = 0; i < 256; i++)
|
||||
{
|
||||
int pc = 0;
|
||||
byte[] opcode = { 0xDD, 0xCB, (byte)i, 0, 0, 0 };
|
||||
disasm.Disassemble(() => opcode[pc++]);
|
||||
opcodeSizes[5, i] = (sbyte)pc;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 256; i++)
|
||||
{
|
||||
int pc = 0;
|
||||
byte[] opcode = { 0xFD, 0xCB, (byte)i, 0, 0, 0 };
|
||||
disasm.Disassemble(() => opcode[pc++]);
|
||||
opcodeSizes[6, i] = (sbyte)pc;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 256; i++)
|
||||
{
|
||||
int pc = 0;
|
||||
byte[] opcode = { 0xDD, 0xED, (byte)i, 0, 0, 0 };
|
||||
disasm.Disassemble(() => opcode[pc++]);
|
||||
opcodeSizes[7, i] = (sbyte)pc;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 256; i++)
|
||||
{
|
||||
int pc = 0;
|
||||
byte[] opcode = { 0xFD, 0xED, (byte)i, 0, 0, 0 };
|
||||
disasm.Disassemble(() => opcode[pc++]);
|
||||
opcodeSizes[8, i] = (sbyte)pc;
|
||||
}
|
||||
}
|
||||
|
||||
static string Result(string format, Func<byte> read)
|
||||
{
|
||||
//d immediately succeeds the opcode
|
||||
//n immediate succeeds the opcode and the displacement (if present)
|
||||
//nn immediately succeeds the opcode and the displacement (if present)
|
||||
if (format.IndexOf("nn") != -1)
|
||||
{
|
||||
byte B = read();
|
||||
byte C = read();
|
||||
format = format.Replace("nn", string.Format("{0:X4}h", B + C * 256));
|
||||
}
|
||||
|
||||
if (format.IndexOf("n") != -1)
|
||||
{
|
||||
byte B = read();
|
||||
format = format.Replace("n", string.Format("{0:X2}h", B));
|
||||
}
|
||||
|
||||
if (format.IndexOf("+d") != -1) format = format.Replace("+d", "d");
|
||||
|
||||
if (format.IndexOf("d") != -1)
|
||||
{
|
||||
byte B = read();
|
||||
bool neg = ((B & 0x80) != 0);
|
||||
char sign = neg ? '-' : '+';
|
||||
int val = neg ? 256 - B : B;
|
||||
format = format.Replace("d", string.Format("{0}{1:X2}h", sign, val));
|
||||
}
|
||||
|
||||
return format;
|
||||
}
|
||||
|
||||
readonly static string[] mnemonics = new string[]
|
||||
{
|
||||
"NOP", "LD BC, nn", "LD (BC), A", "INC BC", //0x04
|
||||
"INC B", "DEC B", "LD B, n", "RLCA", //0x08
|
||||
"EX AF, AF'", "ADD HL, BC", "LD A, (BC)", "DEC BC", //0x0C
|
||||
"INC C", "DEC C", "LD C, n", "RRCA", //0x10
|
||||
"DJNZ d", "LD DE, nn", "LD (DE), A", "INC DE", //0x14
|
||||
"INC D", "DEC D", "LD D, n", "RLA", //0x18
|
||||
"JR d", "ADD HL, DE", "LD A, (DE)", "DEC DE", //0x1C
|
||||
"INC E", "DEC E", "LD E, n", "RRA", //0x20
|
||||
"JR NZ, d", "LD HL, nn", "LD (nn), HL", "INC HL", //0x24
|
||||
"INC H", "DEC H", "LD H, n", "DAA", //0x28
|
||||
"JR Z, d", "ADD HL, HL", "LD HL, (nn)", "DEC HL", //0x2C
|
||||
"INC L", "DEC L", "LD L, n", "CPL", //0x30
|
||||
"JR NC, d", "LD SP, nn", "LD (nn), A", "INC SP", //0x34
|
||||
"INC (HL)", "DEC (HL)", "LD (HL), n", "SCF", //0x38
|
||||
"JR C, d", "ADD HL, SP", "LD A, (nn)", "DEC SP", //0x3C
|
||||
"INC A", "DEC A", "LD A, n", "CCF", //0x40
|
||||
"LD B, B", "LD B, C", "LD B, D", "LD B, E", //0x44
|
||||
"LD B, H", "LD B, L", "LD B, (HL)", "LD B, A", //0x48
|
||||
"LD C, B", "LD C, C", "LD C, D", "LD C, E", //0x4C
|
||||
"LD C, H", "LD C, L", "LD C, (HL)", "LD C, A", //0x50
|
||||
"LD D, B", "LD D, C", "LD D, D", "LD D, E", //0x54
|
||||
"LD D, H", "LD D, L", "LD D, (HL)", "LD D, A", //0x58
|
||||
"LD E, B", "LD E, C", "LD E, D", "LD E, E", //0x5C
|
||||
"LD E, H", "LD E, L", "LD E, (HL)", "LD E, A", //0x60
|
||||
"LD H, B", "LD H, C", "LD H, D", "LD H, E", //0x64
|
||||
"LD H, H", "LD H, L", "LD H, (HL)", "LD H, A", //0x68
|
||||
"LD L, B", "LD L, B", "LD L, D", "LD L, E", //0x6C
|
||||
"LD L, H", "LD L, L", "LD L, (HL)", "LD L, A", //0x70
|
||||
"LD (HL), B", "LD (HL), C", "LD (HL), D", "LD (HL), E", //0x74
|
||||
"LD (HL), H", "LD (HL), L", "HALT", "LD (HL), A", //0x78
|
||||
"LD A, B", "LD A, C", "LD A, D", "LD A, E", //0x7C
|
||||
"LD A, H", "LD A, L", "LD A, (HL)", "LD A, A", //0x80
|
||||
"ADD A, B", "ADD A, C", "ADD A, D", "ADD A, E", //0x84
|
||||
"ADD A, H", "ADD A, L", "ADD A, (HL)", "ADD A, A", //0x88
|
||||
"ADC A, B", "ADC A, C", "ADC A, D", "ADC A, E", //0x8C
|
||||
"ADC A, H", "ADC A, L", "ADC A, (HL)", "ADC A, A", //0x90
|
||||
"SUB A, B", "SUB A, C", "SUB A, D", "SUB A, E", //0x94
|
||||
"SUB A, H", "SUB A, L", "SUB A, (HL)", "SUB A, A", //0x98
|
||||
"SBC A, B", "SBC A, C", "SBC A, D", "SBC A, E", //0x9C
|
||||
"SBC A, H", "SBC A, L", "SBC A, (HL)", "SBC A, A", //0xA0
|
||||
"AND B", "AND C", "AND D", "AND E", //0xA4
|
||||
"AND H", "AND L", "AND (HL)", "AND A", //0xA8
|
||||
"XOR B", "XOR C", "XOR D", "XOR E", //0xAC
|
||||
"XOR H", "XOR L", "XOR (HL)", "XOR A", //0xB0
|
||||
"OR B", "OR C", "OR D", "OR E", //0xB4
|
||||
"OR H", "OR L", "OR (HL)", "OR A", //0xB8
|
||||
"CP B", "CP C", "CP D", "CP E", //0xBC
|
||||
"CP H", "CP L", "CP (HL)", "CP A", //0xC0
|
||||
"RET NZ", "POP BC", "JP NZ, nn", "JP nn", //0xC4
|
||||
"CALL NZ, nn", "PUSH BC", "ADD A, n", "RST $00", //0xC8
|
||||
"RET Z", "RET", "JP Z, nn", "[CB]", //0xCC
|
||||
"CALL Z, nn", "CALL nn", "ADC A, n", "RST $08", //0xD0
|
||||
"RET NC", "POP DE", "JP NC, nn", "OUT n, A", //0xD4
|
||||
"CALL NC, nn", "PUSH DE", "SUB n", "RST $10", //0xD8
|
||||
"RET C", "EXX", "JP C, nn", "IN A, n", //0xDC
|
||||
"CALL C, nn", "[DD]", "SBC A, n", "RST $18", //0xE0
|
||||
"RET PO", "POP HL", "JP PO, nn", "EX (SP), HL", //0xE4
|
||||
"CALL C, nn", "PUSH HL", "AND n", "RST $20", //0xE8
|
||||
"RET PE", "JP HL", "JP PE, nn", "EX DE, HL", //0xEC
|
||||
"CALL PE, nn", "[ED]", "XOR n", "RST $28", //0xF0
|
||||
"RET P", "POP AF", "JP P, nn", "DI", //0xF4
|
||||
"CALL P, nn", "PUSH AF", "OR n", "RST $30", //0xF8
|
||||
"RET M", "LD SP, HL", "JP M, nn", "EI", //0xFC
|
||||
"CALL M, nn", "[FD]", "CP n", "RST $38", //0x100
|
||||
};
|
||||
|
||||
readonly static string[] mnemonicsDD = new string[]
|
||||
{
|
||||
"NOP", "LD BC, nn", "LD (BC), A", "INC BC", //0x04
|
||||
"INC B", "DEC B", "LD B, n", "RLCA", //0x08
|
||||
"EX AF, AF'", "ADD IX, BC", "LD A, (BC)", "DEC BC", //0x0C
|
||||
"INC C", "DEC C", "LD C, n", "RRCA", //0x10
|
||||
"DJNZ d", "LD DE, nn", "LD (DE), A", "INC DE", //0x14
|
||||
"INC D", "DEC D", "LD D, n", "RLA", //0x18
|
||||
"JR d", "ADD IX, DE", "LD A, (DE)", "DEC DE", //0x1C
|
||||
"INC E", "DEC E", "LD E, n", "RRA", //0x20
|
||||
"JR NZ, d", "LD IX, nn", "LD (nn), IX", "INC IX", //0x24
|
||||
"INC IXH", "DEC IXH", "LD IXH, n", "DAA", //0x28
|
||||
"JR Z, d", "ADD IX, IX", "LD IX, (nn)", "DEC IX", //0x2C
|
||||
"INC IXL", "DEC IXL", "LD IXL, n", "CPL", //0x30
|
||||
"JR NC, d", "LD SP, nn", "LD (nn), A", "INC SP", //0x34
|
||||
"INC (IX+d)", "DEC (IX+d)", "LD (IX+d), n", "SCF", //0x38
|
||||
"JR C, d", "ADD IX, SP", "LD A, (nn)", "DEC SP", //0x3C
|
||||
"INC A", "DEC A", "LD A, n", "CCF", //0x40
|
||||
"LD B, B", "LD B, C", "LD B, D", "LD B, E", //0x44
|
||||
"LD B, IXH", "LD B, IXL", "LD B, (IX+d)", "LD B, A", //0x48
|
||||
"LD C, B", "LD C, C", "LD C, D", "LD C, E", //0x4C
|
||||
"LD C, IXH", "LD C, IXL", "LD C, (IX+d)", "LD C, A", //0x50
|
||||
"LD D, B", "LD D, C", "LD D, D", "LD D, E", //0x54
|
||||
"LD D, IXH", "LD D, IXL", "LD D, (IX+d)", "LD D, A", //0x58
|
||||
"LD E, B", "LD E, C", "LD E, D", "LD E, E", //0x5C
|
||||
"LD E, IXH", "LD E, IXL", "LD E, (IX+d)", "LD E, A", //0x60
|
||||
"LD IXH, B", "LD IXH, C", "LD IXH, D", "LD IXH, E", //0x64
|
||||
"LD IXH, IXH", "LD IXH, IXL", "LD H, (IX+d)", "LD IXH, A", //0x68
|
||||
"LD IXL, B", "LD IXL, C", "LD IXL, D", "LD IXL, E", //0x6C
|
||||
"LD IXL, IXH", "LD IXL, IXL", "LD L, (IX+d)", "LD IXL, A", //0x70
|
||||
"LD (IX+d), B", "LD (IX+d), C", "LD (IX+d), D", "LD (IX+d), E", //0x74
|
||||
"LD (IX+d), H", "LD (IX+d), L", "HALT", "LD (IX+d), A", //0x78
|
||||
"LD A, B", "LD A, C", "LD A, D", "LD A, E", //0x7C
|
||||
"LD A, IXH", "LD A, IXL", "LD A, (IX+d)", "LD A, A", //0x80
|
||||
"ADD A, B", "ADD A, C", "ADD A, D", "ADD A, E", //0x84
|
||||
"ADD A, IXH", "ADD A, IXL", "ADD A, (IX+d)", "ADD A, A", //0x88
|
||||
"ADC A, B", "ADC A, C", "ADC A, D", "ADC A, E", //0x8C
|
||||
"ADC A, IXH", "ADC A, IXL", "ADC A, (IX+d)", "ADC A, A", //0x90
|
||||
"SUB A, B", "SUB A, C", "SUB A, D", "SUB A, E", //0x94
|
||||
"SUB A, IXH", "SUB A, IXL", "SUB A, (IX+d)", "SUB A, A", //0x98
|
||||
"SBC A, B", "SBC A, C", "SBC A, D", "SBC A, E", //0x9C
|
||||
"SBC A, IXH", "SBC A, IXL", "SBC A, (IX+d)", "SBC A, A", //0xA0
|
||||
"AND B", "AND C", "AND D", "AND E", //0xA4
|
||||
"AND IXH", "AND IXL", "AND (IX+d)", "AND A", //0xA8
|
||||
"XOR B", "XOR C", "XOR D", "XOR E", //0xAC
|
||||
"XOR IXH", "XOR IXL", "XOR (IX+d)", "XOR A", //0xB0
|
||||
"OR B", "OR C", "OR D", "OR E", //0xB4
|
||||
"OR IXH", "OR IXL", "OR (IX+d)", "OR A", //0xB8
|
||||
"CP B", "CP C", "CP D", "CP E", //0xBC
|
||||
"CP IXH", "CP IXL", "CP (IX+d)", "CP A", //0xC0
|
||||
"RET NZ", "POP BC", "JP NZ, nn", "JP nn", //0xC4
|
||||
"CALL NZ, nn", "PUSH BC", "ADD A, n", "RST $00", //0xC8
|
||||
"RET Z", "RET", "JP Z, nn", "[DD CB]", //0xCC
|
||||
"CALL Z, nn", "CALL nn", "ADC A, n", "RST $08", //0xD0
|
||||
"RET NC", "POP DE", "JP NC, nn", "OUT n, A", //0xD4
|
||||
"CALL NC, nn", "PUSH DE", "SUB n", "RST $10", //0xD8
|
||||
"RET C", "EXX", "JP C, nn", "IN A, n", //0xDC
|
||||
"CALL C, nn", "[!DD DD!]", "SBC A, n", "RST $18", //0xE0
|
||||
"RET PO", "POP IX", "JP PO, nn", "EX (SP), IX", //0xE4
|
||||
"CALL C, nn", "PUSH IX", "AND n", "RST $20", //0xE8
|
||||
"RET PE", "JP IX", "JP PE, nn", "EX DE, HL", //0xEC
|
||||
"CALL PE, nn", "[DD ED]", "XOR n", "RST $28", //0xF0
|
||||
"RET P", "POP AF", "JP P, nn", "DI", //0xF4
|
||||
"CALL P, nn", "PUSH AF", "OR n", "RST $30", //0xF8
|
||||
"RET M", "LD SP, IX", "JP M, nn", "EI", //0xFC
|
||||
"CALL M, nn", "[!!DD FD!!]", "CP n", "RST $38", //0x100
|
||||
};
|
||||
|
||||
readonly static string[] mnemonicsFD = new string[]
|
||||
{
|
||||
"NOP", "LD BC, nn", "LD (BC), A", "INC BC", //0x04
|
||||
"INC B", "DEC B", "LD B, n", "RLCA", //0x08
|
||||
"EX AF, AF'", "ADD IY, BC", "LD A, (BC)", "DEC BC", //0x0C
|
||||
"INC C", "DEC C", "LD C, n", "RRCA", //0x10
|
||||
"DJNZ d", "LD DE, nn", "LD (DE), A", "INC DE", //0x14
|
||||
"INC D", "DEC D", "LD D, n", "RLA", //0x18
|
||||
"JR d", "ADD IY, DE", "LD A, (DE)", "DEC DE", //0x1C
|
||||
"INC E", "DEC E", "LD E, n", "RRA", //0x20
|
||||
"JR NZ, d", "LD IY, nn", "LD (nn), IY", "INC IY", //0x24
|
||||
"INC IYH", "DEC IYH", "LD IYH, n", "DAA", //0x28
|
||||
"JR Z, d", "ADD IY, IY", "LD IY, (nn)", "DEC IY", //0x2C
|
||||
"INC IYL", "DEC IYL", "LD IYL, n", "CPL", //0x30
|
||||
"JR NC, d", "LD SP, nn", "LD (nn), A", "INC SP", //0x34
|
||||
"INC (IY+d)", "DEC (IY+d)", "LD (IY+d), n", "SCF", //0x38
|
||||
"JR C, d", "ADD IY, SP", "LD A, (nn)", "DEC SP", //0x3C
|
||||
"INC A", "DEC A", "LD A, n", "CCF", //0x40
|
||||
"LD B, B", "LD B, C", "LD B, D", "LD B, E", //0x44
|
||||
"LD B, IYH", "LD B, IYL", "LD B, (IY+d)", "LD B, A", //0x48
|
||||
"LD C, B", "LD C, C", "LD C, D", "LD C, E", //0x4C
|
||||
"LD C, IYH", "LD C, IYL", "LD C, (IY+d)", "LD C, A", //0x50
|
||||
"LD D, B", "LD D, C", "LD D, D", "LD D, E", //0x54
|
||||
"LD D, IYH", "LD D, IYL", "LD D, (IY+d)", "LD D, A", //0x58
|
||||
"LD E, B", "LD E, C", "LD E, D", "LD E, E", //0x5C
|
||||
"LD E, IYH", "LD E, IYL", "LD E, (IY+d)", "LD E, A", //0x60
|
||||
"LD IYH, B", "LD IYH, C", "LD IYH, D", "LD IYH, E", //0x64
|
||||
"LD IYH, IYH", "LD IYH, IYL", "LD H, (IY+d)", "LD IYH, A", //0x68
|
||||
"LD IYL, B", "LD IYL, C", "LD IYL, D", "LD IYL, E", //0x6C
|
||||
"LD IYL, IYH", "LD IYL, IYL", "LD L, (IY+d)", "LD IYL, A", //0x70
|
||||
"LD (IY+d), B", "LD (IY+d), C", "LD (IY+d), D", "LD (IY+d), E", //0x74
|
||||
"LD (IY+d), H", "LD (IY+d), L", "HALT", "LD (IY+d), A", //0x78
|
||||
"LD A, B", "LD A, C", "LD A, D", "LD A, E", //0x7C
|
||||
"LD A, IYH", "LD A, IYL", "LD A, (IY+d)", "LD A, A", //0x80
|
||||
"ADD A, B", "ADD A, C", "ADD A, D", "ADD A, E", //0x84
|
||||
"ADD A, IYH", "ADD A, IYL", "ADD A, (IY+d)", "ADD A, A", //0x88
|
||||
"ADC A, B", "ADC A, C", "ADC A, D", "ADC A, E", //0x8C
|
||||
"ADC A, IYH", "ADC A, IYL", "ADC A, (IY+d)", "ADC A, A", //0x90
|
||||
"SUB A, B", "SUB A, C", "SUB A, D", "SUB A, E", //0x94
|
||||
"SUB A, IYH", "SUB A, IYL", "SUB A, (IY+d)", "SUB A, A", //0x98
|
||||
"SBC A, B", "SBC A, C", "SBC A, D", "SBC A, E", //0x9C
|
||||
"SBC A, IYH", "SBC A, IYL", "SBC A, (IY+d)", "SBC A, A", //0xA0
|
||||
"AND B", "AND C", "AND D", "AND E", //0xA4
|
||||
"AND IYH", "AND IYL", "AND (IY+d)", "AND A", //0xA8
|
||||
"XOR B", "XOR C", "XOR D", "XOR E", //0xAC
|
||||
"XOR IYH", "XOR IYL", "XOR (IY+d)", "XOR A", //0xB0
|
||||
"OR B", "OR C", "OR D", "OR E", //0xB4
|
||||
"OR IYH", "OR IYL", "OR (IY+d)", "OR A", //0xB8
|
||||
"CP B", "CP C", "CP D", "CP E", //0xBC
|
||||
"CP IYH", "CP IYL", "CP (IY+d)", "CP A", //0xC0
|
||||
"RET NZ", "POP BC", "JP NZ, nn", "JP nn", //0xC4
|
||||
"CALL NZ, nn", "PUSH BC", "ADD A, n", "RST $00", //0xC8
|
||||
"RET Z", "RET", "JP Z, nn", "[DD CB]", //0xCC
|
||||
"CALL Z, nn", "CALL nn", "ADC A, n", "RST $08", //0xD0
|
||||
"RET NC", "POP DE", "JP NC, nn", "OUT n, A", //0xD4
|
||||
"CALL NC, nn", "PUSH DE", "SUB n", "RST $10", //0xD8
|
||||
"RET C", "EXX", "JP C, nn", "IN A, n", //0xDC
|
||||
"CALL C, nn", "[!FD DD!]", "SBC A, n", "RST $18", //0xE0
|
||||
"RET PO", "POP IY", "JP PO, nn", "EX (SP), IY", //0xE4
|
||||
"CALL C, nn", "PUSH IY", "AND n", "RST $20", //0xE8
|
||||
"RET PE", "JP IY", "JP PE, nn", "EX DE, HL", //0xEC
|
||||
"CALL PE, nn", "[FD ED]", "XOR n", "RST $28", //0xF0
|
||||
"RET P", "POP AF", "JP P, nn", "DI", //0xF4
|
||||
"CALL P, nn", "PUSH AF", "OR n", "RST $30", //0xF8
|
||||
"RET M", "LD SP, IY", "JP M, nn", "EI", //0xFC
|
||||
"CALL M, nn", "[!FD FD!]", "CP n", "RST $38", //0x100
|
||||
};
|
||||
|
||||
readonly static string[] mnemonicsDDCB = new string[]
|
||||
{
|
||||
"RLC (IX+d)->B", "RLC (IX+d)->C", "RLC (IX+d)->D", "RLC (IX+d)->E", "RLC (IX+d)->H", "RLC (IX+d)->L", "RLC (IX+d)", "RLC (IX+d)->A",
|
||||
"RRC (IX+d)->B", "RRC (IX+d)->C", "RRC (IX+d)->D", "RRC (IX+d)->E", "RRC (IX+d)->H", "RRC (IX+d)->L", "RRC (IX+d)", "RRC (IX+d)->A",
|
||||
"RL (IX+d)->B", "RL (IX+d)->C", "RL (IX+d)->D", "RL (IX+d)->E", "RL (IX+d)->H", "RL (IX+d)->L", "RL (IX+d)", "RL (IX+d)->A",
|
||||
"RR (IX+d)->B", "RR (IX+d)->C", "RR (IX+d)->D", "RR (IX+d)->E", "RR (IX+d)->H", "RR (IX+d)->L", "RR (IX+d)", "RR (IX+d)->A",
|
||||
"SLA (IX+d)->B", "SLA (IX+d)->C", "SLA (IX+d)->D", "SLA (IX+d)->E", "SLA (IX+d)->H", "SLA (IX+d)->L", "SLA (IX+d)", "SLA (IX+d)->A",
|
||||
"SRA (IX+d)->B", "SRA (IX+d)->C", "SRA (IX+d)->D", "SRA (IX+d)->E", "SRA (IX+d)->H", "SRA (IX+d)->L", "SRA (IX+d)", "SRA (IX+d)->A",
|
||||
"SL1 (IX+d)->B", "SL1 (IX+d)->C", "SL1 (IX+d)->D", "SL1 (IX+d)->E", "SL1 (IX+d)->H", "SL1 (IX+d)->L", "SL1 (IX+d)", "SL1 (IX+d)->A",
|
||||
"SRL (IX+d)->B", "SRL (IX+d)->C", "SRL (IX+d)->D", "SRL (IX+d)->E", "SRL (IX+d)->H", "SRL (IX+d)->L", "SRL (IX+d)", "SRL (IX+d)->A",
|
||||
"BIT 0, (IX+d)", "BIT 0, (IX+d)", "BIT 0, (IX+d)", "BIT 0, (IX+d)", "BIT 0, (IX+d)", "BIT 0, (IX+d)", "BIT 0, (IX+d)", "BIT 0, (IX+d)",
|
||||
"BIT 1, (IX+d)", "BIT 1, (IX+d)", "BIT 1, (IX+d)", "BIT 1, (IX+d)", "BIT 1, (IX+d)", "BIT 1, (IX+d)", "BIT 1, (IX+d)", "BIT 1, (IX+d)",
|
||||
"BIT 2, (IX+d)", "BIT 2, (IX+d)", "BIT 2, (IX+d)", "BIT 2, (IX+d)", "BIT 2, (IX+d)", "BIT 2, (IX+d)", "BIT 2, (IX+d)", "BIT 2, (IX+d)",
|
||||
"BIT 3, (IX+d)", "BIT 3, (IX+d)", "BIT 3, (IX+d)", "BIT 3, (IX+d)", "BIT 3, (IX+d)", "BIT 3, (IX+d)", "BIT 3, (IX+d)", "BIT 3, (IX+d)",
|
||||
"BIT 4, (IX+d)", "BIT 4, (IX+d)", "BIT 4, (IX+d)", "BIT 4, (IX+d)", "BIT 4, (IX+d)", "BIT 4, (IX+d)", "BIT 4, (IX+d)", "BIT 4, (IX+d)",
|
||||
"BIT 5, (IX+d)", "BIT 5, (IX+d)", "BIT 5, (IX+d)", "BIT 5, (IX+d)", "BIT 5, (IX+d)", "BIT 5, (IX+d)", "BIT 5, (IX+d)", "BIT 5, (IX+d)",
|
||||
"BIT 6, (IX+d)", "BIT 6, (IX+d)", "BIT 6, (IX+d)", "BIT 6, (IX+d)", "BIT 6, (IX+d)", "BIT 6, (IX+d)", "BIT 6, (IX+d)", "BIT 6, (IX+d)",
|
||||
"BIT 7, (IX+d)", "BIT 7, (IX+d)", "BIT 7, (IX+d)", "BIT 7, (IX+d)", "BIT 7, (IX+d)", "BIT 7, (IX+d)", "BIT 7, (IX+d)", "BIT 7, (IX+d)",
|
||||
"RES 0 (IX+d)->B", "RES 0 (IX+d)->C", "RES 0 (IX+d)->D", "RES 0 (IX+d)->E", "RES 0 (IX+d)->H", "RES 0 (IX+d)->L", "RES 0 (IX+d)", "RES 0 (IX+d)->A",
|
||||
"RES 1 (IX+d)->B", "RES 1 (IX+d)->C", "RES 1 (IX+d)->D", "RES 1 (IX+d)->E", "RES 1 (IX+d)->H", "RES 1 (IX+d)->L", "RES 1 (IX+d)", "RES 1 (IX+d)->A",
|
||||
"RES 2 (IX+d)->B", "RES 2 (IX+d)->C", "RES 2 (IX+d)->D", "RES 2 (IX+d)->E", "RES 2 (IX+d)->H", "RES 2 (IX+d)->L", "RES 2 (IX+d)", "RES 2 (IX+d)->A",
|
||||
"RES 3 (IX+d)->B", "RES 3 (IX+d)->C", "RES 3 (IX+d)->D", "RES 3 (IX+d)->E", "RES 3 (IX+d)->H", "RES 3 (IX+d)->L", "RES 3 (IX+d)", "RES 3 (IX+d)->A",
|
||||
"RES 4 (IX+d)->B", "RES 4 (IX+d)->C", "RES 4 (IX+d)->D", "RES 4 (IX+d)->E", "RES 4 (IX+d)->H", "RES 4 (IX+d)->L", "RES 4 (IX+d)", "RES 4 (IX+d)->A",
|
||||
"RES 5 (IX+d)->B", "RES 5 (IX+d)->C", "RES 5 (IX+d)->D", "RES 5 (IX+d)->E", "RES 5 (IX+d)->H", "RES 5 (IX+d)->L", "RES 5 (IX+d)", "RES 5 (IX+d)->A",
|
||||
"RES 6 (IX+d)->B", "RES 6 (IX+d)->C", "RES 6 (IX+d)->D", "RES 6 (IX+d)->E", "RES 6 (IX+d)->H", "RES 6 (IX+d)->L", "RES 6 (IX+d)", "RES 6 (IX+d)->A",
|
||||
"RES 7 (IX+d)->B", "RES 7 (IX+d)->C", "RES 7 (IX+d)->D", "RES 7 (IX+d)->E", "RES 7 (IX+d)->H", "RES 7 (IX+d)->L", "RES 7 (IX+d)", "RES 7 (IX+d)->A",
|
||||
"SET 0 (IX+d)->B", "SET 0 (IX+d)->C", "SET 0 (IX+d)->D", "SET 0 (IX+d)->E", "SET 0 (IX+d)->H", "SET 0 (IX+d)->L", "SET 0 (IX+d)", "SET 0 (IX+d)->A",
|
||||
"SET 1 (IX+d)->B", "SET 1 (IX+d)->C", "SET 1 (IX+d)->D", "SET 1 (IX+d)->E", "SET 1 (IX+d)->H", "SET 1 (IX+d)->L", "SET 1 (IX+d)", "SET 1 (IX+d)->A",
|
||||
"SET 2 (IX+d)->B", "SET 2 (IX+d)->C", "SET 2 (IX+d)->D", "SET 2 (IX+d)->E", "SET 2 (IX+d)->H", "SET 2 (IX+d)->L", "SET 2 (IX+d)", "SET 2 (IX+d)->A",
|
||||
"SET 3 (IX+d)->B", "SET 3 (IX+d)->C", "SET 3 (IX+d)->D", "SET 3 (IX+d)->E", "SET 3 (IX+d)->H", "SET 3 (IX+d)->L", "SET 3 (IX+d)", "SET 3 (IX+d)->A",
|
||||
"SET 4 (IX+d)->B", "SET 4 (IX+d)->C", "SET 4 (IX+d)->D", "SET 4 (IX+d)->E", "SET 4 (IX+d)->H", "SET 4 (IX+d)->L", "SET 4 (IX+d)", "SET 4 (IX+d)->A",
|
||||
"SET 5 (IX+d)->B", "SET 5 (IX+d)->C", "SET 5 (IX+d)->D", "SET 5 (IX+d)->E", "SET 5 (IX+d)->H", "SET 5 (IX+d)->L", "SET 5 (IX+d)", "SET 5 (IX+d)->A",
|
||||
"SET 6 (IX+d)->B", "SET 6 (IX+d)->C", "SET 6 (IX+d)->D", "SET 6 (IX+d)->E", "SET 6 (IX+d)->H", "SET 6 (IX+d)->L", "SET 6 (IX+d)", "SET 6 (IX+d)->A",
|
||||
"SET 7 (IX+d)->B", "SET 7 (IX+d)->C", "SET 7 (IX+d)->D", "SET 7 (IX+d)->E", "SET 7 (IX+d)->H", "SET 7 (IX+d)->L", "SET 7 (IX+d)", "SET 7 (IX+d)->A",
|
||||
};
|
||||
|
||||
readonly static string[] mnemonicsFDCB = new string[]
|
||||
{
|
||||
"RLC (IY+d)->B", "RLC (IY+d)->C", "RLC (IY+d)->D", "RLC (IY+d)->E", "RLC (IY+d)->H", "RLC (IY+d)->L", "RLC (IY+d)", "RLC (IY+d)->A",
|
||||
"RRC (IY+d)->B", "RRC (IY+d)->C", "RRC (IY+d)->D", "RRC (IY+d)->E", "RRC (IY+d)->H", "RRC (IY+d)->L", "RRC (IY+d)", "RRC (IY+d)->A",
|
||||
"RL (IY+d)->B", "RL (IY+d)->C", "RL (IY+d)->D", "RL (IY+d)->E", "RL (IY+d)->H", "RL (IY+d)->L", "RL (IY+d)", "RL (IY+d)->A",
|
||||
"RR (IY+d)->B", "RR (IY+d)->C", "RR (IY+d)->D", "RR (IY+d)->E", "RR (IY+d)->H", "RR (IY+d)->L", "RR (IY+d)", "RR (IY+d)->A",
|
||||
"SLA (IY+d)->B", "SLA (IY+d)->C", "SLA (IY+d)->D", "SLA (IY+d)->E", "SLA (IY+d)->H", "SLA (IY+d)->L", "SLA (IY+d)", "SLA (IY+d)->A",
|
||||
"SRA (IY+d)->B", "SRA (IY+d)->C", "SRA (IY+d)->D", "SRA (IY+d)->E", "SRA (IY+d)->H", "SRA (IY+d)->L", "SRA (IY+d)", "SRA (IY+d)->A",
|
||||
"SL1 (IY+d)->B", "SL1 (IY+d)->C", "SL1 (IY+d)->D", "SL1 (IY+d)->E", "SL1 (IY+d)->H", "SL1 (IY+d)->L", "SL1 (IY+d)", "SL1 (IY+d)->A",
|
||||
"SRL (IY+d)->B", "SRL (IY+d)->C", "SRL (IY+d)->D", "SRL (IY+d)->E", "SRL (IY+d)->H", "SRL (IY+d)->L", "SRL (IY+d)", "SRL (IY+d)->A",
|
||||
"BIT 0, (IY+d)", "BIT 0, (IY+d)", "BIT 0, (IY+d)", "BIT 0, (IY+d)", "BIT 0, (IY+d)", "BIT 0, (IY+d)", "BIT 0, (IY+d)", "BIT 0, (IY+d)",
|
||||
"BIT 1, (IY+d)", "BIT 1, (IY+d)", "BIT 1, (IY+d)", "BIT 1, (IY+d)", "BIT 1, (IY+d)", "BIT 1, (IY+d)", "BIT 1, (IY+d)", "BIT 1, (IY+d)",
|
||||
"BIT 2, (IY+d)", "BIT 2, (IY+d)", "BIT 2, (IY+d)", "BIT 2, (IY+d)", "BIT 2, (IY+d)", "BIT 2, (IY+d)", "BIT 2, (IY+d)", "BIT 2, (IY+d)",
|
||||
"BIT 3, (IY+d)", "BIT 3, (IY+d)", "BIT 3, (IY+d)", "BIT 3, (IY+d)", "BIT 3, (IY+d)", "BIT 3, (IY+d)", "BIT 3, (IY+d)", "BIT 3, (IY+d)",
|
||||
"BIT 4, (IY+d)", "BIT 4, (IY+d)", "BIT 4, (IY+d)", "BIT 4, (IY+d)", "BIT 4, (IY+d)", "BIT 4, (IY+d)", "BIT 4, (IY+d)", "BIT 4, (IY+d)",
|
||||
"BIT 5, (IY+d)", "BIT 5, (IY+d)", "BIT 5, (IY+d)", "BIT 5, (IY+d)", "BIT 5, (IY+d)", "BIT 5, (IY+d)", "BIT 5, (IY+d)", "BIT 5, (IY+d)",
|
||||
"BIT 6, (IY+d)", "BIT 6, (IY+d)", "BIT 6, (IY+d)", "BIT 6, (IY+d)", "BIT 6, (IY+d)", "BIT 6, (IY+d)", "BIT 6, (IY+d)", "BIT 6, (IY+d)",
|
||||
"BIT 7, (IY+d)", "BIT 7, (IY+d)", "BIT 7, (IY+d)", "BIT 7, (IY+d)", "BIT 7, (IY+d)", "BIT 7, (IY+d)", "BIT 7, (IY+d)", "BIT 7, (IY+d)",
|
||||
"RES 0 (IY+d)->B", "RES 0 (IY+d)->C", "RES 0 (IY+d)->D", "RES 0 (IY+d)->E", "RES 0 (IY+d)->H", "RES 0 (IY+d)->L", "RES 0 (IY+d)", "RES 0 (IY+d)->A",
|
||||
"RES 1 (IY+d)->B", "RES 1 (IY+d)->C", "RES 1 (IY+d)->D", "RES 1 (IY+d)->E", "RES 1 (IY+d)->H", "RES 1 (IY+d)->L", "RES 1 (IY+d)", "RES 1 (IY+d)->A",
|
||||
"RES 2 (IY+d)->B", "RES 2 (IY+d)->C", "RES 2 (IY+d)->D", "RES 2 (IY+d)->E", "RES 2 (IY+d)->H", "RES 2 (IY+d)->L", "RES 2 (IY+d)", "RES 2 (IY+d)->A",
|
||||
"RES 3 (IY+d)->B", "RES 3 (IY+d)->C", "RES 3 (IY+d)->D", "RES 3 (IY+d)->E", "RES 3 (IY+d)->H", "RES 3 (IY+d)->L", "RES 3 (IY+d)", "RES 3 (IY+d)->A",
|
||||
"RES 4 (IY+d)->B", "RES 4 (IY+d)->C", "RES 4 (IY+d)->D", "RES 4 (IY+d)->E", "RES 4 (IY+d)->H", "RES 4 (IY+d)->L", "RES 4 (IY+d)", "RES 4 (IY+d)->A",
|
||||
"RES 5 (IY+d)->B", "RES 5 (IY+d)->C", "RES 5 (IY+d)->D", "RES 5 (IY+d)->E", "RES 5 (IY+d)->H", "RES 5 (IY+d)->L", "RES 5 (IY+d)", "RES 5 (IY+d)->A",
|
||||
"RES 6 (IY+d)->B", "RES 6 (IY+d)->C", "RES 6 (IY+d)->D", "RES 6 (IY+d)->E", "RES 6 (IY+d)->H", "RES 6 (IY+d)->L", "RES 6 (IY+d)", "RES 6 (IY+d)->A",
|
||||
"RES 7 (IY+d)->B", "RES 7 (IY+d)->C", "RES 7 (IY+d)->D", "RES 7 (IY+d)->E", "RES 7 (IY+d)->H", "RES 7 (IY+d)->L", "RES 7 (IY+d)", "RES 7 (IY+d)->A",
|
||||
"SET 0 (IY+d)->B", "SET 0 (IY+d)->C", "SET 0 (IY+d)->D", "SET 0 (IY+d)->E", "SET 0 (IY+d)->H", "SET 0 (IY+d)->L", "SET 0 (IY+d)", "SET 0 (IY+d)->A",
|
||||
"SET 1 (IY+d)->B", "SET 1 (IY+d)->C", "SET 1 (IY+d)->D", "SET 1 (IY+d)->E", "SET 1 (IY+d)->H", "SET 1 (IY+d)->L", "SET 1 (IY+d)", "SET 1 (IY+d)->A",
|
||||
"SET 2 (IY+d)->B", "SET 2 (IY+d)->C", "SET 2 (IY+d)->D", "SET 2 (IY+d)->E", "SET 2 (IY+d)->H", "SET 2 (IY+d)->L", "SET 2 (IY+d)", "SET 2 (IY+d)->A",
|
||||
"SET 3 (IY+d)->B", "SET 3 (IY+d)->C", "SET 3 (IY+d)->D", "SET 3 (IY+d)->E", "SET 3 (IY+d)->H", "SET 3 (IY+d)->L", "SET 3 (IY+d)", "SET 3 (IY+d)->A",
|
||||
"SET 4 (IY+d)->B", "SET 4 (IY+d)->C", "SET 4 (IY+d)->D", "SET 4 (IY+d)->E", "SET 4 (IY+d)->H", "SET 4 (IY+d)->L", "SET 4 (IY+d)", "SET 4 (IY+d)->A",
|
||||
"SET 5 (IY+d)->B", "SET 5 (IY+d)->C", "SET 5 (IY+d)->D", "SET 5 (IY+d)->E", "SET 5 (IY+d)->H", "SET 5 (IY+d)->L", "SET 5 (IY+d)", "SET 5 (IY+d)->A",
|
||||
"SET 6 (IY+d)->B", "SET 6 (IY+d)->C", "SET 6 (IY+d)->D", "SET 6 (IY+d)->E", "SET 6 (IY+d)->H", "SET 6 (IY+d)->L", "SET 6 (IY+d)", "SET 6 (IY+d)->A",
|
||||
"SET 7 (IY+d)->B", "SET 7 (IY+d)->C", "SET 7 (IY+d)->D", "SET 7 (IY+d)->E", "SET 7 (IY+d)->H", "SET 7 (IY+d)->L", "SET 7 (IY+d)", "SET 7 (IY+d)->A",
|
||||
};
|
||||
|
||||
readonly static string[] mnemonicsCB = new string[]
|
||||
{
|
||||
"RLC B", "RLC C", "RLC D", "RLC E", "RLC H", "RLC L", "RLC (HL)", "RLC A",
|
||||
"RRC B", "RRC C", "RRC D", "RRC E", "RRC H", "RRC L", "RRC (HL)", "RRC A",
|
||||
"RL B", "RL C", "RL D", "RL E", "RL H", "RL L", "RL (HL)", "RL A",
|
||||
"RR B", "RR C", "RR D", "RR E", "RR H", "RR L", "RR (HL)", "RR A",
|
||||
"SLA B", "SLA C", "SLA D", "SLA E", "SLA H", "SLA L", "SLA (HL)", "SLA A",
|
||||
"SRA B", "SRA C", "SRA D", "SRA E", "SRA H", "SRA L", "SRA (HL)", "SRA A",
|
||||
"SL1 B", "SL1 C", "SL1 D", "SL1 E", "SL1 H", "SL1 L", "SL1 (HL)", "SL1 A",
|
||||
"SRL B", "SRL C", "SRL D", "SRL E", "SRL H", "SRL L", "SRL (HL)", "SRL A",
|
||||
"BIT 0, B", "BIT 0, C", "BIT 0, D", "BIT 0, E", "BIT 0, H", "BIT 0, L", "BIT 0, (HL)", "BIT 0, A",
|
||||
"BIT 1, B", "BIT 1, C", "BIT 1, D", "BIT 1, E", "BIT 1, H", "BIT 1, L", "BIT 1, (HL)", "BIT 1, A",
|
||||
"BIT 2, B", "BIT 2, C", "BIT 2, D", "BIT 2, E", "BIT 2, H", "BIT 2, L", "BIT 2, (HL)", "BIT 2, A",
|
||||
"BIT 3, B", "BIT 3, C", "BIT 3, D", "BIT 3, E", "BIT 3, H", "BIT 3, L", "BIT 3, (HL)", "BIT 3, A",
|
||||
"BIT 4, B", "BIT 4, C", "BIT 4, D", "BIT 4, E", "BIT 4, H", "BIT 4, L", "BIT 4, (HL)", "BIT 4, A",
|
||||
"BIT 5, B", "BIT 5, C", "BIT 5, D", "BIT 5, E", "BIT 5, H", "BIT 5, L", "BIT 5, (HL)", "BIT 5, A",
|
||||
"BIT 6, B", "BIT 6, C", "BIT 6, D", "BIT 6, E", "BIT 6, H", "BIT 6, L", "BIT 6, (HL)", "BIT 6, A",
|
||||
"BIT 7, B", "BIT 7, C", "BIT 7, D", "BIT 7, E", "BIT 7, H", "BIT 7, L", "BIT 7, (HL)", "BIT 7, A",
|
||||
"RES 0, B", "RES 0, C", "RES 0, D", "RES 0, E", "RES 0, H", "RES 0, L", "RES 0, (HL)", "RES 0, A",
|
||||
"RES 1, B", "RES 1, C", "RES 1, D", "RES 1, E", "RES 1, H", "RES 1, L", "RES 1, (HL)", "RES 1, A",
|
||||
"RES 2, B", "RES 2, C", "RES 2, D", "RES 2, E", "RES 2, H", "RES 2, L", "RES 2, (HL)", "RES 2, A",
|
||||
"RES 3, B", "RES 3, C", "RES 3, D", "RES 3, E", "RES 3, H", "RES 3, L", "RES 3, (HL)", "RES 3, A",
|
||||
"RES 4, B", "RES 4, C", "RES 4, D", "RES 4, E", "RES 4, H", "RES 4, L", "RES 4, (HL)", "RES 4, A",
|
||||
"RES 5, B", "RES 5, C", "RES 5, D", "RES 5, E", "RES 5, H", "RES 5, L", "RES 5, (HL)", "RES 5, A",
|
||||
"RES 6, B", "RES 6, C", "RES 6, D", "RES 6, E", "RES 6, H", "RES 6, L", "RES 6, (HL)", "RES 6, A",
|
||||
"RES 7, B", "RES 7, C", "RES 7, D", "RES 7, E", "RES 7, H", "RES 7, L", "RES 7, (HL)", "RES 7, A",
|
||||
"SET 0, B", "SET 0, C", "SET 0, D", "SET 0, E", "SET 0, H", "SET 0, L", "SET 0, (HL)", "SET 0, A",
|
||||
"SET 1, B", "SET 1, C", "SET 1, D", "SET 1, E", "SET 1, H", "SET 1, L", "SET 1, (HL)", "SET 1, A",
|
||||
"SET 2, B", "SET 2, C", "SET 2, D", "SET 2, E", "SET 2, H", "SET 2, L", "SET 2, (HL)", "SET 2, A",
|
||||
"SET 3, B", "SET 3, C", "SET 3, D", "SET 3, E", "SET 3, H", "SET 3, L", "SET 3, (HL)", "SET 3, A",
|
||||
"SET 4, B", "SET 4, C", "SET 4, D", "SET 4, E", "SET 4, H", "SET 4, L", "SET 4, (HL)", "SET 4, A",
|
||||
"SET 5, B", "SET 5, C", "SET 5, D", "SET 5, E", "SET 5, H", "SET 5, L", "SET 5, (HL)", "SET 5, A",
|
||||
"SET 6, B", "SET 6, C", "SET 6, D", "SET 6, E", "SET 6, H", "SET 6, L", "SET 6, (HL)", "SET 6, A",
|
||||
"SET 7, B", "SET 7, C", "SET 7, D", "SET 7, E", "SET 7, H", "SET 7, L", "SET 7, (HL)", "SET 7, A",
|
||||
};
|
||||
|
||||
readonly static string[] mnemonicsED = new string[]
|
||||
{
|
||||
"NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP",
|
||||
"NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP",
|
||||
"NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP",
|
||||
"NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP",
|
||||
|
||||
"IN B, C", "OUT C, B", "SBC HL, BC", "LD (nn), BC", //0x44
|
||||
"NEG", "RETN", "IM $0", "LD I, A", //0x48
|
||||
"IN C, C", "OUT C, C", "ADC HL, BC", "LD BC, (nn)", //0x4C
|
||||
"NEG", "RETI", "IM $0", "LD R, A", //0x50
|
||||
"IN D, C", "OUT C, D", "SBC HL, DE", "LD (nn), DE", //0x54
|
||||
"NEG", "RETN", "IM $1", "LD A, I", //0x58
|
||||
"IN E, C", "OUT C, E", "ADC HL, DE", "LD DE, (nn)", //0x5C
|
||||
"NEG", "RETI", "IM $2", "LD A, R", //0x60
|
||||
|
||||
"IN H, C", "OUT C, H", "SBC HL, HL", "LD (nn), HL", //0x64
|
||||
"NEG", "RETN", "IM $0", "RRD", //0x68
|
||||
"IN L, C", "OUT C, L", "ADC HL, HL", "LD HL, (nn)", //0x6C
|
||||
"NEG", "RETI", "IM $0", "RLD", //0x70
|
||||
"IN 0, C", "OUT C, 0", "SBC HL, SP", "LD (nn), SP", //0x74
|
||||
"NEG", "RETN", "IM $1", "NOP", //0x78
|
||||
"IN A, C", "OUT C, A", "ADC HL, SP", "LD SP, (nn)", //0x7C
|
||||
"NEG", "RETI", "IM $2", "NOP", //0x80
|
||||
|
||||
"NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", //0x90
|
||||
"NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", //0xA0
|
||||
"LDI", "CPI", "INI", "OUTI", //0xA4
|
||||
"NOP", "NOP", "NOP", "NOP", //0xA8
|
||||
"LDD", "CPD", "IND", "OUTD", //0xAC
|
||||
"NOP", "NOP", "NOP", "NOP", //0xB0
|
||||
"LDIR", "CPIR", "INIR", "OTIR", //0xB4
|
||||
"NOP", "NOP", "NOP", "NOP", //0xB8
|
||||
"LDDR", "CPDR", "INDR", "OTDR", //0xBC
|
||||
"NOP", "NOP", "NOP", "NOP", //0xC0
|
||||
|
||||
"NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", //0xD0
|
||||
"NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", //0xE0
|
||||
"NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", //0xF0
|
||||
"NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", "NOP", //0x100
|
||||
};
|
||||
|
||||
string DisassembleInternal(Func<byte> read)
|
||||
{
|
||||
byte A = read();
|
||||
string format;
|
||||
switch (A)
|
||||
{
|
||||
case 0xCB:
|
||||
A = read();
|
||||
format = mnemonicsCB[A];
|
||||
break;
|
||||
case 0xDD:
|
||||
A = read();
|
||||
switch (A)
|
||||
{
|
||||
case 0xCB: format = mnemonicsDDCB[A]; break;
|
||||
case 0xED: format = mnemonicsED[A]; break;
|
||||
default: format = mnemonicsDD[A]; break;
|
||||
}
|
||||
break;
|
||||
case 0xED:
|
||||
A = read();
|
||||
format = mnemonicsED[A];
|
||||
break;
|
||||
case 0xFD:
|
||||
A = read();
|
||||
switch (A)
|
||||
{
|
||||
case 0xCB: format = mnemonicsFDCB[A]; break;
|
||||
case 0xED: format = mnemonicsED[A]; break;
|
||||
default: format = mnemonicsFD[A]; break;
|
||||
}
|
||||
break;
|
||||
default: format = mnemonics[A]; break;
|
||||
}
|
||||
return format;
|
||||
}
|
||||
|
||||
public string Disassemble(Func<byte> read)
|
||||
{
|
||||
return Result(DisassembleInternal(read), read);
|
||||
}
|
||||
public string DisassembleInternal2(byte[] code)
|
||||
{
|
||||
byte A = code[0];
|
||||
string format;
|
||||
switch (A)
|
||||
{
|
||||
case 0xCB:
|
||||
A = code[1];
|
||||
format = mnemonicsCB[A];
|
||||
break;
|
||||
case 0xDD:
|
||||
A = code[1];
|
||||
switch (A)
|
||||
{
|
||||
case 0xCB: format = mnemonicsDDCB[A]; break;
|
||||
case 0xED: format = mnemonicsED[A]; break;
|
||||
default: format = mnemonicsDD[A]; break;
|
||||
}
|
||||
break;
|
||||
case 0xED:
|
||||
A = code[1];
|
||||
format = mnemonicsED[A];
|
||||
break;
|
||||
case 0xFD:
|
||||
A = code[1];
|
||||
switch (A)
|
||||
{
|
||||
case 0xCB: format = mnemonicsFDCB[A]; break;
|
||||
case 0xED: format = mnemonicsED[A]; break;
|
||||
default: format = mnemonicsFD[A]; break;
|
||||
}
|
||||
break;
|
||||
default: format = mnemonics[A]; break;
|
||||
}
|
||||
return format;
|
||||
}
|
||||
static string Result2(string format, byte[] code, int offset)
|
||||
{
|
||||
//d immediately succeeds the opcode
|
||||
//n immediate succeeds the opcode and the displacement (if present)
|
||||
//nn immediately succeeds the opcode and the displacement (if present)
|
||||
if (format.IndexOf("nn") != -1)
|
||||
{
|
||||
byte B = code[offset];
|
||||
byte C = code[offset + 1];
|
||||
format = format.Replace("nn", string.Format("{0:X4}h", B + C * 256));
|
||||
}
|
||||
|
||||
if (format.IndexOf("n") != -1)
|
||||
{
|
||||
byte B = code[offset];
|
||||
format = format.Replace("n", string.Format("{0:X2}h", B));
|
||||
}
|
||||
|
||||
if (format.IndexOf("+d") != -1) format = format.Replace("+d", "d");
|
||||
|
||||
if (format.IndexOf("d") != -1)
|
||||
{
|
||||
byte B = code[offset];
|
||||
bool neg = ((B & 0x80) != 0);
|
||||
char sign = neg ? '-' : '+';
|
||||
int val = neg ? 256 - B : B;
|
||||
format = format.Replace("d", string.Format("{0}{1:X2}h", sign, val));
|
||||
}
|
||||
|
||||
return format;
|
||||
}
|
||||
public string Disassemble2(byte[] code, int offset)
|
||||
{
|
||||
return Result2(DisassembleInternal2(code), code, offset);
|
||||
}
|
||||
public string GetDisassembleInfo(ushort ushort1)
|
||||
{
|
||||
byte[] opcode = null, opcode2 = null;
|
||||
byte byte1, byte2, byte3;
|
||||
string s1 = "", s2;
|
||||
int i, length = 0, offset = 0;
|
||||
string sDisassemble;
|
||||
byte1 = Z80A.zz1[0].ReadOp(ushort1);
|
||||
if (byte1 != 0xCB && byte1 != 0xED && byte1 != 0xDD && byte1 != 0xFD)
|
||||
{
|
||||
opcode2 = new byte[] { byte1, Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 1)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 2)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 3)) };
|
||||
length = Disassembler.opcodeSizes[0, byte1];
|
||||
offset = 1;
|
||||
}
|
||||
else if (byte1 == 0xCB)
|
||||
{
|
||||
opcode2 = new byte[] { byte1, Z80A.zz1[0].ReadOp((ushort)(ushort1 + 1)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 2)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 3)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 4)) };
|
||||
length = Disassembler.opcodeSizes[1, byte1];
|
||||
offset = 2;
|
||||
}
|
||||
else if (byte1 == 0xED)
|
||||
{
|
||||
opcode2 = new byte[] { byte1, Z80A.zz1[0].ReadOp((ushort)(ushort1 + 1)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 2)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 3)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 4)) };
|
||||
length = Disassembler.opcodeSizes[2, byte1];
|
||||
offset = 2;
|
||||
}
|
||||
else if (byte1 == 0xDD)
|
||||
{
|
||||
byte2 = Z80A.zz1[0].ReadOp((ushort)(ushort1 + 1));
|
||||
if (byte2 != 0xCB && byte2 != 0xED)
|
||||
{
|
||||
opcode2 = new byte[] { byte1, byte2, Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 2)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 3)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 4)) };
|
||||
length = Disassembler.opcodeSizes[3, byte2];
|
||||
offset = 2;
|
||||
}
|
||||
else if (byte2 == 0xCB)
|
||||
{
|
||||
byte3 = Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 2));
|
||||
opcode2 = new byte[] { byte1, byte2, byte3, Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 3)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 4)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 5)) };
|
||||
length = Disassembler.opcodeSizes[5, byte3];
|
||||
offset = 2;
|
||||
}
|
||||
else if (byte2 == 0xED)
|
||||
{
|
||||
byte3 = Z80A.zz1[0].ReadOp((ushort)(ushort1 + 2));
|
||||
opcode2 = new byte[] { byte1, byte2, byte3, Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 3)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 4)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 5)) };
|
||||
length = Disassembler.opcodeSizes[7, byte3];
|
||||
offset = 2;
|
||||
}
|
||||
}
|
||||
else if (byte1 == 0xFD)
|
||||
{
|
||||
byte2 = Z80A.zz1[0].ReadOp((ushort)(ushort1 + 1));
|
||||
if (byte2 != 0xCB && byte2 != 0xED)
|
||||
{
|
||||
opcode2 = new byte[] { byte1, byte2, Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 2)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 3)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 4)) };
|
||||
length = Disassembler.opcodeSizes[4, byte2];
|
||||
offset = 2;
|
||||
}
|
||||
else if (byte2 == 0xCB)
|
||||
{
|
||||
byte3 = Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 2));
|
||||
opcode2 = new byte[] { byte1, byte2, byte3, Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 3)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 4)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 5)) };
|
||||
length = Disassembler.opcodeSizes[6, byte3];
|
||||
offset = 2;
|
||||
}
|
||||
else if (byte2 == 0xED)
|
||||
{
|
||||
byte3 = Z80A.zz1[0].ReadOp((ushort)(ushort1 + 2));
|
||||
opcode2 = new byte[] { byte1, byte2, byte3, Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 3)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 4)), Z80A.zz1[0].ReadOpArg((ushort)(ushort1 + 5)) };
|
||||
length = Disassembler.opcodeSizes[8, byte3];
|
||||
offset = 2;
|
||||
}
|
||||
}
|
||||
opcode = new byte[length];
|
||||
Array.Copy(opcode2, opcode, length);
|
||||
s2 = Disassemble2(opcode, offset);
|
||||
for (i = 0; i < length; i++)
|
||||
{
|
||||
s1 += opcode[i].ToString("X2") + " ";
|
||||
}
|
||||
sDisassemble = s1.PadRight(20, ' ') + s2;
|
||||
return sDisassemble;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,11 +0,0 @@
|
||||
fileFormatVersion: 2
|
||||
guid: 5068ca330bee2044293e8006ad23fc35
|
||||
MonoImporter:
|
||||
externalObjects: {}
|
||||
serializedVersion: 2
|
||||
defaultReferences: []
|
||||
executionOrder: 0
|
||||
icon: {instanceID: 0}
|
||||
userData:
|
||||
assetBundleName:
|
||||
assetBundleVariant:
|
||||
@ -87,7 +87,6 @@
|
||||
PPC = RegPC.Word;
|
||||
OP = ReadOp(PPC);
|
||||
RegPC.Word++;
|
||||
//debugger_start_cpu_hook_callback();
|
||||
switch (OP)//ReadMemory(RegPC.Word++))
|
||||
{
|
||||
case 0x00: // NOP
|
||||
@ -11699,7 +11698,6 @@
|
||||
totalExecutedCycles += 11; pendingCycles -= 11;
|
||||
break;
|
||||
}
|
||||
//debugger_stop_cpu_hook_callback();
|
||||
}
|
||||
}
|
||||
while (pendingCycles > 0);
|
||||
|
||||
@ -119,8 +119,6 @@ namespace cpu.z80
|
||||
public Func<ushort, byte> ReadMemory;
|
||||
public Action<ushort, byte> WriteMemory;
|
||||
|
||||
public delegate void debug_delegate();
|
||||
//public debug_delegate debugger_start_cpu_hook_callback, debugger_stop_cpu_hook_callback;
|
||||
|
||||
public void UnregisterMemoryMapper()
|
||||
{
|
||||
|
||||
@ -2117,46 +2117,17 @@ namespace MAME.Core
|
||||
case "Neo Geo":
|
||||
case "PGM":
|
||||
case "Taito B":
|
||||
M68000Motion.m68000State = M68000Motion.M68000State.M68000_RUN;
|
||||
//MC68000.m1.debugger_start_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_start_debug;
|
||||
//MC68000.m1.debugger_stop_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_stop_debug;
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
//Z80A.zz1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
break;
|
||||
case "Tehkan":
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
//Z80A.zz1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
//Z80A.zz1[1].debugger_start_cpu_hook_callback = null_callback;
|
||||
//Z80A.zz1[1].debugger_stop_cpu_hook_callback = null_callback;
|
||||
break;
|
||||
case "IGS011":
|
||||
M68000Motion.m68000State = M68000Motion.M68000State.M68000_RUN;
|
||||
//MC68000.m1.debugger_start_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_start_debug;
|
||||
//MC68000.m1.debugger_stop_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_stop_debug;
|
||||
break;
|
||||
case "SunA8":
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
//Z80A.zz1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
//Z80A.zz1[1].debugger_start_cpu_hook_callback = null_callback;
|
||||
//Z80A.zz1[1].debugger_stop_cpu_hook_callback = null_callback;
|
||||
break;
|
||||
case "Namco System 1":
|
||||
M6809Motion.m6809State = CPUState.RUN;
|
||||
M6809.mm1[0].DisassemblerInit();
|
||||
//M6809.mm1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.m6809motion.m6809_start_debug;
|
||||
//M6809.mm1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.m6809motion.m6809_stop_debug;
|
||||
//M6809.mm1[1].debugger_start_cpu_hook_callback = null_callback;
|
||||
//M6809.mm1[1].debugger_stop_cpu_hook_callback = null_callback;
|
||||
//M6809.mm1[2].debugger_start_cpu_hook_callback = null_callback;
|
||||
//M6809.mm1[2].debugger_stop_cpu_hook_callback = null_callback;
|
||||
//M6809.mm1[0].DisassemblerInit();
|
||||
break;
|
||||
case "M72":
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
//Z80A.zz1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
break;
|
||||
case "M92":
|
||||
break;
|
||||
@ -2185,35 +2156,14 @@ namespace MAME.Core
|
||||
case "boblcave":
|
||||
case "bublcave11":
|
||||
case "bublcave10":
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
//Z80A.zz1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
//Z80A.zz1[1].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[1].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
//Z80A.zz1[2].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[2].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
break;
|
||||
case "opwolf":
|
||||
case "opwolfa":
|
||||
case "opwolfj":
|
||||
case "opwolfu":
|
||||
case "opwolfp":
|
||||
M68000Motion.m68000State = M68000Motion.M68000State.M68000_RUN;
|
||||
//MC68000.m1.debugger_start_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_start_debug;
|
||||
//MC68000.m1.debugger_stop_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_stop_debug;
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
//Z80A.zz1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
break;
|
||||
case "opwolfb":
|
||||
M68000Motion.m68000State = M68000Motion.M68000State.M68000_RUN;
|
||||
//MC68000.m1.debugger_start_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_start_debug;
|
||||
//MC68000.m1.debugger_stop_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_stop_debug;
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
//Z80A.zz1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
//Z80A.zz1[1].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[1].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -2221,17 +2171,7 @@ namespace MAME.Core
|
||||
switch (Machine.sName)
|
||||
{
|
||||
case "cuebrick":
|
||||
M68000Motion.m68000State = M68000Motion.M68000State.M68000_RUN;
|
||||
//MC68000.m1.debugger_start_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_start_debug;
|
||||
//MC68000.m1.debugger_stop_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_stop_debug;
|
||||
break;
|
||||
default:
|
||||
M68000Motion.m68000State = M68000Motion.M68000State.M68000_RUN;
|
||||
//MC68000.m1.debugger_start_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_start_debug;
|
||||
//MC68000.m1.debugger_stop_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_stop_debug;
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
//Z80A.zz1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -2249,13 +2189,6 @@ namespace MAME.Core
|
||||
case "makaimurc":
|
||||
case "makaimurg":
|
||||
case "diamond":
|
||||
M6809Motion.m6809State = CPUState.RUN;
|
||||
M6809.mm1[0].DisassemblerInit();
|
||||
//M6809.mm1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.m6809motion.m6809_start_debug;
|
||||
//M6809.mm1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.m6809motion.m6809_stop_debug;
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
//Z80A.zz1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
break;
|
||||
case "sf":
|
||||
case "sfua":
|
||||
@ -2263,14 +2196,6 @@ namespace MAME.Core
|
||||
case "sfjan":
|
||||
case "sfan":
|
||||
case "sfp":
|
||||
M68000Motion.m68000State = M68000Motion.M68000State.M68000_RUN;
|
||||
//MC68000.m1.debugger_start_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_start_debug;
|
||||
//MC68000.m1.debugger_stop_cpu_hook_callback = Machine.mainMotion.m68000motion.m68000_stop_debug;
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
//Z80A.zz1[0].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[0].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
//Z80A.zz1[1].debugger_start_cpu_hook_callback = Machine.mainMotion.z80motion.z80_start_debug;
|
||||
//Z80A.zz1[1].debugger_stop_cpu_hook_callback = Machine.mainMotion.z80motion.z80_stop_debug;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
@ -2471,10 +2396,10 @@ namespace MAME.Core
|
||||
cpu[icpu].eatcycles = cpu[icpu].nexteatcycles;
|
||||
}
|
||||
EmuTimer.timer_set_global_time(target);
|
||||
if (EmuTimer.global_basetime.attoseconds == 0 && Machine.mainMotion.cheatmotion.lockState == CheatMotion.LockState.LOCK_SECOND)
|
||||
{
|
||||
Machine.mainMotion.cheatmotion.ApplyCheat();
|
||||
}
|
||||
//if (EmuTimer.global_basetime.attoseconds == 0 && Machine.mainMotion.cheatmotion.lockState == CheatMotion.LockState.LOCK_SECOND)
|
||||
//{
|
||||
// Machine.mainMotion.cheatmotion.ApplyCheat();
|
||||
//}
|
||||
}
|
||||
public static void cpu_boost_interleave(Atime timeslice_time, Atime boost_duration)
|
||||
{
|
||||
|
||||
@ -283,8 +283,6 @@ namespace MAME.Core
|
||||
}
|
||||
public static byte[] GetRom(string sFile)
|
||||
{
|
||||
byte[] bb1 = null;
|
||||
int n1;
|
||||
foreach (string s1 in lsParents)
|
||||
{
|
||||
string path = System.IO.Path.Combine(Mame.RomRoot + "/" + s1 + "/", sFile);
|
||||
@ -292,19 +290,13 @@ namespace MAME.Core
|
||||
{
|
||||
EmuLogger.Log($"Had File => {path}");
|
||||
return File.ReadAllBytes(path);
|
||||
//FileStream fs1 = new FileStream(path, FileMode.Open);
|
||||
//n1 = (int)fs1.Length;
|
||||
//bb1 = new byte[n1];
|
||||
//fs1.Read(bb1, 0, n1);
|
||||
//fs1.Close();
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
EmuLogger.Log($"Miss File => {path}");
|
||||
}
|
||||
}
|
||||
return bb1;
|
||||
return null;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,8 +1,4 @@
|
||||
using MAME.Core;
|
||||
using System;
|
||||
using System.Reflection;
|
||||
using System.Runtime.InteropServices;
|
||||
using UnityEngine.UIElements;
|
||||
using System;
|
||||
|
||||
namespace MAME.Core
|
||||
{
|
||||
@ -158,29 +154,29 @@ namespace MAME.Core
|
||||
else
|
||||
{
|
||||
|
||||
for (y = startY; y < endY; y++)
|
||||
{
|
||||
int stepIndex = y * Video.fullwidth;
|
||||
for (x = startX; x < endX; x++, target_i++)
|
||||
{
|
||||
i = stepIndex + x;
|
||||
bitmapcolorRect[target_i] = (int)entry_color[curbitmap[i]];
|
||||
}
|
||||
}
|
||||
|
||||
//for (y = startY; y < endY; y++)
|
||||
//{
|
||||
// int stepIndex = y * Video.fullwidth;
|
||||
|
||||
// for (x = startX; x < endX; x++, target_i++)
|
||||
// {
|
||||
// i = stepIndex + x;
|
||||
// bitmapcolorRect[target_i] = (int)entry_color[curbitmap[i]];
|
||||
// }
|
||||
|
||||
// // 使用Marshal.Copy进行内存拷贝
|
||||
// Marshal.Copy(Palette.entry_color_Ptr,, Video.bitmapcolorRect_Ptr, endX - startX);
|
||||
//}
|
||||
|
||||
for (y = startY; y < endY; y++)
|
||||
{
|
||||
int stepIndex = y * Video.fullwidth;
|
||||
//for (x = startX; x < endX; x++, target_i++)
|
||||
//{
|
||||
// i = stepIndex + x;
|
||||
// //bitmapcolorRect[target_i] = (int)entry_color[curbitmap[i]];
|
||||
//}
|
||||
int stepStartIdx = stepIndex + startX;
|
||||
int linelenght = endX - startX;
|
||||
Array.Copy(Palette.entry_color, stepStartIdx, Video.bitmapcolorRect, 0, linelenght);
|
||||
target_i += linelenght;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -627,10 +623,6 @@ namespace MAME.Core
|
||||
}
|
||||
public static void cpurun()
|
||||
{
|
||||
M68000Motion.m68000State = M68000Motion.M68000State.M68000_RUN;
|
||||
Machine.mainMotion.m68000motion.mTx_tsslStatus = "run";
|
||||
Z80Motion.z80State = Z80Motion.Z80AState.Z80A_RUN;
|
||||
Machine.mainMotion.z80motion.mTx_tsslStatus = "run";
|
||||
}
|
||||
private static double ui_get_line_height()
|
||||
{
|
||||
|
||||
@ -1,7 +1,5 @@
|
||||
using MAME.Core.AxiBitmap;
|
||||
using System;
|
||||
using System.Runtime.InteropServices;
|
||||
using System;
|
||||
using Color = MAME.Core.AxiBitmap.AxiColor;
|
||||
|
||||
namespace MAME.Core
|
||||
{
|
||||
@ -16,7 +14,7 @@ namespace MAME.Core
|
||||
public static float[] entry_contrast;
|
||||
private static uint trans_uint;
|
||||
private static int numcolors, numgroups;
|
||||
public static Color trans_color;
|
||||
//public static Color trans_color;
|
||||
public delegate void palette_delegate(int index, uint rgb);
|
||||
public static palette_delegate palette_set_callback;
|
||||
public static void palette_init()
|
||||
@ -28,59 +26,59 @@ namespace MAME.Core
|
||||
case "CPS-1(QSound)":
|
||||
case "CPS2":
|
||||
//trans_color = Color.Magenta;
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0xc00;
|
||||
palette_set_callback = palette_entry_set_color1;
|
||||
break;
|
||||
case "Data East":
|
||||
//trans_color = Color.Magenta;
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x200;
|
||||
palette_set_callback = palette_entry_set_color2;
|
||||
break;
|
||||
case "Tehkan":
|
||||
//trans_color = Color.Magenta;
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x100;
|
||||
palette_set_callback = palette_entry_set_color2;
|
||||
break;
|
||||
case "SunA8":
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x100;
|
||||
palette_set_callback = palette_entry_set_color2;
|
||||
break;
|
||||
case "Namco System 1":
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x2001;
|
||||
palette_set_callback = palette_entry_set_color1;
|
||||
break;
|
||||
case "IGS011":
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x800;
|
||||
palette_set_callback = palette_entry_set_color1;
|
||||
break;
|
||||
case "PGM":
|
||||
//trans_color = Color.Magenta;
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x901;
|
||||
palette_set_callback = palette_entry_set_color2;
|
||||
break;
|
||||
case "M72":
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x201;
|
||||
palette_set_callback = palette_entry_set_color1;
|
||||
break;
|
||||
case "M92":
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x801;
|
||||
palette_set_callback = palette_entry_set_color2;
|
||||
break;
|
||||
@ -110,7 +108,7 @@ namespace MAME.Core
|
||||
case "bublcave11":
|
||||
case "bublcave10":
|
||||
//trans_color = Color.Magenta;
|
||||
trans_color = Color.Black;
|
||||
//trans_color = Color.Black;
|
||||
numcolors = 0x100;
|
||||
break;
|
||||
case "opwolf":
|
||||
@ -119,23 +117,23 @@ namespace MAME.Core
|
||||
case "opwolfu":
|
||||
case "opwolfb":
|
||||
case "opwolfp":
|
||||
trans_color = Color.Black;
|
||||
//trans_color = Color.Black;
|
||||
numcolors = 0x2000;
|
||||
break;
|
||||
}
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
palette_set_callback = palette_entry_set_color2;
|
||||
break;
|
||||
case "Taito B":
|
||||
//trans_color = Color.Magenta;
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x1000;
|
||||
palette_set_callback = palette_entry_set_color3;
|
||||
break;
|
||||
case "Konami 68000":
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x800;
|
||||
palette_set_callback = palette_entry_set_color3;
|
||||
break;
|
||||
@ -153,8 +151,8 @@ namespace MAME.Core
|
||||
case "makaimurc":
|
||||
case "makaimurg":
|
||||
case "diamond":
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x100;
|
||||
palette_set_callback = palette_entry_set_color2;
|
||||
break;
|
||||
@ -164,8 +162,8 @@ namespace MAME.Core
|
||||
case "sfjan":
|
||||
case "sfan":
|
||||
case "sfp":
|
||||
trans_color = Color.Black;
|
||||
trans_uint = (uint)trans_color.ToArgb();
|
||||
//trans_color = Color.Black;
|
||||
trans_uint = 0x0;//(uint)trans_color.ToArgb();
|
||||
numcolors = 0x400;
|
||||
palette_set_callback = palette_entry_set_color3;
|
||||
break;
|
||||
|
||||
@ -24,15 +24,6 @@ namespace MAME.Core
|
||||
if (!dictName2Rom.TryGetValue(s1, out RomInfo info))
|
||||
return null;
|
||||
return info;
|
||||
|
||||
//foreach (RomInfo ri in romList)
|
||||
//{
|
||||
// if (s1 == ri.Name)
|
||||
// {
|
||||
// return ri;
|
||||
// }
|
||||
//}
|
||||
//return null;
|
||||
}
|
||||
public static string GetParent(string s1)
|
||||
{
|
||||
|
||||
@ -29,9 +29,7 @@ namespace MAME.Core
|
||||
private static int PAUSED_REFRESH_RATE = 30, VIDEO_UPDATE_AFTER_VBLANK = 4;
|
||||
public static EmuTimer.emu_timer vblank_begin_timer, vblank_end_timer;
|
||||
public static EmuTimer.emu_timer scanline0_timer, scanline_timer;
|
||||
private static Atime throttle_emutime, throttle_realtime, speed_last_emutime, overall_emutime;
|
||||
private static long throttle_last_ticks;
|
||||
private static long average_oversleep;
|
||||
private static Atime speed_last_emutime, overall_emutime;
|
||||
private static long speed_last_realtime, overall_real_ticks;
|
||||
private static double speed_percent;
|
||||
private static uint throttle_history, overall_valid_counter, overall_real_seconds;
|
||||
@ -956,10 +954,10 @@ namespace MAME.Core
|
||||
Mouse.Update();
|
||||
Inptport.frame_update_callback();
|
||||
Motion.ui_update_and_render();
|
||||
if (Machine.mainMotion.cheatmotion.lockState == CheatMotion.LockState.LOCK_FRAME)
|
||||
{
|
||||
Machine.mainMotion.cheatmotion.ApplyCheat();
|
||||
}
|
||||
//if (Machine.mainMotion.cheatmotion.lockState == CheatMotion.LockState.LOCK_FRAME)
|
||||
//{
|
||||
// Machine.mainMotion.cheatmotion.ApplyCheat();
|
||||
//}
|
||||
GDIDraw();
|
||||
|
||||
if (effective_throttle())
|
||||
|
||||
@ -1,6 +1,4 @@
|
||||
using MAME.Core.AxiBitmap;
|
||||
using System;
|
||||
using Color = MAME.Core.AxiBitmap.AxiColor;
|
||||
using System;
|
||||
|
||||
namespace MAME.Core
|
||||
{
|
||||
@ -55,30 +53,30 @@ namespace MAME.Core
|
||||
}*/
|
||||
|
||||
|
||||
/// <summary>
|
||||
///
|
||||
/// </summary>
|
||||
/// <param name="bitmap"></param>
|
||||
/// <param name="factor"></param>
|
||||
/// <returns></returns>
|
||||
public static int[] MultiplyAlpha(int[] bitmap, float factor)
|
||||
{
|
||||
int[] result = (int[])bitmap.Clone();
|
||||
for (int i = 0; i < result.Length; i++)
|
||||
{
|
||||
Color originalColor = AxiColor.FromArgb(result[i]);
|
||||
byte newAlpha = (byte)Math.Min(255, (int)(originalColor.a * factor));
|
||||
Color newColor = new Color
|
||||
{
|
||||
r = originalColor.r,
|
||||
g = originalColor.g,
|
||||
b = originalColor.b,
|
||||
a = newAlpha
|
||||
};
|
||||
result[i] = AxiColor.ToArgb(newColor);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
///// <summary>
|
||||
/////
|
||||
///// </summary>
|
||||
///// <param name="bitmap"></param>
|
||||
///// <param name="factor"></param>
|
||||
///// <returns></returns>
|
||||
//public static int[] MultiplyAlpha(int[] bitmap, float factor)
|
||||
//{
|
||||
// int[] result = (int[])bitmap.Clone();
|
||||
// for (int i = 0; i < result.Length; i++)
|
||||
// {
|
||||
// Color originalColor = AxiColor.FromArgb(result[i]);
|
||||
// byte newAlpha = (byte)Math.Min(255, (int)(originalColor.a * factor));
|
||||
// Color newColor = new Color
|
||||
// {
|
||||
// r = originalColor.r,
|
||||
// g = originalColor.g,
|
||||
// b = originalColor.b,
|
||||
// a = newAlpha
|
||||
// };
|
||||
// result[i] = AxiColor.ToArgb(newColor);
|
||||
// }
|
||||
// return result;
|
||||
//}
|
||||
|
||||
//public static void GDIDraw()
|
||||
//{
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
{
|
||||
public class Window
|
||||
{
|
||||
private static MameMainMotion _myParentForm;
|
||||
//private static MameMainMotion _myParentForm;
|
||||
//[DllImport("kernel32.dll ")]
|
||||
//private static extern uint GetTickCount();
|
||||
|
||||
|
||||
@ -400,6 +400,7 @@ namespace MAME.Core
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
public static void ZCWriteMemory(ushort address, byte value)
|
||||
{
|
||||
if (address >= 0xd000 && address <= 0xd7ff)
|
||||
|
||||
@ -419,8 +419,6 @@ namespace MAME.Core
|
||||
public static void MWriteByte(int address, sbyte value)
|
||||
{
|
||||
address &= 0xffffff;
|
||||
M68000Motion.iWAddress = address;
|
||||
M68000Motion.iWOp = 0x01;
|
||||
if (address >= 0x100000 && address <= 0x1fffff)
|
||||
{
|
||||
if (address == 0x100d0b && value == 0x06)//&&MC68000.m1.TotalExecutedCycles>0x3F6FC8C)
|
||||
@ -496,8 +494,6 @@ namespace MAME.Core
|
||||
public static void MWriteWord(int address, short value)
|
||||
{
|
||||
address &= 0xffffff;
|
||||
M68000Motion.iWAddress = address;
|
||||
M68000Motion.iWOp = 0x02;
|
||||
if (address >= 0x100000 && address + 1 <= 0x1fffff)
|
||||
{
|
||||
if (address == 0x1007c4 && value == unchecked((short)0xb102))
|
||||
@ -549,8 +545,6 @@ namespace MAME.Core
|
||||
public static void MWriteLong(int address, int value)
|
||||
{
|
||||
address &= 0xffffff;
|
||||
M68000Motion.iWAddress = address;
|
||||
M68000Motion.iWOp = 0x03;
|
||||
if (address >= 0x100000 && address + 3 <= 0x1fffff)
|
||||
{
|
||||
if (address == 0x1051e4 && value == 0x00130070)
|
||||
|
||||
@ -56,7 +56,7 @@ namespace MAME.Core
|
||||
UNKNOW_T = 1<< 31,
|
||||
UNKNOW_M = 1<< 31,
|
||||
UNKNOW_V = 1<< 31,
|
||||
UNKNOW_B = 1<< 12
|
||||
UNKNOW_B = 1<< 31
|
||||
|
||||
//EMU_PAUSED = (1 << 36),
|
||||
//F10 = (1 << 37),
|
||||
|
||||
@ -1739,70 +1739,6 @@ namespace MAME.Core
|
||||
{
|
||||
////只需要这部分逻辑
|
||||
SubmitSamples(buffer, samples_this_frame);
|
||||
return;
|
||||
|
||||
//TODO后面才考虑原样的处理
|
||||
|
||||
int play_position, write_position;
|
||||
int stream_in;
|
||||
byte[] buffer1, buffer2;
|
||||
int length1, length2;
|
||||
//buf2.GetCurrentPosition(out play_position, out write_position);
|
||||
GetCurrentPosition(out play_position, out write_position);
|
||||
if (write_position < play_position)
|
||||
{
|
||||
write_position += 0x9400;
|
||||
}
|
||||
stream_in = stream_buffer_in;
|
||||
if (stream_in < write_position)
|
||||
{
|
||||
stream_in += 0x9400;
|
||||
}
|
||||
while (stream_in < write_position)
|
||||
{
|
||||
//buffer_underflows++;
|
||||
stream_in += 0xf00;
|
||||
}
|
||||
if (stream_in + 0xf00 > play_position + 0x9400)
|
||||
{
|
||||
//buffer_overflows++;
|
||||
return;
|
||||
}
|
||||
stream_buffer_in = stream_in % 0x9400;
|
||||
if (stream_buffer_in + 0xf00 < 0x9400)
|
||||
{
|
||||
length1 = 0xf00;
|
||||
length2 = 0;
|
||||
buffer1 = new byte[length1];
|
||||
Array.Copy(buffer, buffer1, length1);
|
||||
//buf2.Write(stream_buffer_in, buffer1, LockFlag.None);
|
||||
BufferWirte(stream_buffer_in, buffer1);
|
||||
stream_buffer_in = stream_buffer_in + 0xf00;
|
||||
}
|
||||
else if (stream_buffer_in + 0xf00 == 0x9400)
|
||||
{
|
||||
length1 = 0xf00;
|
||||
length2 = 0;
|
||||
buffer1 = new byte[length1];
|
||||
Array.Copy(buffer, buffer1, length1);
|
||||
//buf2.Write(stream_buffer_in, buffer1, LockFlag.None);
|
||||
BufferWirte(stream_buffer_in, buffer1);
|
||||
stream_buffer_in = 0;
|
||||
}
|
||||
else if (stream_buffer_in + 0xf00 > 0x9400)
|
||||
{
|
||||
length1 = 0x9400 - stream_buffer_in;
|
||||
length2 = 0xf00 - length1;
|
||||
buffer1 = new byte[length1];
|
||||
buffer2 = new byte[length2];
|
||||
Array.Copy(buffer, buffer1, length1);
|
||||
Array.Copy(buffer, length1, buffer2, 0, length2);
|
||||
//buf2.Write(stream_buffer_in, buffer1, LockFlag.None);
|
||||
BufferWirte(stream_buffer_in, buffer1);
|
||||
//buf2.Write(0, buffer2, LockFlag.None);
|
||||
BufferWirte(0, buffer2);
|
||||
stream_buffer_in = length2;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1779,6 +1779,9 @@ namespace MAME.Core
|
||||
// }
|
||||
// }
|
||||
//}
|
||||
|
||||
static bool skiprun_update_one;
|
||||
static int run_update_one_Index;
|
||||
public unsafe static void ym2151_update_one(int offset, int length)
|
||||
{
|
||||
fixed (uint* PSGpanPtr = &PSG.pan[0])
|
||||
@ -1812,6 +1815,48 @@ namespace MAME.Core
|
||||
chanout[5] = 0;
|
||||
chanout[6] = 0;
|
||||
chanout[7] = 0;
|
||||
|
||||
//二分交替混音
|
||||
//skiprun_update_one = !skiprun_update_one;
|
||||
//if (!skiprun_update_one)
|
||||
//{
|
||||
// chan_calc(PSGoper, chanout, imem, 0);
|
||||
// chan_calc(PSGoper, chanout, imem, 2);
|
||||
// chan_calc(PSGoper, chanout, imem, 4);
|
||||
// chan_calc(PSGoper, chanout, imem, 6);
|
||||
//}
|
||||
//else
|
||||
//{
|
||||
// chan_calc(PSGoper, chanout, imem, 1);
|
||||
// chan_calc(PSGoper, chanout, imem, 3);
|
||||
// chan_calc(PSGoper, chanout, imem, 5);
|
||||
// chan7_calc(PSGoper, chanout, imem);
|
||||
//}
|
||||
|
||||
//三分交替混音
|
||||
//run_update_one_Index++;
|
||||
//if (run_update_one_Index > 2)
|
||||
// run_update_one_Index = 0;
|
||||
//switch (run_update_one_Index)
|
||||
//{
|
||||
// case 0:
|
||||
// chan_calc(PSGoper, chanout, imem, 0);
|
||||
// chan_calc(PSGoper, chanout, imem, 2);
|
||||
// chan_calc(PSGoper, chanout, imem, 4);
|
||||
// break;
|
||||
// case 1:
|
||||
// chan_calc(PSGoper, chanout, imem, 1);
|
||||
// chan_calc(PSGoper, chanout, imem, 3);
|
||||
// chan7_calc(PSGoper, chanout, imem);
|
||||
// break;
|
||||
// case 2:
|
||||
// chan_calc(PSGoper, chanout, imem, 0);
|
||||
// chan_calc(PSGoper, chanout, imem, 5);
|
||||
// chan_calc(PSGoper, chanout, imem, 6);
|
||||
// break;
|
||||
//}
|
||||
|
||||
//完全渲染混音
|
||||
chan_calc(PSGoper, chanout, imem, 0);
|
||||
chan_calc(PSGoper, chanout, imem, 1);
|
||||
chan_calc(PSGoper, chanout, imem, 2);
|
||||
@ -1820,6 +1865,7 @@ namespace MAME.Core
|
||||
chan_calc(PSGoper, chanout, imem, 5);
|
||||
chan_calc(PSGoper, chanout, imem, 6);
|
||||
chan7_calc(PSGoper, chanout, imem);
|
||||
|
||||
outl = (int)(chanout[0] & PSGpan[0]);
|
||||
outr = (int)(chanout[0] & PSGpan[1]);
|
||||
outl += (int)(chanout[1] & PSGpan[2]);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user