447 lines
9.7 KiB
C++
447 lines
9.7 KiB
C++
//////////////////////////////////////////////////////////////////////////
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// Mapper074 Nintendo MMC3 //
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//////////////////////////////////////////////////////////////////////////
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void Mapper074::Reset()
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{
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DWORD crc = nes->rom->GetPROM_CRC();
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if(crc == 0x227f8f9f) Decode_PROM(); //Ji Jia Zhan Shi (Ch) [new pcb dump]
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nes->ppu->SetVromWrite(1);
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for( INT j = 0; j < 8; j++ ) reg[j] = 0x00;
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prg0 = 0;
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prg1 = 1;
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prg2 = PROM_8K_SIZE-2;
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prg3 = PROM_8K_SIZE-1;
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SetBank_CPU();
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chr01 = 0;
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chr1 = 1;
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chr23 = 2;
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chr3 = 3;
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chr4 = 4;
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chr5 = 5;
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chr6 = 6;
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chr7 = 7;
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SetBank_PPU();
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irq_enable = 0;
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irq_counter = 0;
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irq_latch = 0;
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irq_request = 0;
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reg5000 = 0;
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reg5001 = 0;
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reg5002 = 0;
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reg5003 = 0;
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reg5010 = 0;
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reg5011 = 0;
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reg5012 = 0;
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reg5013 = 0;
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reg5FF3 = 0;
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JMaddr = 0;
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JMaddrDAT[0] = JMaddrDAT[1] = JMaddrDAT[2] = 0;
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we_sram = 0;
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nes->SetSAVERAM_SIZE( 32*1024 );
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sp_rom = 0;
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if(crc == 0x84966C88){ //[KT-1005] Feng Shen Bang (C)
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nes->SetSAVERAM_SIZE( 8*1024 );
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sp_rom = 1;
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}
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if(crc == 0x830BCF70){ //[KT-1015] Chu Liu Xiang Xin Zhuan (C)
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nes->SetSAVERAM_SIZE( 8*1024 );
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sp_rom = 2;
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bank = 0;
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prg2 = (PROM_8K_SIZE>>1)-2;
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prg3 = (PROM_8K_SIZE>>1)-1;
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SetBank_CPU();
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}
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}
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BYTE Mapper074::ReadLow( WORD addr )
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{
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DEBUGOUT("ReadLow : Address=%04X\n", addr&0xFFFF );
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if( addr >= 0x5000 && addr <= 0x5FFF ){
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return XRAM[addr-0x4000];
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}else if( addr >= 0x6000 && addr <= 0x7FFF ){
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if(JMaddr){
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switch( addr ) {
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case 0x6000: return JMaddrDAT[0];
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case 0x6010: return JMaddrDAT[1];
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case 0x6013: JMaddr=0; return JMaddrDAT[2];
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}
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}
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switch( we_sram ) {
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case 0xE4:
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case 0xEC: return WRAM[(addr&0x1FFF)+0x0000];
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case 0xE5:
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case 0xED: return WRAM[(addr&0x1FFF)+0x2000];
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case 0xE6:
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case 0xEE: return WRAM[(addr&0x1FFF)+0x4000];
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case 0xE7:
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case 0xEF: return WRAM[(addr&0x1FFF)+0x6000];
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default: return CPU_MEM_BANK[addr>>13][addr&0x1FFF];
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}
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}else{
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return Mapper::ReadLow( addr );
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}
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}
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void Mapper074::WriteLow( WORD addr, BYTE data )
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{
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DEBUGOUT("WriteLow : Address=%04X Data=%02X\n", addr&0xFFFF, data&0xFF );
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/*
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if ((addr&0x4100)==0x4100) { //<2F>й<EFBFBD><D0B9><EFBFBD><EFBFBD><EFBFBD>[Sachen]
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if(data&2){
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SetCRAM_8K_Bank(0);
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}else
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SetVROM_1K_Bank(addr>>10,data);
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// data &= 0x03;
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// if ( data == 0 ) SetCRAM_8K_Bank( 2 );
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// else if ( data == 1 ) SetCRAM_8K_Bank( 3 );
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// else if ( data == 2 ) SetCRAM_8K_Bank( 0 );
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// else SetCRAM_8K_Bank( 1 );
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}
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*/
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if( addr >= 0x5000 && addr <= 0x5FFF ) {
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XRAM[addr-0x4000] = data;
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switch( addr ) {
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case 0x5000:
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reg5000 = data;
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if (sp_rom==2){ //[KT-1015] Chu Liu Xiang Xin Zhuan (C)
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bank = ((reg5000<<4)|(reg5003&0xf))>>2;
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SetPROM_32K_Bank( bank );}
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break;
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case 0x5001:
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reg5001 = data;
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break;
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case 0x5002:
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reg5002 = data;
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break;
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case 0x5003:
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reg5003 = data;
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break;
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case 0x5010:
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reg5010 = data;
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break;
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case 0x5011:
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reg5011 = data;
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break;
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case 0x5012:
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reg5012 = data;
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break;
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case 0x5013:
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reg5013 = data;
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break;
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case 0x5FF3:
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reg5FF3 = data;
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if(reg5FF3==2) SetPROM_32K_Bank(0,0,0,0);
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break;
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}
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if((we_sram==0xA5)||(we_sram==0xA9)){
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JMaddr = 1;
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switch( addr ) {
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case 0x5000: JMaddrDAT[0] = data; break;
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case 0x5010: JMaddrDAT[1] = data; break;
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case 0x5013: JMaddrDAT[2] = data; break;
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}
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}
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}else if( addr >= 0x6000 && addr <= 0x7FFF ){
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switch( we_sram ) {
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case 0xE4: //CPU_MEM_BANK
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case 0xEC: //CPU_MEM_BANK
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WRAM[(addr&0x1FFF)+0x0000] = data;
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CPU_MEM_BANK[addr>>13][addr&0x1FFF] = data;
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break;
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case 0xE5: //SRAM
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case 0xED: //SRAM
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WRAM[(addr&0x1FFF)+0x2000] = data;
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break;
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case 0xE6:
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case 0xEE:
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WRAM[(addr&0x1FFF)+0x4000] = data;
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break;
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case 0xE7:
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case 0xEF:
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WRAM[(addr&0x1FFF)+0x6000] = data;
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break;
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default:
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CPU_MEM_BANK[addr>>13][addr&0x1FFF] = data;
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break;
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}
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}else{
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Mapper::WriteLow( addr, data );
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}
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}
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void Mapper074::Write( WORD addr, BYTE data )
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{
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// DEBUGOUT("Write : Address=%04X Data=%02X\n", addr&0xFFFF, data&0xFF );
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switch( addr & 0xE001 ) {
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case 0x8000:
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reg[0] = data;
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SetBank_CPU();
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SetBank_PPU();
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break;
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case 0x8001:
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reg[1] = data;
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switch( reg[0] & 0x0f ) {
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case 0x00:
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chr01 = data;
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chr1 = chr01+1;
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SetBank_PPU();
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break;
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case 0x01:
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chr23 = data;
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chr3 = chr23+1;
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SetBank_PPU();
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break;
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case 0x02:
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chr4 = data;
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SetBank_PPU();
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break;
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case 0x03:
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chr5 = data;
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SetBank_PPU();
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break;
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case 0x04:
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chr6 = data;
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SetBank_PPU();
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break;
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case 0x05:
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chr7 = data;
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SetBank_PPU();
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break;
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case 0x06:
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prg0 = data;
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SetBank_CPU();
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break;
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case 0x07:
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prg1 = data;
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SetBank_CPU();
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break;
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case 0x08:
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prg2 = data;
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SetBank_CPU();
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break;
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case 0x09:
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prg3 = data;
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SetBank_CPU();
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break;
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case 0x0a:
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chr1 = data;
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SetBank_PPU();
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break;
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case 0x0b:
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chr3 = data;
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SetBank_PPU();
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break;
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}
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break;
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case 0xA000:
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reg[2] = data;
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data &= 0x03;
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if ( data == 0 ) SetVRAM_Mirror( VRAM_VMIRROR );
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else if ( data == 1 ) SetVRAM_Mirror( VRAM_HMIRROR );
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else if ( data == 2 ) SetVRAM_Mirror( VRAM_MIRROR4L );
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else SetVRAM_Mirror( VRAM_MIRROR4H );
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break;
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case 0xA001:
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// DEBUGOUT("Write : Address=%04X Data=%02X\n", addr&0xFFFF, data&0xFF );
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reg[3] = data;
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we_sram = data;
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break;
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case 0xC000:
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reg[4] = data;
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irq_counter = data;
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irq_request = 0;
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break;
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case 0xC001:
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reg[5] = data;
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irq_latch = data;
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irq_request = 0;
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break;
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case 0xE000:
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reg[6] = data;
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irq_enable = 0;
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irq_request = 0;
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nes->cpu->ClrIRQ( IRQ_MAPPER );
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break;
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case 0xE001:
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reg[7] = data;
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irq_enable = 1;
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irq_request = 0;
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break;
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}
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}
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void Mapper074::HSync( INT scanline )
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{
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if( (scanline >= 0 && scanline <= 239) ) {
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if( nes->ppu->IsDispON() ) {
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if( irq_enable && !irq_request ) {
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if( scanline == 0 ) {
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if( irq_counter ) {
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irq_counter -= 1;
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}
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}
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if(!(irq_counter)){
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irq_request = 0xFF;
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irq_counter = irq_latch;
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nes->cpu->SetIRQ( IRQ_MAPPER );
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}
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irq_counter--;
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}
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}
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}
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}
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void Mapper074::SetBank_CPU()
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{
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if( reg[0] & 0x40 ) {
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SetPROM_32K_Bank( prg2, prg1, prg0, prg3 );
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} else {
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SetPROM_32K_Bank( prg0, prg1, prg2, prg3 );
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}
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}
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void Mapper074::SetBank_PPU()
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{
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if( VROM_1K_SIZE ) {
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if( reg[0] & 0x80 ) {
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SetVROM_1K_Bank( 4, chr01);
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SetVROM_1K_Bank( 5, chr1 );
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SetVROM_1K_Bank( 6, chr23);
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SetVROM_1K_Bank( 7, chr3 );
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SetVROM_1K_Bank( 0, chr4 );
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SetVROM_1K_Bank( 1, chr5 );
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SetVROM_1K_Bank( 2, chr6 );
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SetVROM_1K_Bank( 3, chr7 );
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} else {
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SetVROM_1K_Bank( 0, chr01);
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SetVROM_1K_Bank( 1, chr1 );
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SetVROM_1K_Bank( 2, chr23);
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SetVROM_1K_Bank( 3, chr3 );
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SetVROM_1K_Bank( 4, chr4 );
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SetVROM_1K_Bank( 5, chr5 );
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SetVROM_1K_Bank( 6, chr6 );
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SetVROM_1K_Bank( 7, chr7 );
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if(sp_rom==1){ //[KT-1005] Feng Shen Bang (C)
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SetVROM_2K_Bank( 0, chr01);
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SetVROM_2K_Bank( 2, chr23);
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SetVROM_2K_Bank( 4, chr4 );
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SetVROM_2K_Bank( 6, chr6 );
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}
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}
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} else {
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if( reg[0] & 0x80 ) {
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SetCRAM_1K_Bank( 4, (chr01+0)&0x07 );
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SetCRAM_1K_Bank( 5, (chr01+1)&0x07 );
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SetCRAM_1K_Bank( 6, (chr23+0)&0x07 );
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SetCRAM_1K_Bank( 7, (chr23+1)&0x07 );
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SetCRAM_1K_Bank( 0, chr4&0x07 );
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SetCRAM_1K_Bank( 1, chr5&0x07 );
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SetCRAM_1K_Bank( 2, chr6&0x07 );
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SetCRAM_1K_Bank( 3, chr7&0x07 );
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} else {
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SetCRAM_1K_Bank( 0, (chr01+0)&0x07 );
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SetCRAM_1K_Bank( 1, (chr01+1)&0x07 );
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SetCRAM_1K_Bank( 2, (chr23+0)&0x07 );
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SetCRAM_1K_Bank( 3, (chr23+1)&0x07 );
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SetCRAM_1K_Bank( 4, chr4&0x07 );
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SetCRAM_1K_Bank( 5, chr5&0x07 );
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SetCRAM_1K_Bank( 6, chr6&0x07 );
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SetCRAM_1K_Bank( 7, chr7&0x07 );
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}
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}
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}
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void Mapper074::Decode_PROM()
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{
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memcpy(BDRAM,PROM,0x80000);
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for(INT i=0;i<0x80000;i++)
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{
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switch(BDRAM[i]&0x0F){
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case 0x01:BDRAM[i]=(BDRAM[i]&0xF0)|0x08;break;
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case 0x02:BDRAM[i]=(BDRAM[i]&0xF0)|0x04;break;
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case 0x03:BDRAM[i]=(BDRAM[i]&0xF0)|0x0C;break;
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case 0x04:BDRAM[i]=(BDRAM[i]&0xF0)|0x02;break;
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case 0x05:BDRAM[i]=(BDRAM[i]&0xF0)|0x0A;break;
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case 0x07:BDRAM[i]=(BDRAM[i]&0xF0)|0x0E;break;
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case 0x08:BDRAM[i]=(BDRAM[i]&0xF0)|0x01;break;
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case 0x0A:BDRAM[i]=(BDRAM[i]&0xF0)|0x05;break;
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case 0x0B:BDRAM[i]=(BDRAM[i]&0xF0)|0x0D;break;
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case 0x0C:BDRAM[i]=(BDRAM[i]&0xF0)|0x03;break;
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case 0x0D:BDRAM[i]=(BDRAM[i]&0xF0)|0x0B;break;
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case 0x0E:BDRAM[i]=(BDRAM[i]&0xF0)|0x07;break;
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}
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}
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memcpy(PROM,BDRAM,0x80000);
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memcpy(&PROM[0x01*0x4000],&BDRAM[0x04*0x4000],0x4000);
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memcpy(&PROM[0x03*0x4000],&BDRAM[0x06*0x4000],0x4000);
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memcpy(&PROM[0x04*0x4000],&BDRAM[0x01*0x4000],0x4000);
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memcpy(&PROM[0x06*0x4000],&BDRAM[0x03*0x4000],0x4000);
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memcpy(&PROM[0x09*0x4000],&BDRAM[0x0C*0x4000],0x4000);
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memcpy(&PROM[0x0B*0x4000],&BDRAM[0x0E*0x4000],0x4000);
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memcpy(&PROM[0x0C*0x4000],&BDRAM[0x09*0x4000],0x4000);
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memcpy(&PROM[0x0E*0x4000],&BDRAM[0x0B*0x4000],0x4000);
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memcpy(&PROM[0x11*0x4000],&BDRAM[0x14*0x4000],0x4000);
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}
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void Mapper074::SaveState( LPBYTE p )
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{
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for( INT i = 0; i < 8; i++ ) {
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p[i] = reg[i];
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}
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p[ 8] = prg0;
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p[ 9] = prg1;
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p[10] = chr01;
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p[11] = chr23;
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p[12] = chr4;
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p[13] = chr5;
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p[14] = chr6;
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p[15] = chr7;
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p[16] = irq_enable;
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p[17] = irq_counter;
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p[18] = irq_latch;
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p[19] = irq_request;
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p[20] = prg2;
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p[21] = prg3;
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p[22] = chr1;
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p[23] = chr3;
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}
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void Mapper074::LoadState( LPBYTE p )
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{
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for( INT i = 0; i < 8; i++ ) {
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reg[i] = p[i];
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}
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prg0 = p[ 8];
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prg1 = p[ 9];
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prg2 = p[20];
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prg3 = p[21];
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chr01 = p[10];
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chr1 = p[22];
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chr23 = p[11];
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chr3 = p[23];
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chr4 = p[12];
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chr5 = p[13];
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chr6 = p[14];
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chr7 = p[15];
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irq_enable = p[16];
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irq_counter = p[17];
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irq_latch = p[18];
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irq_request = p[19];
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}
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