332 lines
10 KiB
C#
332 lines
10 KiB
C#
using static VirtualNes.Core.CPU;
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using static VirtualNes.MMU;
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using BYTE = System.Byte;
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using INT = System.Int32;
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namespace VirtualNes.Core
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{
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public class Mapper012 : Mapper
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{
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uint vb0, vb1;
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BYTE[] reg = new byte[8];
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BYTE prg0, prg1;
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BYTE chr01, chr23, chr4, chr5, chr6, chr7;
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BYTE we_sram;
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BYTE irq_enable;
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BYTE irq_counter;
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BYTE irq_latch;
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BYTE irq_request;
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BYTE irq_preset;
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BYTE irq_preset_vbl;
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public Mapper012(NES parent) : base(parent) { }
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public override void Reset()
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{
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for (INT i = 0; i < 8; i++)
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{
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reg[i] = 0x00;
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}
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prg0 = 0;
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prg1 = 1;
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SetBank_CPU();
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vb0 = 0;
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vb1 = 0;
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chr01 = 0;
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chr23 = 2;
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chr4 = 4;
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chr5 = 5;
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chr6 = 6;
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chr7 = 7;
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SetBank_PPU();
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we_sram = 0; // Disable
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irq_enable = 0; // Disable
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irq_counter = 0;
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irq_latch = 0xFF;
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irq_request = 0;
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irq_preset = 0;
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irq_preset_vbl = 0;
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}
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//void Mapper012::WriteLow(WORD addr, BYTE data)
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public override void WriteLow(ushort addr, byte data)
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{
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if (addr > 0x4100 && addr < 0x6000)
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{
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vb0 = (byte)((data & 0x01) << 8);
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vb1 = (byte)((data & 0x10) << 4);
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SetBank_PPU();
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}
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else
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{
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base.WriteLow(addr, data);
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}
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}
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//BYTE Mapper012::ReadLow(WORD addr)
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public override byte ReadLow(ushort addr)
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{
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return 0x01;
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}
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//void Mapper012::Write(WORD addr, BYTE data)
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public override void Write(ushort addr, byte data)
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{
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//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() );
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switch (addr & 0xE001)
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{
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case 0x8000:
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reg[0] = data;
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SetBank_CPU();
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SetBank_PPU();
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break;
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case 0x8001:
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reg[1] = data;
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switch (reg[0] & 0x07)
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{
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case 0x00:
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chr01 = (byte)(data & 0xFE);
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SetBank_PPU();
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break;
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case 0x01:
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chr23 = (byte)(data & 0xFE);
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SetBank_PPU();
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break;
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case 0x02:
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chr4 = data;
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SetBank_PPU();
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break;
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case 0x03:
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chr5 = data;
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SetBank_PPU();
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break;
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case 0x04:
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chr6 = data;
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SetBank_PPU();
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break;
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case 0x05:
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chr7 = data;
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SetBank_PPU();
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break;
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case 0x06:
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prg0 = data;
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SetBank_CPU();
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break;
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case 0x07:
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prg1 = data;
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SetBank_CPU();
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break;
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}
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break;
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case 0xA000:
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reg[2] = data;
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if (!nes.rom.Is4SCREEN())
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{
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if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
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else SetVRAM_Mirror(VRAM_VMIRROR);
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}
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break;
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case 0xA001:
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reg[3] = data;
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break;
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case 0xC000:
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reg[4] = data;
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irq_latch = data;
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break;
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case 0xC001:
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reg[5] = data;
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if (nes.GetScanline() < 240)
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{
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irq_counter |= 0x80;
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irq_preset = 0xFF;
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}
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else
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{
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irq_counter |= 0x80;
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irq_preset_vbl = 0xFF;
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irq_preset = 0;
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}
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break;
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case 0xE000:
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reg[6] = data;
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irq_enable = 0;
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irq_request = 0;
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nes.cpu.ClrIRQ(IRQ_MAPPER);
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break;
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case 0xE001:
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reg[7] = data;
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irq_enable = 1;
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irq_request = 0;
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break;
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}
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}
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//void Mapper012::HSync(INT scanline)
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public override void HSync(int scanline)
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{
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if ((scanline >= 0 && scanline <= 239) && nes.ppu.IsDispON())
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{
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if (irq_preset_vbl != 0)
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{
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irq_counter = irq_latch;
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irq_preset_vbl = 0;
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}
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if (irq_preset != 0)
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{
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irq_counter = irq_latch;
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irq_preset = 0;
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}
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else if (irq_counter > 0)
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{
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irq_counter--;
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}
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if (irq_counter == 0)
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{
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// Some game set irq_latch to zero to disable irq. So check it here.
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if (irq_enable != 0 && irq_latch != 0)
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{
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irq_request = 0xFF;
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nes.cpu.SetIRQ(IRQ_MAPPER);
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}
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irq_preset = 0xFF;
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}
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}
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}
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void SetBank_CPU()
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{
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if ((reg[0] & 0x40) != 0)
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{
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SetPROM_32K_Bank(PROM_8K_SIZE - 2, prg1, prg0, PROM_8K_SIZE - 1);
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}
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else
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{
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SetPROM_32K_Bank(prg0, prg1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
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}
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}
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void SetBank_PPU()
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{
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if (VROM_1K_SIZE != 0)
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{
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if ((reg[0] & 0x80) != 0)
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{
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SetVROM_8K_Bank(
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(int)(vb0 + chr4),
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(int)(vb0 + chr5),
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(int)(vb0 + chr6),
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(int)(vb0 + chr7),
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(int)(vb1 + chr01),
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(int)(vb1 + chr01 + 1),
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(int)(vb1 + chr23),
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(int)(vb1 + chr23 + 1)
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);
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}
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else
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{
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SetVROM_8K_Bank(
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(int)(vb0 + chr01),
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(int)(vb0 + chr01 + 1),
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(int)(vb0 + chr23),
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(int)(vb0 + chr23 + 1),
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(int)(vb1 + chr4),
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(int)(vb1 + chr5),
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(int)(vb1 + chr6),
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(int)(vb1 + chr7))
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;
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}
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}
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else
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{
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if ((reg[0] & 0x80) != 0)
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{
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SetCRAM_1K_Bank(4, (chr01 + 0) & 0x07);
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SetCRAM_1K_Bank(5, (chr01 + 1) & 0x07);
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SetCRAM_1K_Bank(6, (chr23 + 0) & 0x07);
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SetCRAM_1K_Bank(7, (chr23 + 1) & 0x07);
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SetCRAM_1K_Bank(0, chr4 & 0x07);
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SetCRAM_1K_Bank(1, chr5 & 0x07);
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SetCRAM_1K_Bank(2, chr6 & 0x07);
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SetCRAM_1K_Bank(3, chr7 & 0x07);
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}
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else
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{
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SetCRAM_1K_Bank(0, (chr01 + 0) & 0x07);
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SetCRAM_1K_Bank(1, (chr01 + 1) & 0x07);
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SetCRAM_1K_Bank(2, (chr23 + 0) & 0x07);
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SetCRAM_1K_Bank(3, (chr23 + 1) & 0x07);
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SetCRAM_1K_Bank(4, chr4 & 0x07);
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SetCRAM_1K_Bank(5, chr5 & 0x07);
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SetCRAM_1K_Bank(6, chr6 & 0x07);
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SetCRAM_1K_Bank(7, chr7 & 0x07);
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}
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}
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}
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//void Mapper012::SaveState(LPBYTE p)
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public override void SaveState(byte[] p)
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{
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//for (INT i = 0; i < 8; i++)
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//{
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// p[i] = reg[i];
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//}
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//p[8] = prg0;
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//p[9] = prg1;
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//p[10] = chr01;
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//p[11] = chr23;
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//p[12] = chr4;
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//p[13] = chr5;
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//p[14] = chr6;
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//p[15] = chr7;
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//p[16] = irq_enable;
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//p[17] = (BYTE)irq_counter;
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//p[18] = irq_latch;
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//p[19] = irq_request;
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//p[20] = irq_preset;
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//p[21] = irq_preset_vbl;
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//*((DWORD*)&p[22]) = vb0;
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//*((DWORD*)&p[26]) = vb1;
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}
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//void Mapper012::LoadState(LPBYTE p)
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public override void LoadState(byte[] p)
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{
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//for (INT i = 0; i < 8; i++)
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//{
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// reg[i] = p[i];
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//}
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//prg0 = p[8];
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//prg1 = p[9];
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//chr01 = p[10];
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//chr23 = p[11];
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//chr4 = p[12];
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//chr5 = p[13];
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//chr6 = p[14];
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//chr7 = p[15];
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//irq_enable = p[16];
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//irq_counter = (INT)p[17];
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//irq_latch = p[18];
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//irq_request = p[19];
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//irq_preset = p[20];
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//irq_preset_vbl = p[21];
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//vb0 = *((DWORD*)&p[22]);
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//vb1 = *((DWORD*)&p[26]);
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}
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public override bool IsStateSave()
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{
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return true;
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}
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}
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}
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