113 lines
2.6 KiB
C#
113 lines
2.6 KiB
C#
using System.IO;
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namespace MyNes.Core
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{
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[BoardInfo("Unknown", 207)]
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[HassIssues]
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internal class Mapper207 : Board
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{
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private int mirroring0;
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private int mirroring1;
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internal override string Issues => MNInterfaceLanguage.IssueMapper207;
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internal override void HardReset()
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{
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base.HardReset();
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Switch08KPRG(PRG_ROM_08KB_Mask, PRGArea.AreaE000);
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}
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internal override void WriteSRM(ref ushort address, ref byte data)
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{
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switch (address)
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{
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case 32496:
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Switch02KCHR(data & 0x3F, CHRArea.Area0000);
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mirroring0 = (data >> 7) & 1;
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break;
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case 32497:
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Switch02KCHR(data & 0x3F, CHRArea.Area0800);
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mirroring1 = (data >> 7) & 1;
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break;
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case 32498:
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Switch01KCHR(data, CHRArea.Area1000);
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break;
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case 32499:
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Switch01KCHR(data, CHRArea.Area1400);
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break;
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case 32500:
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Switch01KCHR(data, CHRArea.Area1800);
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break;
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case 32501:
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Switch01KCHR(data, CHRArea.Area1C00);
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break;
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case 32506:
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case 32507:
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Switch08KPRG(data, PRGArea.Area8000);
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break;
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case 32508:
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case 32509:
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Switch08KPRG(data, PRGArea.AreaA000);
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break;
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case 32510:
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case 32511:
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Switch08KPRG(data, PRGArea.AreaC000);
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break;
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case 32502:
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case 32503:
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case 32504:
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case 32505:
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break;
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}
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}
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internal override void ReadNMT(ref ushort address, out byte data)
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{
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switch ((address >> 10) & 3)
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{
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case 0:
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case 1:
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data = NMT_RAM[mirroring0][address & 0x3FF];
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break;
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case 2:
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case 3:
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data = NMT_RAM[mirroring1][address & 0x3FF];
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break;
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default:
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data = 0;
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break;
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}
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}
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internal override void WriteNMT(ref ushort address, ref byte data)
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{
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switch ((address >> 10) & 3)
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{
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case 0:
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case 1:
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NMT_RAM[mirroring0][address & 0x3FF] = data;
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break;
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case 2:
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case 3:
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NMT_RAM[mirroring1][address & 0x3FF] = data;
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break;
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}
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}
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internal override void WriteStateData(ref BinaryWriter stream)
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{
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base.WriteStateData(ref stream);
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stream.Write(mirroring0);
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stream.Write(mirroring1);
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}
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internal override void ReadStateData(ref BinaryReader stream)
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{
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base.ReadStateData(ref stream);
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mirroring0 = stream.ReadInt32();
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mirroring1 = stream.ReadInt32();
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}
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}
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}
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