871 lines
23 KiB
C#
871 lines
23 KiB
C#
using System;
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using System.IO;
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namespace MyNes.Core
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{
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[BoardInfo("MMC5", 5, 8, 16)]
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[WithExternalSound]
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[HassIssues]
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internal class Mapper005 : Board
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{
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private int ram_protectA;
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private int ram_protectB;
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private int ExRAM_mode;
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private int[] CHROffset_spr;
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private int[] CHROffsetEX;
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private int[] CHROffsetSP;
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private int[] chrRegA;
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private int[] chrRegB;
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private int[] prgReg;
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private bool useSRAMmirroring;
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private int chr_high;
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private int chr_mode;
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private int prg_mode;
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private bool chr_setB_last;
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private byte temp_val;
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private byte temp_fill;
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private int lastAccessVRAM;
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private int paletteNo;
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private int shift;
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private int EXtilenumber;
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private byte multiplicand;
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private byte multiplier;
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private ushort product;
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private bool split_enable;
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private bool split_right;
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private int split_tile;
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private int split_yscroll;
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private bool split_doit;
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private int split_watch_tile;
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private byte irq_line;
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private byte irq_enable;
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private int irq_pending;
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private int irq_current_counter;
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private int irq_current_inframe;
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private MMC5Sqr snd_1;
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private MMC5Sqr snd_2;
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private MMC5Pcm snd_3;
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private double[] audio_pulse_table;
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private double[] audio_tnd_table;
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internal override string Issues => MNInterfaceLanguage.IssueMapper5;
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internal override void Initialize(IRom rom)
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{
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base.Initialize(rom);
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snd_1 = new MMC5Sqr();
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snd_2 = new MMC5Sqr();
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snd_3 = new MMC5Pcm();
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audio_pulse_table = new double[32];
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for (int i = 0; i < 32; i++)
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{
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audio_pulse_table[i] = 95.52 / (8128.0 / (double)i + 100.0);
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}
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audio_tnd_table = new double[204];
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for (int j = 0; j < 204; j++)
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{
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audio_tnd_table[j] = 163.67 / (24329.0 / (double)j + 100.0);
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}
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}
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internal override void HardReset()
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{
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base.HardReset();
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switch (SHA1.ToUpper())
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{
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case "37267833C984F176DB4B0BC9D45DABA0FFF45304":
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useSRAMmirroring = true;
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break;
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case "800AEFE756E85A0A78CCB4DAE68EBBA5DF24BF41":
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useSRAMmirroring = true;
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break;
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}
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Console.WriteLine("MMC5: using PRG RAM mirroring = " + useSRAMmirroring);
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CHROffset_spr = new int[8];
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CHROffsetEX = new int[8];
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CHROffsetSP = new int[8];
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chrRegA = new int[8];
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chrRegB = new int[4];
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prgReg = new int[4];
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prgReg[3] = PRG_ROM_08KB_Mask;
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prg_mode = 3;
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Switch08KPRG(PRG_ROM_08KB_Mask, PRGArea.Area8000);
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Switch08KPRG(PRG_ROM_08KB_Mask, PRGArea.AreaA000);
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Switch08KPRG(PRG_ROM_08KB_Mask, PRGArea.AreaC000);
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Switch08KPRG(PRG_ROM_08KB_Mask, PRGArea.AreaE000);
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Switch04kCHREX(0, 0);
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Switch04kCHRSP(0, 0);
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Switch08kCHR_spr(0);
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TogglePRGRAMWritableEnable(enable: true);
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TogglePRGRAMEnable(enable: true);
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APUApplyChannelsSettings();
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snd_1.HardReset();
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snd_2.HardReset();
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snd_3.HardReset();
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}
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internal override void SoftReset()
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{
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base.SoftReset();
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snd_1.SoftReset();
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snd_2.SoftReset();
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snd_3.SoftReset();
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}
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internal override void WriteEX(ref ushort address, ref byte value)
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{
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if (address >= 23552)
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{
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if (ExRAM_mode == 2)
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{
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NMT_RAM[2][address & 0x3FF] = value;
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}
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else if (ExRAM_mode < 2)
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{
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if (irq_current_inframe == 64)
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{
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NMT_RAM[2][address & 0x3FF] = value;
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}
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else
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{
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NMT_RAM[2][address & 0x3FF] = 0;
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}
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}
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return;
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}
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switch (address)
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{
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case 20480:
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snd_1.Write0(ref value);
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break;
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case 20482:
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snd_1.Write2(ref value);
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break;
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case 20483:
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snd_1.Write3(ref value);
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break;
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case 20484:
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snd_2.Write0(ref value);
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break;
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case 20486:
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snd_2.Write2(ref value);
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break;
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case 20487:
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snd_2.Write3(ref value);
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break;
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case 20496:
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snd_3.Write5010(value);
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break;
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case 20497:
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snd_3.Write5011(value);
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break;
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case 20501:
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snd_1.WriteEnabled((value & 1) != 0);
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snd_2.WriteEnabled((value & 2) != 0);
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break;
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case 20736:
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prg_mode = value & 3;
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break;
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case 20737:
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chr_mode = value & 3;
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break;
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case 20738:
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ram_protectA = value & 3;
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UpdateRamProtect();
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break;
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case 20739:
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ram_protectB = value & 3;
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UpdateRamProtect();
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break;
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case 20740:
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ExRAM_mode = value & 3;
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break;
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case 20741:
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Switch01KNMT(value);
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break;
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case 20755:
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if (!useSRAMmirroring)
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{
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Switch08KPRG(value & 7, PRGArea.Area6000);
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}
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else
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{
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Switch08KPRG((value >> 2) & 1, PRGArea.Area6000);
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}
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break;
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case 20756:
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if (prg_mode == 3)
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{
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Toggle08KPRG_RAM((value & 0x80) == 0, PRGArea.Area8000);
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Switch08KPRG(value & 0x7F, PRGArea.Area8000);
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}
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break;
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case 20757:
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switch (prg_mode)
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{
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case 1:
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Toggle16KPRG_RAM((value & 0x80) == 0, PRGArea.Area8000);
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Switch16KPRG((value & 0x7F) >> 1, PRGArea.Area8000);
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break;
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case 2:
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Toggle16KPRG_RAM((value & 0x80) == 0, PRGArea.Area8000);
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Switch16KPRG((value & 0x7F) >> 1, PRGArea.Area8000);
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break;
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case 3:
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Toggle08KPRG_RAM((value & 0x80) == 0, PRGArea.AreaA000);
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Switch08KPRG(value & 0x7F, PRGArea.AreaA000);
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break;
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}
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break;
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case 20758:
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{
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int num = prg_mode;
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if ((uint)(num - 2) <= 1u)
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{
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Toggle08KPRG_RAM((value & 0x80) == 0, PRGArea.AreaC000);
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Switch08KPRG(value & 0x7F, PRGArea.AreaC000);
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}
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break;
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}
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case 20759:
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switch (prg_mode)
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{
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case 0:
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Switch32KPRG((value & 0x7C) >> 2, PRGArea.Area8000);
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break;
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case 1:
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Switch16KPRG((value & 0x7F) >> 1, PRGArea.AreaC000);
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break;
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case 2:
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Switch08KPRG(value & 0x7F, PRGArea.AreaE000);
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break;
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case 3:
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Switch08KPRG(value & 0x7F, PRGArea.AreaE000);
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break;
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}
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break;
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case 20768:
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chr_setB_last = false;
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if (chr_mode == 3)
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{
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Switch01kCHR_spr(value | chr_high, 0);
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}
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break;
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case 20769:
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chr_setB_last = false;
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switch (chr_mode)
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{
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case 2:
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Switch02kCHR_spr(value | chr_high, 0);
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break;
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case 3:
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Switch01kCHR_spr(value | chr_high, 1024);
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break;
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}
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break;
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case 20770:
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chr_setB_last = false;
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if (chr_mode == 3)
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{
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Switch01kCHR_spr(value | chr_high, 2048);
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}
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break;
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case 20771:
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chr_setB_last = false;
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switch (chr_mode)
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{
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case 1:
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Switch04kCHR_spr(value | chr_high, 0);
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break;
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case 2:
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Switch02kCHR_spr(value | chr_high, 2048);
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break;
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case 3:
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Switch01kCHR_spr(value | chr_high, 3072);
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break;
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}
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break;
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case 20772:
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chr_setB_last = false;
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if (chr_mode == 3)
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{
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Switch01kCHR_spr(value | chr_high, 4096);
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}
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break;
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case 20773:
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chr_setB_last = false;
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switch (chr_mode)
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{
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case 2:
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Switch02kCHR_spr(value | chr_high, 4096);
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break;
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case 3:
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Switch01kCHR_spr(value | chr_high, 5120);
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break;
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}
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break;
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case 20774:
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chr_setB_last = false;
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if (chr_mode == 3)
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{
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Switch01kCHR_spr(value | chr_high, 6144);
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}
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break;
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case 20775:
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chr_setB_last = false;
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switch (chr_mode)
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{
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case 0:
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Switch08kCHR_spr(value | chr_high);
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break;
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case 1:
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Switch04kCHR_spr(value | chr_high, 4096);
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break;
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case 2:
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Switch02kCHR_spr(value | chr_high, 6144);
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break;
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case 3:
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Switch01kCHR_spr(value | chr_high, 7168);
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break;
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}
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break;
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case 20776:
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chr_setB_last = true;
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if (chr_mode == 3)
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{
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Switch01KCHR(value | chr_high, CHRArea.Area0000);
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Switch01KCHR(value | chr_high, CHRArea.Area1000);
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}
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break;
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case 20777:
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chr_setB_last = true;
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switch (chr_mode)
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{
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case 2:
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Switch02KCHR(value | chr_high, CHRArea.Area0000);
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Switch02KCHR(value | chr_high, CHRArea.Area1000);
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break;
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case 3:
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Switch01KCHR(value | chr_high, CHRArea.Area0400);
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Switch01KCHR(value | chr_high, CHRArea.Area1400);
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break;
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}
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break;
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case 20778:
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chr_setB_last = true;
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if (chr_mode == 3)
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{
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Switch01KCHR(value | chr_high, CHRArea.Area0800);
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Switch01KCHR(value | chr_high, CHRArea.Area1800);
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}
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break;
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case 20779:
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chr_setB_last = true;
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switch (chr_mode)
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{
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case 0:
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Switch04kCHR_bkg(value | chr_high, 0);
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Switch04kCHR_bkg(value | chr_high, 4096);
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break;
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case 1:
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Switch04KCHR(value | chr_high, CHRArea.Area0000);
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Switch04KCHR(value | chr_high, CHRArea.Area1000);
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break;
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case 2:
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Switch02KCHR(value | chr_high, CHRArea.Area0800);
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Switch02KCHR(value | chr_high, CHRArea.Area1800);
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break;
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case 3:
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Switch01KCHR(value | chr_high, CHRArea.Area0C00);
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Switch01KCHR(value | chr_high, CHRArea.Area1C00);
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break;
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}
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break;
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case 20784:
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chr_high = (value & 3) << 8;
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break;
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case 20742:
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{
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for (int j = 0; j < 960; j++)
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{
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NMT_RAM[3][j] = value;
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}
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break;
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}
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case 20743:
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{
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for (int i = 960; i < 1024; i++)
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{
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temp_fill = (byte)((uint)(2 << (value & 3)) | (value & 3u));
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temp_fill |= (byte)((temp_fill & 0xF) << 4);
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NMT_RAM[3][i] = temp_fill;
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}
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break;
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}
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case 20992:
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split_tile = value & 0x1F;
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split_enable = (value & 0x80) == 128;
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split_right = (value & 0x40) == 64;
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break;
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case 20993:
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split_yscroll = value;
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break;
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case 20994:
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Switch04kCHRSP(value, address & 0);
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Switch04kCHRSP(value, address & 0x1000);
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break;
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case 20995:
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irq_line = value;
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break;
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case 20996:
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irq_enable = value;
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break;
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case 20997:
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multiplicand = value;
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product = (ushort)(multiplicand * multiplier);
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break;
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case 20998:
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multiplier = value;
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product = (ushort)(multiplicand * multiplier);
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break;
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}
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}
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internal override void ReadEX(ref ushort address, out byte data)
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{
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if (address >= 23552 && ExRAM_mode >= 2)
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{
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data = NMT_RAM[2][address & 0x3FF];
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return;
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}
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switch (address)
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{
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case 20496:
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data = snd_3.Read5010();
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break;
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case 20996:
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data = (byte)(irq_current_inframe | irq_pending);
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irq_pending = 0;
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NesEmu.IRQFlags &= -9;
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break;
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case 20997:
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data = (byte)(product & 0xFFu);
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break;
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case 20998:
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data = (byte)((product & 0xFF00) >> 8);
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break;
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case 20501:
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data = (byte)((snd_1.ReadEnable() ? 1u : 0u) | (snd_2.ReadEnable() ? 2u : 0u));
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data = 0;
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break;
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default:
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data = 0;
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break;
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}
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}
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internal override void ReadCHR(ref ushort address, out byte data)
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{
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if (!NesEmu.ppu_is_sprfetch && split_enable && ExRAM_mode < 2)
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{
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split_watch_tile = address & 0x3F;
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if (!split_right)
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{
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split_doit = split_watch_tile < split_tile;
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}
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else
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{
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split_doit = split_watch_tile >= split_tile;
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}
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_ = split_doit;
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}
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if (ExRAM_mode == 1)
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{
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if (!NesEmu.ppu_is_sprfetch)
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{
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EXtilenumber = NMT_RAM[2][lastAccessVRAM] & 0x3F;
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Switch04kCHREX(EXtilenumber | chr_high, address & 0x1000);
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data = CHR_ROM[CHROffsetEX[(address >> 10) & 7]][address & 0x3FF];
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}
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else
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{
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data = CHR_ROM[CHROffset_spr[(address >> 10) & 7]][address & 0x3FF];
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}
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}
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else if (NesEmu.ppu_reg_2000_Sprite_size == 16)
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{
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if (!NesEmu.ppu_is_sprfetch)
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{
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data = CHR_ROM[CHR_AREA_BLK_INDEX[(address >> 10) & 7]][address & 0x3FF];
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}
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else
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{
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data = CHR_ROM[CHROffset_spr[(address >> 10) & 7]][address & 0x3FF];
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}
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}
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else if (chr_setB_last)
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{
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data = CHR_ROM[CHR_AREA_BLK_INDEX[(address >> 10) & 7]][address & 0x3FF];
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}
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else
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{
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data = CHR_ROM[CHROffset_spr[(address >> 10) & 7]][address & 0x3FF];
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}
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}
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internal override void ReadNMT(ref ushort address, out byte data)
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{
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_ = split_doit;
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if (ExRAM_mode == 1)
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{
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if ((address & 0x3FF) <= 959)
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{
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lastAccessVRAM = address & 0x3FF;
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}
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else
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{
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paletteNo = NMT_RAM[2][lastAccessVRAM] & 0xC0;
|
|
shift = ((lastAccessVRAM >> 4) & 4) | (lastAccessVRAM & 2);
|
|
switch (shift)
|
|
{
|
|
case 0:
|
|
data = (byte)(paletteNo >> 6);
|
|
return;
|
|
case 2:
|
|
data = (byte)(paletteNo >> 4);
|
|
return;
|
|
case 4:
|
|
data = (byte)(paletteNo >> 2);
|
|
return;
|
|
case 6:
|
|
data = (byte)paletteNo;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
data = NMT_RAM[NMT_AREA_BLK_INDEX[(address >> 10) & 3]][address & 0x3FF];
|
|
}
|
|
|
|
internal override void WriteNMT(ref ushort address, ref byte value)
|
|
{
|
|
if (ExRAM_mode == 1 && (address & 0x3FF) <= 959)
|
|
{
|
|
lastAccessVRAM = address & 0x3FF;
|
|
}
|
|
NMT_RAM[NMT_AREA_BLK_INDEX[(address >> 10) & 3]][address & 0x3FF] = value;
|
|
}
|
|
|
|
private void UpdateRamProtect()
|
|
{
|
|
TogglePRGRAMWritableEnable(ram_protectA == 2 && ram_protectB == 1);
|
|
}
|
|
|
|
private void Switch04kCHR_bkg(int index, int where)
|
|
{
|
|
int num = (where >> 10) & 7;
|
|
index <<= 2;
|
|
CHR_AREA_BLK_INDEX[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHR_AREA_BLK_INDEX[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHR_AREA_BLK_INDEX[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHR_AREA_BLK_INDEX[num] = index & CHR_ROM_01KB_Mask;
|
|
}
|
|
|
|
private void Switch01kCHR_spr(int index, int where)
|
|
{
|
|
CHROffset_spr[(where >> 10) & 7] = index & CHR_ROM_01KB_Mask;
|
|
}
|
|
|
|
private void Switch02kCHR_spr(int index, int where)
|
|
{
|
|
int num = (where >> 10) & 7;
|
|
index <<= 1;
|
|
CHROffset_spr[num] = index & CHR_ROM_01KB_Mask;
|
|
index++;
|
|
CHROffset_spr[num + 1] = index & CHR_ROM_01KB_Mask;
|
|
}
|
|
|
|
private void Switch04kCHR_spr(int index, int where)
|
|
{
|
|
int num = (where >> 10) & 7;
|
|
index <<= 2;
|
|
CHROffset_spr[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHROffset_spr[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHROffset_spr[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHROffset_spr[num] = index & CHR_ROM_01KB_Mask;
|
|
}
|
|
|
|
private void Switch08kCHR_spr(int index)
|
|
{
|
|
index <<= 3;
|
|
CHROffset_spr[0] = index & CHR_ROM_01KB_Mask;
|
|
index++;
|
|
CHROffset_spr[1] = index & CHR_ROM_01KB_Mask;
|
|
index++;
|
|
CHROffset_spr[2] = index & CHR_ROM_01KB_Mask;
|
|
index++;
|
|
CHROffset_spr[3] = index & CHR_ROM_01KB_Mask;
|
|
index++;
|
|
CHROffset_spr[4] = index & CHR_ROM_01KB_Mask;
|
|
index++;
|
|
CHROffset_spr[5] = index & CHR_ROM_01KB_Mask;
|
|
index++;
|
|
CHROffset_spr[6] = index & CHR_ROM_01KB_Mask;
|
|
index++;
|
|
CHROffset_spr[7] = index & CHR_ROM_01KB_Mask;
|
|
}
|
|
|
|
private void Switch04kCHREX(int index, int where)
|
|
{
|
|
int num = (where >> 10) & 7;
|
|
index <<= 2;
|
|
CHROffsetEX[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHROffsetEX[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHROffsetEX[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHROffsetEX[num] = index & CHR_ROM_01KB_Mask;
|
|
}
|
|
|
|
private void Switch04kCHRSP(int index, int where)
|
|
{
|
|
int num = (where >> 10) & 7;
|
|
index <<= 2;
|
|
CHROffsetSP[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHROffsetSP[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHROffsetSP[num] = index & CHR_ROM_01KB_Mask;
|
|
num++;
|
|
index++;
|
|
CHROffsetSP[num] = index & CHR_ROM_01KB_Mask;
|
|
}
|
|
|
|
internal override void OnPPUScanlineTick()
|
|
{
|
|
irq_current_inframe = ((NesEmu.IsInRender() && NesEmu.IsRenderingOn()) ? 64 : 0);
|
|
if (irq_current_inframe == 0)
|
|
{
|
|
irq_current_inframe = 64;
|
|
irq_current_counter = 0;
|
|
irq_pending = 0;
|
|
NesEmu.IRQFlags &= -9;
|
|
return;
|
|
}
|
|
irq_current_counter++;
|
|
if (irq_current_counter == irq_line)
|
|
{
|
|
irq_pending = 128;
|
|
if (irq_enable == 128)
|
|
{
|
|
NesEmu.IRQFlags |= 8;
|
|
}
|
|
}
|
|
}
|
|
|
|
internal override void OnAPUClock()
|
|
{
|
|
base.OnAPUClock();
|
|
snd_1.Clock();
|
|
snd_2.Clock();
|
|
}
|
|
|
|
internal override void OnAPUClockEnvelope()
|
|
{
|
|
base.OnAPUClockEnvelope();
|
|
snd_1.ClockLength();
|
|
snd_2.ClockLength();
|
|
snd_1.ClockEnvelope();
|
|
snd_2.ClockEnvelope();
|
|
}
|
|
|
|
internal override double APUGetSample()
|
|
{
|
|
return audio_pulse_table[snd_1.output + snd_2.output] + audio_tnd_table[snd_3.output];
|
|
}
|
|
|
|
internal override void APUApplyChannelsSettings()
|
|
{
|
|
base.APUApplyChannelsSettings();
|
|
snd_1.Outputable = MyNesMain.RendererSettings.Audio_ChannelEnabled_MMC5_SQ1;
|
|
snd_2.Outputable = MyNesMain.RendererSettings.Audio_ChannelEnabled_MMC5_SQ2;
|
|
snd_3.Outputable = MyNesMain.RendererSettings.Audio_ChannelEnabled_MMC5_PCM;
|
|
}
|
|
|
|
internal override void WriteStateData(ref BinaryWriter stream)
|
|
{
|
|
base.WriteStateData(ref stream);
|
|
stream.Write(ram_protectA);
|
|
stream.Write(ram_protectB);
|
|
stream.Write(ExRAM_mode);
|
|
for (int i = 0; i < CHROffset_spr.Length; i++)
|
|
{
|
|
stream.Write(CHROffset_spr[i]);
|
|
}
|
|
for (int j = 0; j < CHROffsetEX.Length; j++)
|
|
{
|
|
stream.Write(CHROffsetEX[j]);
|
|
}
|
|
for (int k = 0; k < CHROffsetSP.Length; k++)
|
|
{
|
|
stream.Write(CHROffsetSP[k]);
|
|
}
|
|
for (int l = 0; l < chrRegA.Length; l++)
|
|
{
|
|
stream.Write(chrRegA[l]);
|
|
}
|
|
for (int m = 0; m < chrRegB.Length; m++)
|
|
{
|
|
stream.Write(chrRegB[m]);
|
|
}
|
|
for (int n = 0; n < prgReg.Length; n++)
|
|
{
|
|
stream.Write(prgReg[n]);
|
|
}
|
|
stream.Write(useSRAMmirroring);
|
|
stream.Write(chr_high);
|
|
stream.Write(chr_mode);
|
|
stream.Write(prg_mode);
|
|
stream.Write(chr_setB_last);
|
|
stream.Write(temp_val);
|
|
stream.Write(temp_fill);
|
|
stream.Write(lastAccessVRAM);
|
|
stream.Write(paletteNo);
|
|
stream.Write(shift);
|
|
stream.Write(EXtilenumber);
|
|
stream.Write(multiplicand);
|
|
stream.Write(multiplier);
|
|
stream.Write(product);
|
|
stream.Write(split_enable);
|
|
stream.Write(split_right);
|
|
stream.Write(split_tile);
|
|
stream.Write(split_yscroll);
|
|
stream.Write(split_doit);
|
|
stream.Write(split_watch_tile);
|
|
stream.Write(irq_line);
|
|
stream.Write(irq_enable);
|
|
stream.Write(irq_pending);
|
|
stream.Write(irq_current_counter);
|
|
stream.Write(irq_current_inframe);
|
|
snd_1.WriteStateData(ref stream);
|
|
snd_2.WriteStateData(ref stream);
|
|
snd_3.SaveState(ref stream);
|
|
}
|
|
|
|
internal override void ReadStateData(ref BinaryReader stream)
|
|
{
|
|
base.ReadStateData(ref stream);
|
|
ram_protectA = stream.ReadInt32();
|
|
ram_protectB = stream.ReadInt32();
|
|
ExRAM_mode = stream.ReadInt32();
|
|
for (int i = 0; i < CHROffset_spr.Length; i++)
|
|
{
|
|
CHROffset_spr[i] = stream.ReadInt32();
|
|
}
|
|
for (int j = 0; j < CHROffsetEX.Length; j++)
|
|
{
|
|
CHROffsetEX[j] = stream.ReadInt32();
|
|
}
|
|
for (int k = 0; k < CHROffsetSP.Length; k++)
|
|
{
|
|
CHROffsetSP[k] = stream.ReadInt32();
|
|
}
|
|
for (int l = 0; l < chrRegA.Length; l++)
|
|
{
|
|
chrRegA[l] = stream.ReadInt32();
|
|
}
|
|
for (int m = 0; m < chrRegB.Length; m++)
|
|
{
|
|
chrRegB[m] = stream.ReadInt32();
|
|
}
|
|
for (int n = 0; n < prgReg.Length; n++)
|
|
{
|
|
prgReg[n] = stream.ReadInt32();
|
|
}
|
|
useSRAMmirroring = stream.ReadBoolean();
|
|
chr_high = stream.ReadInt32();
|
|
chr_mode = stream.ReadInt32();
|
|
prg_mode = stream.ReadInt32();
|
|
chr_setB_last = stream.ReadBoolean();
|
|
temp_val = stream.ReadByte();
|
|
temp_fill = stream.ReadByte();
|
|
lastAccessVRAM = stream.ReadInt32();
|
|
paletteNo = stream.ReadInt32();
|
|
shift = stream.ReadInt32();
|
|
EXtilenumber = stream.ReadInt32();
|
|
multiplicand = stream.ReadByte();
|
|
multiplier = stream.ReadByte();
|
|
product = stream.ReadUInt16();
|
|
split_enable = stream.ReadBoolean();
|
|
split_right = stream.ReadBoolean();
|
|
split_tile = stream.ReadInt32();
|
|
split_yscroll = stream.ReadInt32();
|
|
split_doit = stream.ReadBoolean();
|
|
split_watch_tile = stream.ReadInt32();
|
|
irq_line = stream.ReadByte();
|
|
irq_enable = stream.ReadByte();
|
|
irq_pending = stream.ReadInt32();
|
|
irq_current_counter = stream.ReadInt32();
|
|
irq_current_inframe = stream.ReadInt32();
|
|
snd_1.ReadStateData(ref stream);
|
|
snd_2.ReadStateData(ref stream);
|
|
snd_3.LoadState(ref stream);
|
|
}
|
|
}
|
|
}
|