635 lines
16 KiB
C#
635 lines
16 KiB
C#
using System.IO;
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namespace MyNes.Core
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{
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[BoardInfo("Pirate MMC5-style", 90)]
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[HassIssues]
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internal class Mapper090 : Board
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{
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protected bool MAPPER90MODE;
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private int[] prg_reg;
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private int[] chr_reg;
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private int[] nt_reg;
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private int prg_mode;
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private int chr_mode;
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private bool chr_block_mode;
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private int chr_block;
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private bool chr_m;
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private bool flag_s;
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private int irqCounter = 0;
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private bool IrqEnable = false;
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private bool irqCountDownMode = false;
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private bool irqCountUpMode = false;
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private bool irqFunkyMode = false;
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private bool irqPrescalerSize = false;
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private int irqSource = 0;
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private int irqPrescaler = 0;
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private int irqPrescalerXOR = 0;
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private byte irqFunkyModeReg = 0;
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private byte Dipswitch;
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private byte multiplication_a;
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private byte multiplication_b;
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private ushort multiplication;
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private byte RAM5803;
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private bool nt_advanced_enable;
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private bool nt_rom_only;
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private int nt_ram_select;
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internal override string Issues => MNInterfaceLanguage.IssueMapper90;
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internal override void HardReset()
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{
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base.HardReset();
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MAPPER90MODE = true;
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prg_reg = new int[4];
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chr_reg = new int[8];
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nt_reg = new int[4];
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prg_mode = (chr_mode = 0);
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for (int i = 0; i < 4; i++)
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{
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prg_reg[i] = i;
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nt_reg[i] = i;
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}
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for (int j = 0; j < 8; j++)
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{
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chr_reg[j] = j;
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}
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SetupPRG();
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SetupCHR();
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Dipswitch = 0;
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irqCounter = 0;
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IrqEnable = false;
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irqCountDownMode = false;
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irqCountUpMode = false;
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irqFunkyMode = false;
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irqPrescalerSize = false;
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irqSource = 0;
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irqPrescaler = 0;
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irqPrescalerXOR = 0;
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irqFunkyModeReg = 0;
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RAM5803 = 0;
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flag_s = false;
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multiplication_a = 0;
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multiplication_b = 0;
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multiplication = 0;
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}
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internal override void SoftReset()
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{
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base.SoftReset();
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if (Dipswitch == 0)
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{
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Dipswitch = byte.MaxValue;
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}
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else
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{
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Dipswitch = 0;
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}
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}
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internal override void WritePRG(ref ushort address, ref byte data)
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{
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switch (address & 0xF007)
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{
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case 32768:
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case 32769:
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case 32770:
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case 32771:
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case 32772:
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case 32773:
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case 32774:
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case 32775:
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prg_reg[address & 3] = data & 0x7F;
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SetupPRG();
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break;
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case 36864:
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case 36865:
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case 36866:
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case 36867:
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case 36868:
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case 36869:
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case 36870:
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case 36871:
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chr_reg[address & 7] = (chr_reg[address & 7] & 0xFF00) | data;
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SetupCHR();
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break;
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case 40960:
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case 40961:
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case 40962:
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case 40963:
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case 40964:
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case 40965:
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case 40966:
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case 40967:
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chr_reg[address & 7] = (chr_reg[address & 7] & 0xFF) | (data << 8);
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SetupCHR();
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break;
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case 45056:
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case 45057:
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case 45058:
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case 45059:
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nt_reg[address & 3] = (nt_reg[address & 3] & 0xFF00) | data;
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break;
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case 45060:
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case 45061:
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case 45062:
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case 45063:
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nt_reg[address & 3] = (nt_reg[address & 3] & 0xFF) | (data << 8);
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break;
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case 49152:
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IrqEnable = (data & 1) == 1;
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if (!IrqEnable)
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{
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NesEmu.IRQFlags &= -9;
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}
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break;
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case 49153:
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irqCountDownMode = (data & 0x80) == 128;
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irqCountUpMode = (data & 0x40) == 64;
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irqFunkyMode = (data & 8) == 8;
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irqPrescalerSize = (data & 4) == 4;
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irqSource = data & 3;
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break;
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case 49154:
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IrqEnable = false;
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NesEmu.IRQFlags &= -9;
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break;
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case 49155:
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IrqEnable = true;
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break;
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case 49156:
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irqPrescaler = data ^ irqPrescalerXOR;
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break;
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case 49157:
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irqCounter = data ^ irqPrescalerXOR;
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break;
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case 49158:
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irqPrescalerXOR = data;
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break;
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case 49159:
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irqFunkyModeReg = data;
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break;
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case 53248:
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flag_s = (data & 0x80) == 128;
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prg_mode = data & 7;
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chr_mode = (data >> 3) & 3;
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nt_advanced_enable = (data & 0x20) == 32;
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nt_rom_only = (data & 0x40) == 64;
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SetupPRG();
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SetupCHR();
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break;
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case 53249:
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switch (data & 3)
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{
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case 0:
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Switch01KNMTFromMirroring(Mirroring.Vert);
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break;
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case 1:
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Switch01KNMTFromMirroring(Mirroring.Horz);
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break;
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case 2:
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Switch01KNMTFromMirroring(Mirroring.OneScA);
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break;
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case 3:
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Switch01KNMTFromMirroring(Mirroring.OneScB);
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break;
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}
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break;
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case 53250:
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nt_ram_select = data & 0x80;
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break;
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case 53251:
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chr_m = (data & 0x80) == 128;
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chr_block_mode = (data & 0x20) == 32;
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chr_block = (data & 0x1F) << 8;
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SetupCHR();
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break;
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}
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}
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internal override void WriteSRM(ref ushort address, ref byte data)
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{
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}
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internal override void ReadSRM(ref ushort address, out byte data)
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{
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if (flag_s)
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{
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base.ReadSRM(ref address, out data);
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}
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else
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{
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data = 0;
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}
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}
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internal override void ReadEX(ref ushort address, out byte data)
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{
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switch (address)
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{
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case 20480:
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data = Dipswitch;
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break;
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case 22528:
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data = (byte)(multiplication & 0xFFu);
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break;
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case 22529:
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data = (byte)((multiplication & 0xFF00) >> 8);
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break;
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case 22531:
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data = RAM5803;
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break;
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default:
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data = 0;
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break;
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}
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}
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internal override void WriteEX(ref ushort address, ref byte data)
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{
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switch (address)
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{
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case 22528:
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multiplication_a = data;
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multiplication = (ushort)(multiplication_a * multiplication_b);
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break;
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case 22529:
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multiplication_b = data;
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multiplication = (ushort)(multiplication_a * multiplication_b);
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break;
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case 22531:
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RAM5803 = data;
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break;
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case 22530:
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break;
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}
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}
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internal override void ReadNMT(ref ushort address, out byte data)
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{
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if (MAPPER90MODE)
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{
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data = NMT_RAM[NMT_AREA_BLK_INDEX[(address >> 10) & 3]][address & 0x3FF];
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}
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if (!nt_advanced_enable)
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{
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data = NMT_RAM[NMT_AREA_BLK_INDEX[(address >> 10) & 3]][address & 0x3FF];
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}
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else if (nt_rom_only)
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{
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data = CHR_ROM[nt_reg[(address >> 10) & 3]][address & 0x3FF];
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}
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else if ((nt_reg[(address >> 10) & 3] & 0x80) != nt_ram_select)
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{
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data = CHR_ROM[nt_reg[(address >> 10) & 3]][address & 0x3FF];
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}
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else
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{
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data = NMT_RAM[nt_reg[(address >> 10) & 3] & 1][address & 0x3FF];
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}
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}
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internal override void WriteNMT(ref ushort address, ref byte data)
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{
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if (MAPPER90MODE)
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{
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NMT_RAM[NMT_AREA_BLK_INDEX[(address >> 10) & 3]][address & 0x3FF] = data;
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}
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else if (!nt_advanced_enable)
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{
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NMT_RAM[NMT_AREA_BLK_INDEX[(address >> 10) & 3]][address & 0x3FF] = data;
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}
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else if (!nt_rom_only && (nt_reg[(address >> 10) & 3] & 0x80) == nt_ram_select)
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{
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NMT_RAM[nt_reg[(address >> 10) & 3] & 1][address & 0x3FF] = data;
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}
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}
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private void SetupPRG()
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{
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switch (prg_mode)
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{
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case 0:
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Switch08KPRG(prg_reg[3] * 4 + 3, PRGArea.Area6000);
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Switch32KPRG(PRG_ROM_32KB_Mask, PRGArea.Area8000);
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break;
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case 1:
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Switch08KPRG(prg_reg[3] * 2 + 1, PRGArea.Area6000);
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Switch16KPRG(prg_reg[1], PRGArea.Area8000);
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Switch16KPRG(PRG_ROM_16KB_Mask, PRGArea.AreaC000);
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break;
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case 2:
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Switch08KPRG(prg_reg[3], PRGArea.Area6000);
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Switch08KPRG(prg_reg[0], PRGArea.Area8000);
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Switch08KPRG(prg_reg[1], PRGArea.AreaA000);
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Switch08KPRG(prg_reg[2], PRGArea.AreaC000);
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Switch08KPRG(PRG_ROM_08KB_Mask, PRGArea.AreaE000);
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break;
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case 3:
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Switch08KPRG(ReverseByte(prg_reg[3]), PRGArea.Area6000);
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Switch08KPRG(ReverseByte(prg_reg[0]), PRGArea.Area8000);
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Switch08KPRG(ReverseByte(prg_reg[1]), PRGArea.AreaA000);
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Switch08KPRG(ReverseByte(prg_reg[2]), PRGArea.AreaC000);
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Switch08KPRG(PRG_ROM_16KB_Mask, PRGArea.AreaE000);
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break;
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case 4:
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Switch08KPRG(prg_reg[3] * 4 + 3, PRGArea.Area6000);
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Switch32KPRG(prg_reg[3], PRGArea.Area8000);
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break;
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case 5:
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Switch08KPRG(prg_reg[3] * 2 + 1, PRGArea.Area6000);
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Switch16KPRG(prg_reg[1], PRGArea.Area8000);
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Switch16KPRG(prg_reg[3], PRGArea.AreaC000);
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break;
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case 6:
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Switch08KPRG(prg_reg[3], PRGArea.Area6000);
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Switch08KPRG(prg_reg[0], PRGArea.Area8000);
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Switch08KPRG(prg_reg[1], PRGArea.AreaA000);
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Switch08KPRG(prg_reg[2], PRGArea.AreaC000);
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Switch08KPRG(prg_reg[3], PRGArea.AreaE000);
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break;
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case 7:
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Switch08KPRG(ReverseByte(prg_reg[3]), PRGArea.Area6000);
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Switch08KPRG(ReverseByte(prg_reg[0]), PRGArea.Area8000);
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Switch08KPRG(ReverseByte(prg_reg[1]), PRGArea.AreaA000);
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Switch08KPRG(ReverseByte(prg_reg[2]), PRGArea.AreaC000);
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Switch08KPRG(ReverseByte(prg_reg[3]), PRGArea.AreaE000);
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break;
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}
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}
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private void SetupCHR()
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{
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switch (chr_mode)
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{
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case 0:
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if (chr_block_mode)
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{
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Switch08KCHR(chr_reg[0]);
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}
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else
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{
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Switch08KCHR((chr_reg[0] & 0xFF) | chr_block);
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}
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break;
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case 1:
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if (chr_block_mode)
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{
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Switch04KCHR(chr_reg[0], CHRArea.Area0000);
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Switch04KCHR(chr_reg[4], CHRArea.Area1000);
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}
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else
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{
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Switch04KCHR((chr_reg[0] & 0xFF) | chr_block, CHRArea.Area0000);
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Switch04KCHR((chr_reg[4] & 0xFF) | chr_block, CHRArea.Area1000);
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}
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break;
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case 2:
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if (chr_block_mode)
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{
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Switch02KCHR(chr_reg[0], CHRArea.Area0000);
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Switch02KCHR(chr_m ? chr_reg[0] : chr_reg[2], CHRArea.Area0800);
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Switch02KCHR(chr_reg[4], CHRArea.Area1000);
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Switch02KCHR(chr_reg[6], CHRArea.Area1800);
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}
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else
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{
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Switch02KCHR((chr_reg[0] & 0xFF) | chr_block, CHRArea.Area0000);
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Switch02KCHR(((chr_m ? chr_reg[0] : chr_reg[2]) & 0xFF) | chr_block, CHRArea.Area0800);
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Switch02KCHR((chr_reg[4] & 0xFF) | chr_block, CHRArea.Area1000);
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Switch02KCHR((chr_reg[6] & 0xFF) | chr_block, CHRArea.Area1800);
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}
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break;
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case 3:
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if (chr_block_mode)
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{
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Switch01KCHR(chr_reg[0], CHRArea.Area0000);
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Switch01KCHR(chr_reg[1], CHRArea.Area0400);
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Switch01KCHR(chr_m ? chr_reg[0] : chr_reg[2], CHRArea.Area0800);
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Switch01KCHR(chr_m ? chr_reg[1] : chr_reg[3], CHRArea.Area0C00);
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Switch01KCHR(chr_reg[4], CHRArea.Area1000);
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Switch01KCHR(chr_reg[5], CHRArea.Area1400);
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Switch01KCHR(chr_reg[6], CHRArea.Area1800);
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Switch01KCHR(chr_reg[7], CHRArea.Area1C00);
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}
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else
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{
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Switch01KCHR((chr_reg[0] & 0xFF) | chr_block, CHRArea.Area0000);
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Switch01KCHR((chr_reg[1] & 0xFF) | chr_block, CHRArea.Area0400);
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Switch01KCHR(((chr_m ? chr_reg[0] : chr_reg[2]) & 0xFF) | chr_block, CHRArea.Area0800);
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Switch01KCHR(((chr_m ? chr_reg[1] : chr_reg[3]) & 0xFF) | chr_block, CHRArea.Area0C00);
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Switch01KCHR((chr_reg[4] & 0xFF) | chr_block, CHRArea.Area1000);
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Switch01KCHR((chr_reg[5] & 0xFF) | chr_block, CHRArea.Area1400);
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Switch01KCHR((chr_reg[6] & 0xFF) | chr_block, CHRArea.Area1800);
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Switch01KCHR((chr_reg[7] & 0xFF) | chr_block, CHRArea.Area1C00);
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}
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break;
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}
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}
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private byte ReverseByte(int value)
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{
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return (byte)((uint)(((value & 0x40) >> 6) | ((value & 0x20) >> 4) | ((value & 0x10) >> 2)) | ((uint)value & 8u) | (uint)((value & 4) << 2) | (uint)((value & 2) << 4) | (uint)((value & 1) << 6));
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}
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internal override void OnCPUClock()
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{
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if (irqSource != 0)
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{
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return;
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}
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if (irqPrescalerSize)
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{
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irqPrescaler = (irqPrescaler & 0xF8) | (((irqPrescaler & 7) + 1) & 7);
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if ((irqPrescaler & 7) == 7)
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{
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ClockIRQCounter();
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}
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}
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else
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{
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irqPrescaler++;
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if (irqPrescaler == 255)
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{
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ClockIRQCounter();
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}
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}
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}
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internal override void OnPPUAddressUpdate(ref ushort address)
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{
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if (irqSource != 1)
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{
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return;
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}
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old_vram_address = new_vram_address;
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new_vram_address = address & 0x1000;
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if (old_vram_address >= new_vram_address)
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{
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return;
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}
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if (irqPrescalerSize)
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{
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irqPrescaler = (irqPrescaler & 0xF8) | (((irqPrescaler & 7) + 1) & 7);
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if ((irqPrescaler & 7) == 7)
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{
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ClockIRQCounter();
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}
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}
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else
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{
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irqPrescaler++;
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if (irqPrescaler == 255)
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{
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ClockIRQCounter();
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}
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}
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}
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private void ClockIRQCounter()
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{
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if (irqCountDownMode && irqCountUpMode)
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{
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return;
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}
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if (irqCountDownMode)
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{
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irqCounter--;
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if (irqCounter == 0)
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{
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irqCounter = 255;
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if (IrqEnable)
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{
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NesEmu.IRQFlags |= 8;
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}
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}
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}
|
|
else
|
|
{
|
|
if (!irqCountUpMode)
|
|
{
|
|
return;
|
|
}
|
|
irqCounter++;
|
|
if (irqCounter == 255)
|
|
{
|
|
irqCounter = 0;
|
|
if (IrqEnable)
|
|
{
|
|
NesEmu.IRQFlags |= 8;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
internal override void WriteStateData(ref BinaryWriter stream)
|
|
{
|
|
base.WriteStateData(ref stream);
|
|
for (int i = 0; i < prg_reg.Length; i++)
|
|
{
|
|
stream.Write(prg_reg[i]);
|
|
}
|
|
for (int j = 0; j < chr_reg.Length; j++)
|
|
{
|
|
stream.Write(chr_reg[j]);
|
|
}
|
|
for (int k = 0; k < nt_reg.Length; k++)
|
|
{
|
|
stream.Write(nt_reg[k]);
|
|
}
|
|
stream.Write(prg_mode);
|
|
stream.Write(chr_mode);
|
|
stream.Write(chr_block_mode);
|
|
stream.Write(chr_block);
|
|
stream.Write(chr_m);
|
|
stream.Write(flag_s);
|
|
stream.Write(irqCounter);
|
|
stream.Write(IrqEnable);
|
|
stream.Write(irqCountDownMode);
|
|
stream.Write(irqCountUpMode);
|
|
stream.Write(irqFunkyMode);
|
|
stream.Write(irqPrescalerSize);
|
|
stream.Write(irqSource);
|
|
stream.Write(irqPrescaler);
|
|
stream.Write(irqPrescalerXOR);
|
|
stream.Write(irqFunkyModeReg);
|
|
stream.Write(Dipswitch);
|
|
stream.Write(multiplication_a);
|
|
stream.Write(multiplication_b);
|
|
stream.Write(multiplication);
|
|
stream.Write(RAM5803);
|
|
stream.Write(nt_advanced_enable);
|
|
stream.Write(nt_rom_only);
|
|
stream.Write(nt_ram_select);
|
|
}
|
|
|
|
internal override void ReadStateData(ref BinaryReader stream)
|
|
{
|
|
base.ReadStateData(ref stream);
|
|
for (int i = 0; i < prg_reg.Length; i++)
|
|
{
|
|
prg_reg[i] = stream.ReadInt32();
|
|
}
|
|
for (int j = 0; j < chr_reg.Length; j++)
|
|
{
|
|
chr_reg[j] = stream.ReadInt32();
|
|
}
|
|
for (int k = 0; k < nt_reg.Length; k++)
|
|
{
|
|
nt_reg[k] = stream.ReadInt32();
|
|
}
|
|
prg_mode = stream.ReadInt32();
|
|
chr_mode = stream.ReadInt32();
|
|
chr_block_mode = stream.ReadBoolean();
|
|
chr_block = stream.ReadInt32();
|
|
chr_m = stream.ReadBoolean();
|
|
flag_s = stream.ReadBoolean();
|
|
irqCounter = stream.ReadInt32();
|
|
IrqEnable = stream.ReadBoolean();
|
|
irqCountDownMode = stream.ReadBoolean();
|
|
irqCountUpMode = stream.ReadBoolean();
|
|
irqFunkyMode = stream.ReadBoolean();
|
|
irqPrescalerSize = stream.ReadBoolean();
|
|
irqSource = stream.ReadInt32();
|
|
irqPrescaler = stream.ReadInt32();
|
|
irqPrescalerXOR = stream.ReadInt32();
|
|
irqFunkyModeReg = stream.ReadByte();
|
|
Dipswitch = stream.ReadByte();
|
|
multiplication_a = stream.ReadByte();
|
|
multiplication_b = stream.ReadByte();
|
|
multiplication = stream.ReadUInt16();
|
|
RAM5803 = stream.ReadByte();
|
|
nt_advanced_enable = stream.ReadBoolean();
|
|
nt_rom_only = stream.ReadBoolean();
|
|
nt_ram_select = stream.ReadInt32();
|
|
}
|
|
}
|
|
}
|