137 lines
4.1 KiB
C++
137 lines
4.1 KiB
C++
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class Mapper172 : public Mapper
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{
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public:
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Mapper172( NES* parent ) : Mapper(parent) {}
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void Reset();
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BYTE ReadLow( WORD addr );
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void WriteLow(WORD addr, BYTE data);
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BOOL ReadHigh( WORD addr, LPBYTE pdata );
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void Write( WORD addr, BYTE data );
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void Clock( INT cycles );
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void PPU_Latch( WORD addr );
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//for FDC code by fanoble
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void FdcHardReset(void);
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void FdcSoftReset(void);
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static void FdcNop(Mapper172* thiz);
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static void FdcReadTrack(Mapper172* thiz);
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static void FdcSpecify(Mapper172* thiz);
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static void FdcSenseDriveStatus(Mapper172* thiz);
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static void FdcWriteData(Mapper172* thiz);
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static void FdcReadData(Mapper172* thiz);
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static void FdcRecalibrate(Mapper172* thiz);
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static void FdcSenseIntStatus(Mapper172* thiz);
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static void FdcWriteDeletedData(Mapper172* thiz);
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static void FdcReadID(Mapper172* thiz);
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static void FdcReadDeletedData(Mapper172* thiz);
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static void FdcFormatTrack(Mapper172* thiz);
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static void FdcSeek(Mapper172* thiz);
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static void FdcScanEqual(Mapper172* thiz);
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static void FdcScanLowOrEqual(Mapper172* thiz);
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static void FdcScanHighOrEqual(Mapper172* thiz);
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typedef struct tagFDC_CMD_DESC
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{
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BYTE bWLength;
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BYTE bRLength;
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void (*pFun)(Mapper172*);
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} FDC_CMD_DESC;
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protected:
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BYTE reg[10];
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BYTE WE_SRAM, WE_DRAM, RE_DRAM;
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BYTE irq_enable;
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WORD irq_counter;
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INT read_mode,read_mode1,write_mode,write_mode1;
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private:
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LPBYTE Load_DiskIMG();
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LPBYTE lpDisk, DISK;
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//for FDC code by fanoble
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#define FDC_MS_BUSYS0 0x01 // FDD0 in SEEK mode
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#define FDC_MS_BUSYS1 0x02 // FDD1 in SEEK mode
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#define FDC_MS_BUSYS2 0x04 // FDD2 in SEEK mode
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#define FDC_MS_BUSYS3 0x08 // FDD3 in SEEK mode
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#define FDC_MS_BUSYRW 0x10 // Read or Write in progress
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#define FDC_MS_EXECUTION 0x20 // Execution Mode
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#define FDC_MS_DATA_IN 0x40 // Data input or output
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#define FDC_MS_RQM 0x80 // Request for Master, Ready
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#define FDC_S0_US0 0x01 // Unit Select 0
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#define FDC_S0_US1 0x02 // Unit Select 1
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#define FDC_S0_HD 0x04 // Head Address
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#define FDC_S0_NR 0x08 // Not Ready
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#define FDC_S0_EC 0x10 // Equipment Check
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#define FDC_S0_SE 0x20 // Seek End
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#define FDC_S0_IC0 0x40 // Interrupt Code
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#define FDC_S0_IC1 0x80 // NT/AT/IC/XX
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#define FDC_S1_MA 0x01 // Missing Address Mark
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#define FDC_S1_NW 0x02 // Not Writable
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#define FDC_S1_ND 0x04 // No Data
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#define FDC_S1_OR 0x10 // Over Run
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#define FDC_S1_DE 0x20 // Data Error
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#define FDC_S1_EN 0x80 // End of Cylinder
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#define FDC_S2_MD 0x01 // Missing Address Mark in Data Field
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#define FDC_S2_BC 0x02 // Bad Cylinder
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#define FDC_S2_SN 0x04 // Scan Not Satisfied
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#define FDC_S2_SH 0x08 // Scan Equal Hit
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#define FDC_S2_WC 0x10 // Wrong Cylinder
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#define FDC_S2_DD 0x20 // Data Error in Data Field
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#define FDC_S2_CM 0x40 // Control Mark
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#define FDC_S3_US0 0x01 // Unit Select 0
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#define FDC_S3_US1 0x02 // Unit Select 1
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#define FDC_S3_HD 0x04 // Side Select
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#define FDC_S3_TS 0x08 // Two Side
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#define FDC_S3_T0 0x10 // Track 0
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#define FDC_S3_RY 0x20 // Ready
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#define FDC_S3_WP 0x40 // Write Protect
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#define FDC_S3_FT 0x80 // Fault
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#define FDC_CC_MASK 0x1F
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#define FDC_CF_MT 0x80
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#define FDC_CF_MF 0x40
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#define FDC_CF_SK 0x20
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#define FDC_CC_READ_TRACK 0x02
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#define FDC_CC_SPECIFY 0x03
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#define FDC_CC_SENSE_DRIVE_STATUS 0x04
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#define FDC_CC_WRITE_DATA 0x05
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#define FDC_CC_READ_DATA 0x06
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#define FDC_CC_RECALIBRATE 0x07
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#define FDC_CC_SENSE_INTERRUPT_STATUS 0x08
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#define FDC_CC_WRITE_DELETED_DATA 0x09
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#define FDC_CC_READ_ID 0x0A
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#define FDC_CC_READ_DELETED_DATA 0x0C
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#define FDC_CC_FORMAT_TRACK 0x0D
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#define FDC_CC_SEEK 0x0F
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#define FDC_CC_SCAN_EQUAL 0x11
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#define FDC_CC_SCAN_LOW_OR_EQUAL 0x19
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#define FDC_CC_SCAN_HIGH_OR_EQUAL 0x1D
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#define FDC_PH_IDLE 0
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#define FDC_PH_COMMAND 1
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#define FDC_PH_EXECUTION 2
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#define FDC_PH_RESULT 3
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const FDC_CMD_DESC* pFdcCmd;
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BOOL bFdcIrq;
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BOOL bFdcHwReset;
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BOOL bFdcSoftReset;
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BOOL bFdcDmaInt;
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UINT nFdcDrvSel;
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UINT nFdcMotor;
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BYTE nFdcMainStatus;
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BYTE nFDCStatus[4];
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BYTE bFdcCycle;
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BYTE bFdcCommands[10];
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BYTE bFdcResults[8];
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BYTE bFdcPhase;
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BYTE nFdcCylinder;
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BYTE nFdcHeadAddres;
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BYTE nFdcRecord;
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BYTE nFdcNumber;
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LPBYTE pFdcDataPtr;
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};
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