566 lines
11 KiB
C++
566 lines
11 KiB
C++
//////////////////////////////////////////////////////////////////////////
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// Mapper116 CartSaint : —H—VAV‹—ñ“` //
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//////////////////////////////////////////////////////////////////////////
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void Mapper116::Reset()
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{
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/*
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for( INT i = 0; i < 8; i++ ) {
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reg[i] = 0x00;
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}
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prg0 = prg0L = 0;
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prg1 = prg1L = 1;
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prg2 = PROM_8K_SIZE-2;
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prg3 = PROM_8K_SIZE-1;
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ExPrgSwitch = 0;
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ExChrSwitch = 0;
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SetBank_CPU();
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if( VROM_1K_SIZE ) {
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chr0 = 0;
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chr1 = 1;
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chr2 = 2;
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chr3 = 3;
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chr4 = 4;
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chr5 = 5;
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chr6 = 6;
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chr7 = 7;
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SetBank_PPU();
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} else {
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chr0 = chr2 = chr4 = chr5 = chr6 = chr7 = 0;
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chr1 = chr3 = 1;
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}
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irq_enable = 0; // Disable
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irq_counter = 0;
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irq_latch = 0;
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// nes->SetFrameIRQmode( FALSE );
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*/
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mode = 0;
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vrc2_chr[0] = 0;
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vrc2_chr[1] = 1;
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vrc2_chr[2] = 2;
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vrc2_chr[3] = 3;
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vrc2_chr[4] = 4;
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vrc2_chr[5] = 5;
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vrc2_chr[6] = 6;
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vrc2_chr[7] = 7;
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vrc2_prg[0] = 0;
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vrc2_prg[1] = 1;
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vrc2_mirr = 0;
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mmc3_regs[0] = 0;
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mmc3_regs[1] = 2;
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mmc3_regs[2] = 4;
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mmc3_regs[3] = 5;
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mmc3_regs[4] = 6;
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mmc3_regs[5] = 7;
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mmc3_regs[6] = 0x3C;
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mmc3_regs[7] = 0x3D;
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mmc3_regs[8] = 0xFE;
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mmc3_regs[9] = 0xFF;
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mmc3_ctrl = mmc3_mirr = 0;
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IRQCount = IRQLatch = IRQa = 0;
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mmc1_regs[0] = 0xc;
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mmc1_regs[1] = 0;
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mmc1_regs[2] = 0;
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mmc1_regs[3] = 0;
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mmc1_buffer = 0;
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mmc1_shift = 0;
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SetBank_CPU();
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SetBank_PPU();
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SetBank_MIR();
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}
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void Mapper116::WriteLow( WORD addr, BYTE data )
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{
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DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes->GetScanline(), nes->cpu->GetTotalCycles() );
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/*
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if( (addr & 0x4100) == 0x4100 ) {
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ExChrSwitch = data;
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SetBank_PPU();
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}
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*/
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if ((addr&0x4100)==0x4100) {
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mode = data;
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if (addr&1) {
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mmc1_regs[0] = 0xc;
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mmc1_regs[3] = 0;
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mmc1_buffer = 0;
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mmc1_shift = 0;
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}
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// if ((data&0x3)!=1)
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// {
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// IRQCount = IRQLatch;
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// IRQa = 0;
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// nes->cpu->ClrIRQ( IRQ_MAPPER );
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// }
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SetBank_CPU();
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SetBank_PPU();
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SetBank_MIR();
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}
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}
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void Mapper116::Write( WORD addr, BYTE data )
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{
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DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes->GetScanline(), nes->cpu->GetTotalCycles() );
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/*
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switch( addr & 0xE001 ) {
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case 0x8000:
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reg[0] = data;
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SetBank_CPU();
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SetBank_PPU();
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break;
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case 0x8001:
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reg[1] = data;
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switch( reg[0] & 0x07 ) {
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case 0x00:
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chr0 = data & 0xFE;
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chr1 = chr0+1;
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SetBank_PPU();
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break;
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case 0x01:
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chr2 = data & 0xFE;
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chr3 = chr2+1;
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SetBank_PPU();
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break;
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case 0x02:
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chr4 = data;
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SetBank_PPU();
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break;
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case 0x03:
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chr5 = data;
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SetBank_PPU();
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break;
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case 0x04:
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chr6 = data;
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SetBank_PPU();
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break;
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case 0x05:
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chr7 = data;
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SetBank_PPU();
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break;
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case 0x06:
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prg0 = data;
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SetBank_CPU();
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break;
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case 0x07:
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prg1 = data;
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SetBank_CPU();
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break;
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}
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break;
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case 0xA000:
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reg[2] = data;
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if( !nes->rom->Is4SCREEN() ) {
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if( data & 0x01 ) SetVRAM_Mirror( VRAM_HMIRROR );
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else SetVRAM_Mirror( VRAM_VMIRROR );
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}
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break;
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case 0xA001:
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reg[3] = data;
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break;
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case 0xC000:
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reg[4] = data;
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irq_counter = data;
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// irq_enable = 0xFF;
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break;
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case 0xC001:
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reg[5] = data;
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irq_latch = data;
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break;
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case 0xE000:
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reg[6] = data;
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irq_counter = irq_latch;
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irq_enable = 0;
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nes->cpu->ClrIRQ( IRQ_MAPPER );
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break;
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case 0xE001:
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reg[7] = data;
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irq_enable = 0xFF;
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break;
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}
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*/
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switch (mode & 3) {
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case 0: {
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if ((addr >= 0xB000) && (addr <= 0xE003)) {
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int32 ind = ((((addr & 2) | (addr >> 10)) >> 1) + 2) & 7;
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int32 sar = ((addr & 1) << 2);
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vrc2_chr[ind] = (vrc2_chr[ind] & (0xF0 >> sar)) | ((data & 0x0F) << sar);
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SetBank_PPU();
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} else
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switch (addr & 0xF000) {
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case 0x8000: vrc2_prg[0] = data; SetBank_CPU(); break;
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case 0xA000: vrc2_prg[1] = data; SetBank_CPU(); break;
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case 0x9000: vrc2_mirr = data; SetBank_MIR(); break;
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}
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break;
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}
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case 1: {
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switch (addr & 0xE001) {
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case 0x8000:
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// uint8 old_ctrl = mmc3_ctrl;
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// mmc3_ctrl = data;
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// if ((old_ctrl & 0x40) != (mmc3_ctrl & 0x40))
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// SetBank_CPU();
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// if ((old_ctrl & 0x80) != (mmc3_ctrl & 0x80))
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// SetBank_PPU();
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addr = mmc3_ctrl ^ data;
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mmc3_ctrl = data;
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if (addr & 0x40)
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SetBank_CPU();
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if (addr & (0x80|0x07))
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SetBank_PPU();
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break;
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case 0x8001:
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// mmc3_regs[mmc3_ctrl & 7] = data;
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// if ((mmc3_ctrl & 7) < 6)
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// SetBank_PPU();
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// else
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// SetBank_CPU();
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addr = mmc3_ctrl & 0x7;
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if (addr<2) data>>= 1;
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if (mmc3_regs[addr] != data)
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{
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mmc3_regs[addr] = data;
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if (addr<6)
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SetBank_PPU();
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else
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SetBank_CPU();
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}
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break;
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case 0xA000:
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mmc3_mirr = data;
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SetBank_MIR();
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break;
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case 0xC000:
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IRQCount = data;
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break;
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case 0xC001:
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IRQLatch = data;
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break;
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case 0xE000:
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IRQCount = IRQLatch;
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IRQa = 0;
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nes->cpu->ClrIRQ( IRQ_MAPPER );
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break;
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case 0xE001:
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IRQa = 0xFF;
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break;
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}
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break;
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}
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case 2:
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case 3: {
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if (data & 0x80) {
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mmc1_regs[0] |= 0xc;
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mmc1_buffer = mmc1_shift = 0;
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SetBank_CPU();
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} else {
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uint8 n = (addr >> 13) - 4;
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mmc1_buffer |= (data & 1) << (mmc1_shift++);
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if (mmc1_shift == 5) {
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mmc1_regs[n] = mmc1_buffer;
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mmc1_buffer = mmc1_shift = 0;
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switch (n) {
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case 0: SetBank_MIR();
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case 2: SetBank_PPU();
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case 3:
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case 1: SetBank_CPU();
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}
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}
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}
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break;
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}
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}
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}
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void Mapper116::HSync( INT scanline )
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{
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/*
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if( (scanline >= 0 && scanline <= 239) ) {
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if ((mode & 3) == 1) {
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int32 count = IRQCount;
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if (!count || IRQReload) {
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IRQCount = IRQLatch;
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IRQReload = 0;
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} else
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IRQCount--;
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if (!IRQCount) {
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if (IRQa)
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nes->cpu->SetIRQ( IRQ_MAPPER );
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}
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}
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}
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*/
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if( (scanline >= 0 && scanline <= 239) ) {
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if( IRQCount <= 0 ) {
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if( IRQa ) {
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nes->cpu->SetIRQ( IRQ_MAPPER );
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return;
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}
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}
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if(nes->ppu->IsDispON() ) {
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IRQCount--;
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}
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}
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}
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/*
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void Mapper116::HSync( INT scanline )
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{
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if( (scanline >= 0 && scanline <= 239) ) {
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if( irq_counter <= 0 ) {
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if( irq_enable ) {
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// nes->cpu->IRQ_NotPending();
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nes->cpu->SetIRQ( IRQ_MAPPER );
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#if 0
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DEBUGOUT( "IRQ L=%3d\n", scanline );
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{
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LPBYTE lpScn = nes->ppu->GetScreenPtr();
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lpScn = lpScn+(256+16)*scanline;
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for( INT i = 0; i < 64; i++ ) {
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lpScn[i] = 22;
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}
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}
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#endif
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return;
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}
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}
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if( nes->ppu->IsDispON() ) {
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irq_counter--;
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}
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}
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#if 0
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if( (scanline >= 0 && scanline <= 239) ) {
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if( nes->ppu->IsDispON() ) {
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if( irq_enable ) {
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if( !(irq_counter--) ) {
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// irq_counter = irq_latch;
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nes->cpu->IRQ_NotPending();
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}
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}
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}
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}
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#endif
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}
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void Mapper116::SetBank_CPU()
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{
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if( reg[0] & 0x40 ) {
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SetPROM_32K_Bank( PROM_8K_SIZE-2, prg1, prg0, PROM_8K_SIZE-1 );
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} else {
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SetPROM_32K_Bank( prg0, prg1, PROM_8K_SIZE-2, PROM_8K_SIZE-1 );
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}
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}
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void Mapper116::SetBank_PPU()
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{
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if( VROM_1K_SIZE ) {
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if( ExChrSwitch & 0x04 ) {
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INT chrbank = 256;
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SetVROM_8K_Bank( chrbank+chr4, chrbank+chr5,
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chrbank+chr6, chrbank+chr7,
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chr0, chr1,
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chr2, chr3 );
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} else {
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INT chrbank = 0;
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SetVROM_8K_Bank( chrbank+chr4, chrbank+chr5,
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chrbank+chr6, chrbank+chr7,
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chr0, chr1,
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chr2, chr3 );
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}
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#if 0
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if( reg[0] & 0x80 ) {
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// SetVROM_8K_Bank( chrbank+chr4, chrbank+chr5,
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// chrbank+chr6, chrbank+chr7,
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// chrbank+chr0, chrbank+chr1,
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// chrbank+chr2, chrbank+chr3 );
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SetVROM_8K_Bank( chrbank+chr4, chrbank+chr5,
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chrbank+chr6, chrbank+chr7,
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chr0, chr1,
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chr2, chr3 );
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} else {
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SetVROM_8K_Bank( chr0, chr1,
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chr2, chr3,
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chrbank+chr4, chrbank+chr5,
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chrbank+chr6, chrbank+chr7 );
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}
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#endif
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}
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}
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*/
|
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|
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void Mapper116::SetBank_CPU()
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{
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switch (mode & 3) {
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case 0:
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SetPROM_8K_Bank(4, vrc2_prg[0]);
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SetPROM_8K_Bank(5, vrc2_prg[1]);
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SetPROM_8K_Bank(6, 0x1E);
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SetPROM_8K_Bank(7, 0x1F);
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break;
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case 1:
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{
|
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uint32 swap = (mmc3_ctrl >> 5) & 2;
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SetPROM_8K_Bank(4, mmc3_regs[6 + swap]);
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SetPROM_8K_Bank(5, mmc3_regs[7]);
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SetPROM_8K_Bank(6, mmc3_regs[6 + (swap^2)]);
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SetPROM_8K_Bank(7, mmc3_regs[9]);
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break;
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}
|
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case 2:
|
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case 3:
|
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{
|
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uint8 bank = mmc1_regs[3] & 0xF;
|
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if (mmc1_regs[0] & 8) {
|
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if (mmc1_regs[0] & 4) {
|
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SetPROM_16K_Bank(4, bank);
|
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SetPROM_16K_Bank(6, 0x0F);
|
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} else {
|
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SetPROM_16K_Bank(4, 0);
|
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SetPROM_16K_Bank(6, bank);
|
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}
|
||
} else
|
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SetPROM_32K_Bank(bank>>1);
|
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break;
|
||
}
|
||
}
|
||
}
|
||
void Mapper116::SetBank_PPU()
|
||
{
|
||
uint32 base = (mode & 4) << 6;
|
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switch (mode & 3) {
|
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case 0:
|
||
SetVROM_1K_Bank(0, base | vrc2_chr[0]);
|
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SetVROM_1K_Bank(1, base | vrc2_chr[1]);
|
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SetVROM_1K_Bank(2, base | vrc2_chr[2]);
|
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SetVROM_1K_Bank(3, base | vrc2_chr[3]);
|
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SetVROM_1K_Bank(4, base | vrc2_chr[4]);
|
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SetVROM_1K_Bank(5, base | vrc2_chr[5]);
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SetVROM_1K_Bank(6, base | vrc2_chr[6]);
|
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SetVROM_1K_Bank(7, base | vrc2_chr[7]);
|
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break;
|
||
case 1: {
|
||
uint32 swap = (mmc3_ctrl & 0x80) << 5;
|
||
// SetVROM_1K_Bank(((0x0000^swap)/0x400)+0, base | ((mmc3_regs[0]) & 0xFE));
|
||
// SetVROM_1K_Bank(((0x0400^swap)/0x400)+1, base | (mmc3_regs[0] | 1));
|
||
// SetVROM_1K_Bank(((0x0800^swap)/0x400)+2, base | ((mmc3_regs[1]) & 0xFE));
|
||
// SetVROM_1K_Bank(((0x0c00^swap)/0x400)+3, base | (mmc3_regs[1] | 1));
|
||
// SetVROM_1K_Bank(((0x1000^swap)/0x400)+4, base | mmc3_regs[2]);
|
||
// SetVROM_1K_Bank(((0x1400^swap)/0x400)+5, base | mmc3_regs[3]);
|
||
// SetVROM_1K_Bank(((0x1800^swap)/0x400)+6, base | mmc3_regs[4]);
|
||
// SetVROM_1K_Bank(((0x1c00^swap)/0x400)+7, base | mmc3_regs[5]);
|
||
SetVROM_2K_Bank(((0x0000^swap)>>10)+0,base >> 1 | mmc3_regs[0]);
|
||
SetVROM_2K_Bank(((0x0000^swap)>>10)+2,base >> 1 | mmc3_regs[1]);
|
||
SetVROM_1K_Bank(((0x1000^swap)>>10)+0,base|mmc3_regs[2]);
|
||
SetVROM_1K_Bank(((0x1000^swap)>>10)+1,base|mmc3_regs[3]);
|
||
SetVROM_1K_Bank(((0x1000^swap)>>10)+2,base|mmc3_regs[4]);
|
||
SetVROM_1K_Bank(((0x1000^swap)>>10)+3,base|mmc3_regs[5]);
|
||
break;
|
||
}
|
||
case 2:
|
||
case 3:
|
||
if (mmc1_regs[0] & 0x10) {
|
||
SetVROM_4K_Bank(0, mmc1_regs[1]);
|
||
SetVROM_4K_Bank(4, mmc1_regs[2]);
|
||
} else
|
||
SetVROM_8K_Bank(mmc1_regs[1] >> 1);
|
||
break;
|
||
}
|
||
}
|
||
void Mapper116::SetBank_MIR()
|
||
{
|
||
switch (mode & 3) {
|
||
case 0: {
|
||
if(vrc2_mirr&0x01) SetVRAM_Mirror( VRAM_HMIRROR );
|
||
else SetVRAM_Mirror( VRAM_VMIRROR );
|
||
break;
|
||
break;
|
||
}
|
||
case 1: {
|
||
if(mmc3_mirr&0x01) SetVRAM_Mirror( VRAM_HMIRROR );
|
||
else SetVRAM_Mirror( VRAM_VMIRROR );
|
||
break;
|
||
}
|
||
case 2:
|
||
case 3: {
|
||
switch (mmc1_regs[0] & 3) {
|
||
case 0: SetVRAM_Mirror( VRAM_MIRROR4L ); break;
|
||
case 1: SetVRAM_Mirror( VRAM_MIRROR4H ); break;
|
||
case 2: SetVRAM_Mirror( VRAM_VMIRROR ); break;
|
||
case 3: SetVRAM_Mirror( VRAM_HMIRROR ); break;
|
||
}
|
||
break;
|
||
}
|
||
}
|
||
}
|
||
|
||
void Mapper116::SaveState( LPBYTE p )
|
||
{
|
||
for( INT i = 0; i < 8; i++ ) {
|
||
p[i] = reg[i];
|
||
}
|
||
p[ 8] = prg0;
|
||
p[ 9] = prg1;
|
||
p[10] = prg2;
|
||
p[11] = prg3;
|
||
p[12] = chr0;
|
||
p[13] = chr1;
|
||
p[14] = chr2;
|
||
p[15] = chr3;
|
||
p[16] = chr4;
|
||
p[17] = chr5;
|
||
p[18] = chr6;
|
||
p[19] = chr7;
|
||
p[20] = irq_enable;
|
||
p[21] = irq_counter;
|
||
p[22] = irq_latch;
|
||
p[23] = ExPrgSwitch;
|
||
p[24] = prg0L;
|
||
p[25] = prg1L;
|
||
p[26] = ExChrSwitch;
|
||
}
|
||
|
||
void Mapper116::LoadState( LPBYTE p )
|
||
{
|
||
for( INT i = 0; i < 8; i++ ) {
|
||
reg[i] = p[i];
|
||
}
|
||
prg0 = p[ 8];
|
||
prg1 = p[ 9];
|
||
prg2 = p[10];
|
||
prg3 = p[11];
|
||
chr0 = p[12];
|
||
chr1 = p[13];
|
||
chr2 = p[14];
|
||
chr3 = p[15];
|
||
chr4 = p[16];
|
||
chr5 = p[17];
|
||
chr6 = p[18];
|
||
chr7 = p[19];
|
||
irq_enable = p[20];
|
||
irq_counter = p[21];
|
||
irq_latch = p[22];
|
||
ExPrgSwitch = p[23];
|
||
prg0L = p[24];
|
||
prg1L = p[25];
|
||
ExChrSwitch = p[26];
|
||
}
|