319 lines
10 KiB
C#
319 lines
10 KiB
C#
//////////////////////////////////////////////////////////////////////////
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// Mapper199 WaiXingTypeG Base ON Nintendo MMC3 //
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//////////////////////////////////////////////////////////////////////////
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using static VirtualNes.MMU;
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using static VirtualNes.Core.CPU;
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using INT = System.Int32;
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using BYTE = System.Byte;
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using System;
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using Codice.CM.Client.Differences;
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namespace VirtualNes.Core
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{
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public class Mapper199 : Mapper
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{
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BYTE[] reg = new byte[8];
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BYTE[] prg = new byte[4];
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BYTE[] chr = new byte[8];
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BYTE we_sram;
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BYTE JMaddr;
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BYTE[] JMaddrDAT = new BYTE[3];
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BYTE irq_enable;
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BYTE irq_counter;
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BYTE irq_latch;
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BYTE irq_request;
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public Mapper199(NES parent) : base(parent)
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{
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}
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public override void Reset()
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{
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for (byte i = 0; i < 8; i++)
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{
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reg[i] = 0x00;
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chr[i] = i;
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}
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prg[0] = 0x00;
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prg[1] = 0x01;
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prg[2] = (byte)(PROM_8K_SIZE - 2);
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prg[3] = (byte)(PROM_8K_SIZE - 1);
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SetBank_CPU();
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SetBank_PPU();
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irq_enable = irq_counter = irq_latch = irq_request = 0;
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JMaddr = 0;
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JMaddrDAT[0] = JMaddrDAT[1] = JMaddrDAT[2] = 0;
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we_sram = 0;
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nes.SetSAVERAM_SIZE(32 * 1024);
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nes.SetVideoMode(true);
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}
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//BYTE Mapper199::ReadLow(WORD addr)
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public override byte ReadLow(ushort addr)
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{
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if (addr >= 0x5000 && addr <= 0x5FFF)
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{
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return XRAM[addr - 0x4000];
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}
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else if (addr >= 0x6000 && addr <= 0x7FFF)
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{
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if (JMaddr != 0)
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{
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switch (addr)
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{
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case 0x6000: return JMaddrDAT[0];
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case 0x6010: return JMaddrDAT[1];
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case 0x6013: JMaddr = 0; return JMaddrDAT[2];
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}
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}
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switch (we_sram)
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{
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case 0xE4:
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case 0xEC: return WRAM[(addr & 0x1FFF) + 0x0000];
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case 0xE5:
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case 0xED: return WRAM[(addr & 0x1FFF) + 0x2000];
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case 0xE6:
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case 0xEE: return WRAM[(addr & 0x1FFF) + 0x4000];
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case 0xE7:
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case 0xEF: return WRAM[(addr & 0x1FFF) + 0x6000];
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default: return CPU_MEM_BANK[addr >> 13][addr & 0x1FFF];
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}
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}
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else
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{
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return base.ReadLow(addr);
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}
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}
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//void Mapper199::WriteLow(WORD addr, BYTE data)
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public override void WriteLow(ushort addr, byte data)
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{
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if (addr >= 0x5000 && addr <= 0x5FFF)
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{
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XRAM[addr - 0x4000] = data;
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if ((we_sram == 0xA1) || (we_sram == 0xA5) || (we_sram == 0xA9))
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{
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JMaddr = 1;
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switch (addr)
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{
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case 0x5000: JMaddrDAT[0] = data; break;
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case 0x5010: JMaddrDAT[1] = data; break;
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case 0x5013: JMaddrDAT[2] = data; break;
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}
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}
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}
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else if (addr >= 0x6000 && addr <= 0x7FFF)
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{
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switch (we_sram)
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{
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case 0xE4: //CPU_MEM_BANK
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case 0xEC: //CPU_MEM_BANK
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WRAM[(addr & 0x1FFF) + 0x0000] = data;
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CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
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break;
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case 0xE5: //SRAM
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case 0xED: //SRAM
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WRAM[(addr & 0x1FFF) + 0x2000] = data;
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break;
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case 0xE6:
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case 0xEE:
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WRAM[(addr & 0x1FFF) + 0x4000] = data;
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break;
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case 0xE7:
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case 0xEF:
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WRAM[(addr & 0x1FFF) + 0x6000] = data;
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break;
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default:
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CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
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break;
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}
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}
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else
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{
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base.WriteLow(addr, data);
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}
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}
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//void Mapper199::Write(WORD addr, BYTE data)
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public override void Write(ushort addr, byte data)
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{
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switch (addr & 0xE001)
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{
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case 0x8000:
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reg[0] = data;
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SetBank_CPU();
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SetBank_PPU();
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break;
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case 0x8001:
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reg[1] = data;
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switch (reg[0] & 0x0f)
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{
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case 0x00: chr[0] = data; SetBank_PPU(); break;
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case 0x01: chr[2] = data; SetBank_PPU(); break;
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case 0x02:
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case 0x03:
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case 0x04:
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case 0x05: chr[(reg[0] & 0x07) + 2] = data; SetBank_PPU(); break;
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case 0x06:
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case 0x07:
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case 0x08:
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case 0x09: prg[(reg[0] & 0x0f) - 6] = data; SetBank_CPU(); break;
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case 0x0A: chr[1] = data; SetBank_PPU(); break;
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case 0x0B: chr[3] = data; SetBank_PPU(); break;
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}
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break;
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case 0xA000:
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reg[2] = data;
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data &= 0x03;
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if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
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else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
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else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L);
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else SetVRAM_Mirror(VRAM_MIRROR4H);
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break;
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case 0xA001:
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// DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes->GetScanline(), nes->cpu->GetTotalCycles() );
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reg[3] = data;
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we_sram = data;
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break;
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case 0xC000:
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reg[4] = data;
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irq_counter = data;
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irq_request = 0;
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break;
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case 0xC001:
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reg[5] = data;
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irq_latch = data;
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irq_request = 0;
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break;
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case 0xE000:
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reg[6] = data;
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irq_enable = 0;
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irq_request = 0;
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nes.cpu.ClrIRQ(IRQ_MAPPER);
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break;
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case 0xE001:
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reg[7] = data;
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irq_enable = 1;
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irq_request = 0;
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break;
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}
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}
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//void Mapper199::HSync(INT scanline)
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public override void HSync(int scanline)
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{
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if ((scanline >= 0 && scanline <= 239))
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{
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if (nes.ppu.IsDispON())
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{
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if (irq_enable != 0 && irq_request == 0)
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{
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if (scanline == 0)
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{
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if (irq_counter != 0)
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{
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irq_counter -= 1;
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}
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}
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if (irq_counter == 0)
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{
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irq_request = 0xFF;
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irq_counter = irq_latch;
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nes.cpu.SetIRQ(IRQ_MAPPER);
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}
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irq_counter--;
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}
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}
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}
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}
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void SetBank_CPU()
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{
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SetPROM_8K_Bank(4, prg[0 ^ (reg[0] >> 5 & ~(0 << 1) & 2)]);
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SetPROM_8K_Bank(5, prg[1 ^ (reg[0] >> 5 & ~(1 << 1) & 2)]);
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SetPROM_8K_Bank(6, prg[2 ^ (reg[0] >> 5 & ~(2 << 1) & 2)]);
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SetPROM_8K_Bank(7, prg[3 ^ (reg[0] >> 5 & ~(3 << 1) & 2)]);
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}
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void SetBank_PPU()
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{
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uint bank = (uint)((reg[0] & 0x80) >> 5);
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for (int x = 0; x < 8; x++)
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{
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if (chr[x] <= 7)
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SetCRAM_1K_Bank((byte)(x ^ bank), chr[x]);
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else
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SetVROM_1K_Bank((byte)(x ^ bank), chr[x]);
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}
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}
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//void Mapper199::SaveState(LPBYTE p)
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public override void SaveState(byte[] p)
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{
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//for (INT i = 0; i < 8; i++)
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//{
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// p[i] = reg[i];
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//}
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//for (i = 8; i < 12; i++)
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//{
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// p[i] = prg[i];
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//}
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//for (i = 8; i < 20; i++)
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//{
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// p[i] = chr[i];
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//}
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//p[20] = we_sram;
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//p[21] = JMaddr;
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//p[22] = JMaddrDAT[0];
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//p[23] = JMaddrDAT[1];
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//p[24] = JMaddrDAT[2];
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//p[25] = irq_enable;
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//p[26] = irq_counter;
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//p[27] = irq_latch;
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//p[28] = irq_request;
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}
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//void Mapper199::LoadState(LPBYTE p)
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public override void LoadState(byte[] p)
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{
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//for (INT i = 0; i < 8; i++)
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//{
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// reg[i] = p[i];
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//}
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//for (i = 8; i < 12; i++)
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//{
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// prg[i] = p[i];
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//}
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//for (i = 8; i < 20; i++)
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//{
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// chr[i] = p[i];
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//}
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//we_sram = p[20];
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//JMaddr = p[21];
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//JMaddrDAT[0] = p[22];
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//JMaddrDAT[1] = p[23];
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//JMaddrDAT[2] = p[24];
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//irq_enable = p[25];
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//irq_counter = p[26];
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//irq_latch = p[27];
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//irq_request = p[28];
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}
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public override bool IsStateSave()
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{
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return true;
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}
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}
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}
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