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MAME: MV68000.MOVE命令优化

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sin365 2025-11-17 18:12:22 +08:00
parent c1ad639f7a
commit a806deed55
6 changed files with 541 additions and 103 deletions
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31
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/DataMovement.cs
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@ -530,14 +530,41 @@ namespace cpu.m68000
} }
//void PEA()
//{
// int mode = (op >> 3) & 7;
// int reg = (op >> 0) & 7;
// int ea = ReadAddress(mode, reg);
// ptrA7->s32 -= 4;
// WriteLong(ptrA7->s32, ea);
// switch (mode)
// {
// case 2: pendingCycles -= 12; break;
// case 5: pendingCycles -= 16; break;
// case 6: pendingCycles -= 20; break;
// case 7:
// switch (reg)
// {
// case 0: pendingCycles -= 16; break;
// case 1: pendingCycles -= 20; break;
// case 2: pendingCycles -= 16; break;
// case 3: pendingCycles -= 20; break;
// }
// break;
// }
//}
void PEA() void PEA()
{ {
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
int ea = ReadAddress(mode, reg); int ea = ReadAddress(mode, reg);
A[7].s32 -= 4; Register* ptrA7 = &A[7];
WriteLong(A[7].s32, ea); ptrA7->s32 -= 4;
WriteLong(ptrA7->s32, ea);
switch (mode) switch (mode)
{ {

52
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/ProgramFlow.cs
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@ -106,17 +106,18 @@ namespace cpu.m68000
{ {
sbyte displacement8 = (sbyte)op; sbyte displacement8 = (sbyte)op;
A[7].s32 -= 4; Register* ptrA7 = &A[7];
ptrA7->s32 -= 4;
if (displacement8 != 0) if (displacement8 != 0)
{ {
// use embedded displacement // use embedded displacement
WriteLong(A[7].s32, PC); WriteLong(ptrA7->s32, PC);
PC += displacement8; PC += displacement8;
} }
else else
{ {
// use extension word displacement // use extension word displacement
WriteLong(A[7].s32, PC + 2); WriteLong(ptrA7->s32, PC + 2);
PC += ReadOpWord(PC); PC += ReadOpWord(PC);
} }
pendingCycles -= 18; pendingCycles -= 18;
@ -151,19 +152,21 @@ namespace cpu.m68000
void RTS() void RTS()
{ {
PC = ReadLong(A[7].s32); Register* ptrA7 = &A[7];
A[7].s32 += 4; PC = ReadLong(ptrA7->s32);
ptrA7->s32 += 4;
pendingCycles -= 16; pendingCycles -= 16;
} }
void RTR() void RTR()
{ {
short value = ReadWord(A[7].s32); Register* ptrA7 = &A[7];
A[7].s32 += 2; short value = ReadWord(ptrA7->s32);
ptrA7->s32 += 2;
CCR = value; CCR = value;
PC = ReadLong(A[7].s32); PC = ReadLong(ptrA7->s32);
A[7].s32 += 4; ptrA7->s32 += 4;
pendingCycles -= 20; pendingCycles -= 20;
} }
@ -181,10 +184,11 @@ namespace cpu.m68000
void RTE() void RTE()
{ {
short newSR = ReadWord(A[7].s32); Register* ptrA7 = &A[7];
A[7].s32 += 2; short newSR = ReadWord(ptrA7->s32);
PC = ReadLong(A[7].s32); ptrA7->s32 += 2;
A[7].s32 += 4; PC = ReadLong(ptrA7->s32);
ptrA7->s32 += 4;
SR = newSR; SR = newSR;
pendingCycles -= 20; pendingCycles -= 20;
} }
@ -467,8 +471,9 @@ namespace cpu.m68000
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
int addr = ReadAddress(mode, reg); int addr = ReadAddress(mode, reg);
A[7].s32 -= 4; Register* ptrA7 = &A[7];
WriteLong(A[7].s32, PC); ptrA7->s32 -= 4;
WriteLong(ptrA7->s32, PC);
PC = addr; PC = addr;
switch (mode) switch (mode)
@ -492,11 +497,13 @@ namespace cpu.m68000
void LINK() void LINK()
{ {
int reg = op & 7; int reg = op & 7;
A[7].s32 -= 4;
Register* ptrA7 = &A[7];
ptrA7->s32 -= 4;
short offset = ReadOpWord(PC); PC += 2; short offset = ReadOpWord(PC); PC += 2;
WriteLong(A[7].s32, A[reg].s32); WriteLong(ptrA7->s32, A[reg].s32);
A[reg].s32 = A[7].s32; A[reg].s32 = ptrA7->s32;
A[7].s32 += offset; ptrA7->s32 += offset;
pendingCycles -= 16; pendingCycles -= 16;
} }
@ -504,9 +511,10 @@ namespace cpu.m68000
void UNLK() void UNLK()
{ {
int reg = op & 7; int reg = op & 7;
A[7].s32 = A[reg].s32; Register* ptrA7 = &A[7];
A[reg].s32 = ReadLong(A[7].s32); ptrA7->s32 = A[reg].s32;
A[7].s32 += 4; A[reg].s32 = ReadLong(ptrA7->s32);
ptrA7->s32 += 4;
pendingCycles -= 12; pendingCycles -= 12;
} }

20
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/Supervisor.cs
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@ -125,24 +125,26 @@ namespace cpu.m68000
void TrapVector(int vector) void TrapVector(int vector)
{ {
Register* ptrA7 = &A[7];
short sr = (short)SR; // capture current SR. short sr = (short)SR; // capture current SR.
S = true; // switch to supervisor mode, if not already in it. S = true; // switch to supervisor mode, if not already in it.
A[7].s32 -= 4; // Push PC on stack ptrA7->s32 -= 4; // Push PC on stack
WriteLong(A[7].s32, PC); WriteLong(ptrA7->s32, PC);
A[7].s32 -= 2; // Push SR on stack ptrA7->s32 -= 2; // Push SR on stack
WriteWord(A[7].s32, sr); WriteWord(ptrA7->s32, sr);
PC = ReadLong(vector * 4); // Jump to vector PC = ReadLong(vector * 4); // Jump to vector
pendingCycles -= CyclesException[vector]; pendingCycles -= CyclesException[vector];
} }
void TrapVector2(int vector) unsafe void TrapVector2(int vector)
{ {
Register* ptrA7 = &A[7];
short sr = (short)SR; // capture current SR. short sr = (short)SR; // capture current SR.
S = true; // switch to supervisor mode, if not already in it. S = true; // switch to supervisor mode, if not already in it.
A[7].s32 -= 4; // Push PPC on stack ptrA7->s32 -= 4; // Push PPC on stack
WriteLong(A[7].s32, PPC); WriteLong(ptrA7->s32, PPC);
A[7].s32 -= 2; // Push SR on stack ptrA7->s32 -= 2; // Push SR on stack
WriteWord(A[7].s32, sr); WriteWord(ptrA7->s32, sr);
PC = ReadLong(vector * 4); // Jump to vector PC = ReadLong(vector * 4); // Jump to vector
pendingCycles -= CyclesException[vector]; pendingCycles -= CyclesException[vector];
} }

36
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/MC68000.cs
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@ -107,18 +107,20 @@ namespace cpu.m68000
{ {
if (value == s) if (value == s)
return; return;
Register* ptrA7 = &A[7];
if (value == true) // entering supervisor mode if (value == true) // entering supervisor mode
{ {
//EmuLogger.Log("&^&^&^&^& ENTER SUPERVISOR MODE"); //EmuLogger.Log("&^&^&^&^& ENTER SUPERVISOR MODE");
usp = A[7].s32; usp = ptrA7->s32;
A[7].s32 = ssp; ptrA7->s32 = ssp;
s = true; s = true;
} }
else else
{ // exiting supervisor mode { // exiting supervisor mode
//EmuLogger.Log("&^&^&^&^& LEAVE SUPERVISOR MODE"); //EmuLogger.Log("&^&^&^&^& LEAVE SUPERVISOR MODE");
ssp = A[7].s32; ssp = ptrA7->s32;
A[7].s32 = usp; ptrA7->s32 = usp;
s = false; s = false;
} }
} }
@ -241,7 +243,7 @@ namespace cpu.m68000
m = false; m = false;
InterruptMaskLevel = 7; InterruptMaskLevel = 7;
Interrupt = 0; Interrupt = 0;
A[7].s32 = ReadOpLong(0); (A + 7)->s32 = ReadOpLong(0);
PC = ReadOpLong(4); PC = ReadOpLong(4);
} }
@ -311,10 +313,14 @@ namespace cpu.m68000
//int vector = Cpuint.cpu_irq_callback(cpunum, Interrupt); //int vector = Cpuint.cpu_irq_callback(cpunum, Interrupt);
short sr = (short)SR; // capture current SR. short sr = (short)SR; // capture current SR.
S = true; // switch to supervisor mode, if not already in it. S = true; // switch to supervisor mode, if not already in it.
A[7].s32 -= 4; // Push PC on stack
WriteLong(A[7].s32, PC);
A[7].s32 -= 2; // Push SR on stack Register* ptrA7 = &A[7];
WriteWord(A[7].s32, sr);
ptrA7->s32 -= 4; // Push PC on stack
WriteLong(ptrA7->s32, PC);
ptrA7->s32 -= 2; // Push SR on stack
WriteWord(ptrA7->s32, sr);
PC = ReadLong((24 + Interrupt) * 4); // Jump to interrupt vector PC = ReadLong((24 + Interrupt) * 4); // Jump to interrupt vector
InterruptMaskLevel = Interrupt; // Set interrupt mask to level currently being entered InterruptMaskLevel = Interrupt; // Set interrupt mask to level currently being entered
Interrupt = 0; // "ack" interrupt. Note: this is wrong. Interrupt = 0; // "ack" interrupt. Note: this is wrong.
@ -342,10 +348,12 @@ namespace cpu.m68000
//int vector = Cpuint.cpu_irq_callback(cpunum, Interrupt); //int vector = Cpuint.cpu_irq_callback(cpunum, Interrupt);
short sr = (short)SR; // capture current SR. short sr = (short)SR; // capture current SR.
S = true; // switch to supervisor mode, if not already in it. S = true; // switch to supervisor mode, if not already in it.
A[7].s32 -= 4; // Push PC on stack
WriteLong(A[7].s32, PC); Register* ptrA7 = &A[7];
A[7].s32 -= 2; // Push SR on stack ptrA7->s32 -= 4; // Push PC on stack
WriteWord(A[7].s32, sr); WriteLong(ptrA7->s32, PC);
ptrA7->s32 -= 2; // Push SR on stack
WriteWord(ptrA7->s32, sr);
PC = ReadLong((24 + Interrupt) * 4); // Jump to interrupt vector PC = ReadLong((24 + Interrupt) * 4); // Jump to interrupt vector
InterruptMaskLevel = Interrupt; // Set interrupt mask to level currently being entered InterruptMaskLevel = Interrupt; // Set interrupt mask to level currently being entered
Interrupt = 0; // "ack" interrupt. Note: this is wrong. Interrupt = 0; // "ack" interrupt. Note: this is wrong.
@ -358,7 +366,7 @@ namespace cpu.m68000
// string a = Disassemble(PC).ToString().PadRight(64); // string a = Disassemble(PC).ToString().PadRight(64);
// //string a = string.Format("{0:X6}: {1:X4}", PC, ReadWord(PC)).PadRight(64); // //string a = string.Format("{0:X6}: {1:X4}", PC, ReadWord(PC)).PadRight(64);
// string b = string.Format("D0:{0:X8} D1:{1:X8} D2:{2:X8} D3:{3:X8} D4:{4:X8} D5:{5:X8} D6:{6:X8} D7:{7:X8} ", D[0].u32, D[1].u32, D[2].u32, D[3].u32, D[4].u32, D[5].u32, D[6].u32, D[7].u32); // string b = string.Format("D0:{0:X8} D1:{1:X8} D2:{2:X8} D3:{3:X8} D4:{4:X8} D5:{5:X8} D6:{6:X8} D7:{7:X8} ", D[0].u32, D[1].u32, D[2].u32, D[3].u32, D[4].u32, D[5].u32, D[6].u32, D[7].u32);
// string c = string.Format("A0:{0:X8} A1:{1:X8} A2:{2:X8} A3:{3:X8} A4:{4:X8} A5:{5:X8} A6:{6:X8} A7:{7:X8} ", A[0].u32, A[1].u32, A[2].u32, A[3].u32, A[4].u32, A[5].u32, A[6].u32, A[7].u32); // string c = string.Format("A0:{0:X8} A1:{1:X8} A2:{2:X8} A3:{3:X8} A4:{4:X8} A5:{5:X8} A6:{6:X8} A7:{7:X8} ", A[0].u32, A[1].u32, A[2].u32, A[3].u32, A[4].u32, A[5].u32, A[6].u32, ptrA7->u32);
// string d = string.Format("SR:{0:X4} Pending {1}", SR, pendingCycles); // string d = string.Format("SR:{0:X4} Pending {1}", SR, pendingCycles);
// return a + b + c + d; // return a + b + c + d;
//} //}

387
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Memory.cs
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@ -4,29 +4,83 @@ namespace cpu.m68000
{ {
unsafe partial class MC68000 unsafe partial class MC68000
{ {
//sbyte ReadValueB(int mode, int reg)
//{
// sbyte value;
// switch (mode)
// {
// case 0: // Dn
// return D[reg].s8;
// case 1: // An
// return A[reg].s8;
// case 2: // (An)
// return ReadByte(A[reg].s32);
// case 3: // (An)+
// value = ReadByte(A[reg].s32);
// A[reg].s32 += reg == 7 ? 2 : 1;
// return value;
// case 4: // -(An)
// A[reg].s32 -= reg == 7 ? 2 : 1;
// return ReadByte(A[reg].s32);
// case 5: // (d16,An)
// value = ReadByte((A[reg].s32 + ReadOpWord(PC))); PC += 2;
// return value;
// case 6: // (d8,An,Xn)
// return ReadByte(A[reg].s32 + GetIndex());
// case 7:
// switch (reg)
// {
// case 0: // (imm).W
// value = ReadByte(ReadOpWord(PC)); PC += 2;
// return value;
// case 1: // (imm).L
// value = ReadByte(ReadOpLong(PC)); PC += 4;
// return value;
// case 2: // (d16,PC)
// value = ReadOpByte(PC + ReadOpWord(PC)); PC += 2;
// return value;
// case 3: // (d8,PC,Xn)
// int pc = PC;
// value = ReadOpByte((pc + GetIndex()));
// return value;
// case 4: // immediate
// value = (sbyte)ReadOpWord(PC); PC += 2;
// return value;
// default:
// throw new Exception("Invalid addressing mode!");
// }
// }
// throw new Exception("Invalid addressing mode!");
//}
sbyte ReadValueB(int mode, int reg) sbyte ReadValueB(int mode, int reg)
{ {
sbyte value; sbyte value;
switch (mode) switch (mode)
{ {
case 0: // Dn case 0: // Dn
return D[reg].s8; return (D + reg)->s8;
case 1: // An case 1: // An
return A[reg].s8; return (A + reg)->s8;
case 2: // (An) case 2: // (An)
return ReadByte(A[reg].s32); return ReadByte((A + reg)->s32);
case 3: // (An)+ case 3: // (An)+
value = ReadByte(A[reg].s32); {
A[reg].s32 += reg == 7 ? 2 : 1; Register* ptr = &A[reg];
value = ReadByte(ptr->s32);
ptr->s32 += reg == 7 ? 2 : 1;
}
return value; return value;
case 4: // -(An) case 4: // -(An)
A[reg].s32 -= reg == 7 ? 2 : 1; {
return ReadByte(A[reg].s32); Register* ptr = &A[reg];
ptr->s32 -= reg == 7 ? 2 : 1;
return ReadByte(ptr->s32);
}
case 5: // (d16,An) case 5: // (d16,An)
value = ReadByte((A[reg].s32 + ReadOpWord(PC))); PC += 2; value = ReadByte(((A + reg)->s32 + ReadOpWord(PC))); PC += 2;
return value; return value;
case 6: // (d8,An,Xn) case 6: // (d8,An,Xn)
return ReadByte(A[reg].s32 + GetIndex()); return ReadByte((A + reg)->s32 + GetIndex());
case 7: case 7:
switch (reg) switch (reg)
{ {
@ -53,29 +107,83 @@ namespace cpu.m68000
throw new Exception("Invalid addressing mode!"); throw new Exception("Invalid addressing mode!");
} }
//short ReadValueW(int mode, int reg)
//{
// short value;
// switch (mode)
// {
// case 0: // Dn
// return D[reg].s16;
// case 1: // An
// return A[reg].s16;
// case 2: // (An)
// return ReadWord(A[reg].s32);
// case 3: // (An)+
// value = ReadWord(A[reg].s32);
// A[reg].s32 += 2;
// return value;
// case 4: // -(An)
// A[reg].s32 -= 2;
// return ReadWord(A[reg].s32);
// case 5: // (d16,An)
// value = ReadWord((A[reg].s32 + ReadOpWord(PC))); PC += 2;
// return value;
// case 6: // (d8,An,Xn)
// return ReadWord(A[reg].s32 + GetIndex());
// case 7:
// switch (reg)
// {
// case 0: // (imm).W
// value = ReadWord(ReadOpWord(PC)); PC += 2;
// return value;
// case 1: // (imm).L
// value = ReadWord(ReadOpLong(PC)); PC += 4;
// return value;
// case 2: // (d16,PC)
// value = ReadOpWord(PC + ReadOpWord(PC)); PC += 2;
// return value;
// case 3: // (d8,PC,Xn)
// int pc = PC;
// value = ReadOpWord((pc + GetIndex()));
// return value;
// case 4: // immediate
// value = ReadOpWord(PC); PC += 2;
// return value;
// default:
// throw new Exception("Invalid addressing mode!");
// }
// }
// throw new Exception("Invalid addressing mode!");
//}
short ReadValueW(int mode, int reg) short ReadValueW(int mode, int reg)
{ {
short value; short value;
switch (mode) switch (mode)
{ {
case 0: // Dn case 0: // Dn
return D[reg].s16; return (D + reg)->s16;
case 1: // An case 1: // An
return A[reg].s16; return (A + reg)->s16;
case 2: // (An) case 2: // (An)
return ReadWord(A[reg].s32); return ReadWord((A + reg)->s32);
case 3: // (An)+ case 3: // (An)+
value = ReadWord(A[reg].s32); {
A[reg].s32 += 2; Register* ptr = &A[reg];
value = ReadWord(ptr->s32);
ptr->s32 += 2;
return value; return value;
}
case 4: // -(An) case 4: // -(An)
A[reg].s32 -= 2; {
return ReadWord(A[reg].s32); Register* ptr = &A[reg];
ptr->s32 -= 2;
return ReadWord(ptr->s32);
}
case 5: // (d16,An) case 5: // (d16,An)
value = ReadWord((A[reg].s32 + ReadOpWord(PC))); PC += 2; value = ReadWord((A + reg)->s32 + ReadOpWord(PC)); PC += 2;
return value; return value;
case 6: // (d8,An,Xn) case 6: // (d8,An,Xn)
return ReadWord(A[reg].s32 + GetIndex()); return ReadWord((A + reg)->s32 + GetIndex());
case 7: case 7:
switch (reg) switch (reg)
{ {
@ -101,6 +209,54 @@ namespace cpu.m68000
} }
throw new Exception("Invalid addressing mode!"); throw new Exception("Invalid addressing mode!");
} }
//int ReadValueL(int mode, int reg)
//{
// int value;
// switch (mode)
// {
// case 0: // Dn
// return D[reg].s32;
// case 1: // An
// return A[reg].s32;
// case 2: // (An)
// return ReadLong(A[reg].s32);
// case 3: // (An)+
// value = ReadLong(A[reg].s32);
// A[reg].s32 += 4;
// return value;
// case 4: // -(An)
// A[reg].s32 -= 4;
// return ReadLong(A[reg].s32);
// case 5: // (d16,An)
// value = ReadLong((A[reg].s32 + ReadOpWord(PC))); PC += 2;
// return value;
// case 6: // (d8,An,Xn)
// return ReadLong(A[reg].s32 + GetIndex());
// case 7:
// switch (reg)
// {
// case 0: // (imm).W
// value = ReadLong(ReadOpWord(PC)); PC += 2;
// return value;
// case 1: // (imm).L
// value = ReadLong(ReadOpLong(PC)); PC += 4;
// return value;
// case 2: // (d16,PC)
// value = ReadOpLong(PC + ReadOpWord(PC)); PC += 2;
// return value;
// case 3: // (d8,PC,Xn)
// int pc = PC;
// value = ReadOpLong((pc + GetIndex()));
// return value;
// case 4: // immediate
// value = ReadOpLong(PC); PC += 4;
// return value;
// default:
// throw new Exception("Invalid addressing mode!");
// }
// }
// throw new Exception("Invalid addressing mode!");
//}
int ReadValueL(int mode, int reg) int ReadValueL(int mode, int reg)
{ {
@ -108,23 +264,29 @@ namespace cpu.m68000
switch (mode) switch (mode)
{ {
case 0: // Dn case 0: // Dn
return D[reg].s32; return (D + reg)->s32;
case 1: // An case 1: // An
return A[reg].s32; return (A + reg)->s32;
case 2: // (An) case 2: // (An)
return ReadLong(A[reg].s32); return ReadLong((A + reg)->s32);
case 3: // (An)+ case 3: // (An)+
value = ReadLong(A[reg].s32); {
A[reg].s32 += 4; Register* ptr = &A[reg];
value = ReadLong(ptr->s32);
ptr->s32 += 4;
}
return value; return value;
case 4: // -(An) case 4: // -(An)
A[reg].s32 -= 4; {
return ReadLong(A[reg].s32); Register* ptr = &A[reg];
ptr->s32 -= 4;
return ReadLong(ptr->s32);
}
case 5: // (d16,An) case 5: // (d16,An)
value = ReadLong((A[reg].s32 + ReadOpWord(PC))); PC += 2; value = ReadLong(((A + reg)->s32 + ReadOpWord(PC))); PC += 2;
return value; return value;
case 6: // (d8,An,Xn) case 6: // (d8,An,Xn)
return ReadLong(A[reg].s32 + GetIndex()); return ReadLong((A + reg)->s32 + GetIndex());
case 7: case 7:
switch (reg) switch (reg)
{ {
@ -316,32 +478,87 @@ namespace cpu.m68000
} }
//void WriteValueB(int mode, int reg, sbyte value)
//{
// switch (mode)
// {
// case 0x00: // Dn
// D[reg].s8 = value;
// return;
// case 0x01: // An
// A[reg].s32 = value;
// return;
// case 0x02: // (An)
// WriteByte(A[reg].s32, value);
// return;
// case 0x03: // (An)+
// WriteByte(A[reg].s32, value);
// A[reg].s32 += reg == 7 ? 2 : 1;
// return;
// case 0x04: // -(An)
// A[reg].s32 -= reg == 7 ? 2 : 1;
// WriteByte(A[reg].s32, value);
// return;
// case 0x05: // (d16,An)
// WriteByte(A[reg].s32 + ReadOpWord(PC), value); PC += 2;
// return;
// case 0x06: // (d8,An,Xn)
// WriteByte(A[reg].s32 + GetIndex(), value);
// return;
// case 0x07:
// switch (reg)
// {
// case 0x00: // (imm).W
// WriteByte(ReadOpWord(PC), value); PC += 2;
// return;
// case 0x01: // (imm).L
// WriteByte(ReadOpLong(PC), value); PC += 4;
// return;
// case 0x02: // (d16,PC)
// WriteByte(PC + ReadOpWord(PC), value); PC += 2;
// return;
// case 0x03: // (d8,PC,Xn)
// int pc = PC;
// WriteByte(pc + PeekIndex(), value);
// PC += 2;
// return;
// default: throw new Exception("Invalid addressing mode!");
// }
// }
//}
void WriteValueB(int mode, int reg, sbyte value) void WriteValueB(int mode, int reg, sbyte value)
{ {
switch (mode) switch (mode)
{ {
case 0x00: // Dn case 0x00: // Dn
D[reg].s8 = value; (D + reg)->s8 = value;
return; return;
case 0x01: // An case 0x01: // An
A[reg].s32 = value; (A + reg)->s32 = value;
return; return;
case 0x02: // (An) case 0x02: // (An)
WriteByte(A[reg].s32, value); WriteByte((A + reg)->s32, value);
return; return;
case 0x03: // (An)+ case 0x03: // (An)+
WriteByte(A[reg].s32, value); {
A[reg].s32 += reg == 7 ? 2 : 1; Register* ptr = &A[reg];
WriteByte(ptr->s32, value);
ptr->s32 += reg == 7 ? 2 : 1;
}
return; return;
case 0x04: // -(An) case 0x04: // -(An)
A[reg].s32 -= reg == 7 ? 2 : 1; {
WriteByte(A[reg].s32, value); Register* ptr = &A[reg];
ptr->s32 -= reg == 7 ? 2 : 1;
WriteByte(ptr->s32, value);
}
return; return;
case 0x05: // (d16,An) case 0x05: // (d16,An)
WriteByte(A[reg].s32 + ReadOpWord(PC), value); PC += 2; WriteByte((A + reg)->s32 + ReadOpWord(PC), value); PC += 2;
return; return;
case 0x06: // (d8,An,Xn) case 0x06: // (d8,An,Xn)
WriteByte(A[reg].s32 + GetIndex(), value); WriteByte((A + reg)->s32 + GetIndex(), value);
return; return;
case 0x07: case 0x07:
switch (reg) switch (reg)
@ -365,32 +582,88 @@ namespace cpu.m68000
} }
} }
//void WriteValueW(int mode, int reg, short value)
//{
// switch (mode)
// {
// case 0x00: // Dn
// D[reg].s16 = value;
// return;
// case 0x01: // An
// A[reg].s32 = value;
// return;
// case 0x02: // (An)
// WriteWord(A[reg].s32, value);
// return;
// case 0x03: // (An)+
// WriteWord(A[reg].s32, value);
// A[reg].s32 += 2;
// return;
// case 0x04: // -(An)
// A[reg].s32 -= 2;
// WriteWord(A[reg].s32, value);
// return;
// case 0x05: // (d16,An)
// WriteWord(A[reg].s32 + ReadOpWord(PC), value); PC += 2;
// return;
// case 0x06: // (d8,An,Xn)
// WriteWord(A[reg].s32 + GetIndex(), value);
// return;
// case 0x07:
// switch (reg)
// {
// case 0x00: // (imm).W
// WriteWord(ReadOpWord(PC), value); PC += 2;
// return;
// case 0x01: // (imm).L
// WriteWord(ReadOpLong(PC), value); PC += 4;
// return;
// case 0x02: // (d16,PC)
// WriteWord(PC + ReadOpWord(PC), value); PC += 2;
// return;
// case 0x03: // (d8,PC,Xn)
// int pc = PC;
// WriteWord(pc + PeekIndex(), value);
// PC += 2;
// return;
// default: throw new Exception("Invalid addressing mode!");
// }
// }
//}
void WriteValueW(int mode, int reg, short value) void WriteValueW(int mode, int reg, short value)
{ {
switch (mode) switch (mode)
{ {
case 0x00: // Dn case 0x00: // Dn
D[reg].s16 = value; (D + reg)->s16 = value;
return; return;
case 0x01: // An case 0x01: // An
A[reg].s32 = value; (A + reg)->s32 = value;
return; return;
case 0x02: // (An) case 0x02: // (An)
WriteWord(A[reg].s32, value); WriteWord((A + reg)->s32, value);
return; return;
case 0x03: // (An)+ case 0x03: // (An)+
WriteWord(A[reg].s32, value); {
A[reg].s32 += 2; Register* ptr = &A[reg];
WriteWord(ptr->s32, value);
ptr->s32 += 2;
}
return; return;
case 0x04: // -(An) case 0x04: // -(An)
A[reg].s32 -= 2; {
WriteWord(A[reg].s32, value); Register* ptr = &A[reg];
ptr->s32 -= 2;
WriteWord(ptr->s32, value);
}
return; return;
case 0x05: // (d16,An) case 0x05: // (d16,An)
WriteWord(A[reg].s32 + ReadOpWord(PC), value); PC += 2; WriteWord((A + reg)->s32 + ReadOpWord(PC), value); PC += 2;
return; return;
case 0x06: // (d8,An,Xn) case 0x06: // (d8,An,Xn)
WriteWord(A[reg].s32 + GetIndex(), value); WriteWord((A + reg)->s32 + GetIndex(), value);
return; return;
case 0x07: case 0x07:
switch (reg) switch (reg)
@ -419,27 +692,33 @@ namespace cpu.m68000
switch (mode) switch (mode)
{ {
case 0x00: // Dn case 0x00: // Dn
D[reg].s32 = value; (D + reg)->s32 = value;
return; return;
case 0x01: // An case 0x01: // An
A[reg].s32 = value; (A + reg)->s32 = value;
return; return;
case 0x02: // (An) case 0x02: // (An)
WriteLong(A[reg].s32, value); WriteLong((A + reg)->s32, value);
return; return;
case 0x03: // (An)+ case 0x03: // (An)+
WriteLong(A[reg].s32, value); {
A[reg].s32 += 4; Register* ptr = &A[reg];
WriteLong(ptr->s32, value);
ptr->s32 += 4;
}
return; return;
case 0x04: // -(An) case 0x04: // -(An)
A[reg].s32 -= 4; {
WriteLong(A[reg].s32, value); Register* ptr = &A[reg];
ptr->s32 -= 4;
WriteLong(ptr->s32, value);
}
return; return;
case 0x05: // (d16,An) case 0x05: // (d16,An)
WriteLong(A[reg].s32 + ReadOpWord(PC), value); PC += 2; WriteLong((A + reg)->s32 + ReadOpWord(PC), value); PC += 2;
return; return;
case 0x06: // (d8,An,Xn) case 0x06: // (d8,An,Xn)
WriteLong(A[reg].s32 + GetIndex(), value); WriteLong((A + reg)->s32 + GetIndex(), value);
return; return;
case 0x07: case 0x07:
switch (reg) switch (reg)

114
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/mame/neogeo/Memory.cs
View File

@ -354,6 +354,120 @@ namespace MAME.Core
} }
return result; return result;
} }
//public static short MReadWord(int address)
//{
// address &= 0xffffff;
// short result = 0;
// if (address >= 0x000000 && address + 1 <= 0x00007f)
// {
// if (main_cpu_vector_table_source == 0)
// {
// byte* ptr_0 = &mainbiosrom[0];
// byte* ptr = ptr_0 + address;
// //result = (short)(mainbiosrom[address] * 0x100 + mainbiosrom[address + 1]);
// result = (short)(*ptr * 0x100 + *(ptr + 1));
// }
// else if (main_cpu_vector_table_source == 1)
// {
// byte* ptr_0 = &Memory.mainrom[0];
// byte* ptr = ptr_0 + address;
// //result = (short)(Memory.mainrom[address] * 0x100 + Memory.mainrom[address + 1]);
// result = (short)(*ptr * 0x100 + *(ptr + 1));
// }
// }
// else if (address >= 0x000080 && address + 1 <= 0x0fffff)
// {
// //if (address >= 0x142B9 && address <= 0x142C9)
// //{
// // //m68000Form.iStatus = 1;
// //}
// byte* ptr_0 = &Memory.mainrom[0];
// byte* ptr = ptr_0 + address;
// //result = (short)(Memory.mainrom[address] * 0x100 + Memory.mainrom[address + 1]);
// result = (short)(*ptr * 0x100 + *(ptr + 1));
// }
// else if (address >= 0x100000 && address + 1 <= 0x1fffff)
// {
// //if (address == 0x101410)
// //{
// // int i1 = 1;
// //}
// byte* ptr_0 = &Memory.mainrom[0];
// byte* ptr = ptr_0 + (address & 0xffff);
// //result = (short)(Memory.mainram[address & 0xffff] * 0x100 + Memory.mainram[(address & 0xffff) + 1]);
// result = (short)(*ptr * 0x100 + *(ptr + 1));
// }
// else if (address >= 0x200000 && address <= 0x2fffff)
// {
// byte* ptr_0 = &Memory.mainrom[0];
// byte* ptr = ptr_0 + (main_cpu_bank_address + (address & 0xfffff));
// //result = (short)(Memory.mainrom[main_cpu_bank_address + (address & 0xfffff)] * 0x100 + Memory.mainrom[main_cpu_bank_address + (address & 0xfffff) + 1]);
// result = (short)(*ptr * 0x100 + *(ptr + 1));
// }
// /*else if (address >= 0x300000 && address <= 0x300001)
// {
// result = (short)((ushort)short0 | dsw);
// }
// else if (address >= 0x300080 && address <= 0x300081)
// {
// result = short4;
// }*/
// else if (address >= 0x300000 && address <= 0x31ffff)
// {
// int add = address & 0x81;
// if (add >= 0x00 && add + 1 <= 0x01)
// {
// result = (short)((ushort)short0 | dsw);
// }
// else if (add >= 0x80 && add + 1 <= 0x81)
// {
// result = short4;
// }
// }
// else if (address >= 0x320000 && address <= 0x33ffff)
// {
// result = (short)((ushort)short3 | (ushort)((get_calendar_status() & 0x03) << 6) | (get_audio_result() << 8));
// }
// else if (address >= 0x340000 && address <= 0x35ffff)
// {
// result = short1;
// }
// else if (address >= 0x380000 && address <= 0x39ffff)
// {
// result = short2;
// }
// else if (address >= 0x3c0000 && address + 1 <= 0x3dffff)
// {
// result = (short)neogeo_video_register_r((address & 0x07) >> 1);
// }
// else if (address >= 0x400000 && address + 1 <= 0x7fffff)
// {
// result = (short)palettes[palette_bank, (address & 0x1fff) >> 1];
// }
// else if (address >= 0xc00000 && address + 1 <= 0xcfffff)
// {
// byte* ptr_0 = &Memory.mainrom[0];
// byte* ptr = ptr_0 + (address & 0x1ffff);
// //result = (short)(mainbiosrom[address & 0x1ffff] * 0x100 + mainbiosrom[(address & 0x1ffff) + 1]);
// result = (short)(*ptr * 0x100 + *(ptr + 1));
// }
// else if (address >= 0xd00000 && address + 1 <= 0xdfffff)
// {
// byte* ptr_0 = &Memory.mainrom[0];
// byte* ptr = ptr_0 + (address & 0xffff);
// //result = (short)(mainram2[address & 0xffff] * 0x100 + mainram2[(address & 0xffff) + 1]);
// result = (short)(*ptr * 0x100 + *(ptr + 1));
// }
// //else
// //{
// // int i1 = 1;
// //}
// return result;
//}
public static int MReadOpLong(int address) public static int MReadOpLong(int address)
{ {
address &= 0xffffff; address &= 0xffffff;