sin365/AxibugEmuOnline
1
0
Fork 1
Code Issues Pull Requests Projects Releases Wiki Activity

Merge branch 'master' of http://git.axibug.com/sin365/AxibugEmuOnline

Browse Source
This commit is contained in:
ALIENJACK\alien 2024-08-16 10:25:09 +08:00
commit 57cb91262b
193 changed files with 8909 additions and 9256 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
AxibugEmuOnline.Client/Assets/Script/Manager/AppEmu.cs
View File

@ -1,7 +1,4 @@
using System.IO; namespace AxibugEmuOnline.Client.Manager
using UnityEngine;
namespace AxibugEmuOnline.Client.Manager
{ {
public class AppEmu public class AppEmu
{ {

4
AxibugEmuOnline.Client/Assets/Script/Manager/AppLogin.cs
View File

@ -17,7 +17,7 @@ namespace AxibugEmuOnline.Client.Manager
public void Login() public void Login()
{ {
AppAxibugEmuOnline.log.Debug("-->Login"); AppAxibugEmuOnline.log.Debug("-->Login");
if(string.IsNullOrEmpty(LastLoginGuid)) if (string.IsNullOrEmpty(LastLoginGuid))
LastLoginGuid = Guid.NewGuid().ToString(); LastLoginGuid = Guid.NewGuid().ToString();
AppAxibugEmuOnline.user.userdata.Account = LastLoginGuid; AppAxibugEmuOnline.user.userdata.Account = LastLoginGuid;
@ -35,7 +35,7 @@ namespace AxibugEmuOnline.Client.Manager
if (msg.Status == LoginResultStatus.Ok) if (msg.Status == LoginResultStatus.Ok)
{ {
AppAxibugEmuOnline.log.Info("登录成功"); AppAxibugEmuOnline.log.Info("登录成功");
AppAxibugEmuOnline.user.InitMainUserData(AppAxibugEmuOnline.user.userdata.Account,msg.UID); AppAxibugEmuOnline.user.InitMainUserData(AppAxibugEmuOnline.user.userdata.Account, msg.UID);
} }
else else
{ {

6
AxibugEmuOnline.Client/Assets/Script/Manager/LogManager.cs
View File

@ -2,7 +2,7 @@
{ {
public class LogManager public class LogManager
{ {
public enum E_LogType:byte public enum E_LogType : byte
{ {
Info = 0, Info = 0,
Debug = 1, Debug = 1,
@ -13,7 +13,7 @@
/// 日志 /// 日志
/// </summary> /// </summary>
/// <param name="sk"></param> /// <param name="sk"></param>
public delegate void OnLogHandler(int debuglv,string msg); public delegate void OnLogHandler(int debuglv, string msg);
/// <summary> /// <summary>
/// 内部输出 /// 内部输出
@ -40,7 +40,7 @@
Log(E_LogType.Error, str); Log(E_LogType.Error, str);
} }
public void Log(E_LogType logtype,string str) public void Log(E_LogType logtype, string str)
{ {
OnLog?.Invoke((int)logtype, str); OnLog?.Invoke((int)logtype, str);
} }

8
AxibugEmuOnline.Client/Assets/Script/Manager/RomLib/EnumPlatform.cs
View File

@ -1,10 +1,4 @@
using System; namespace AxibugEmuOnline.Client
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
namespace AxibugEmuOnline.Client
{ {
public enum EnumPlatform public enum EnumPlatform
{ {

1
AxibugEmuOnline.Client/Assets/Script/Manager/RomLib/RomFile.cs
View File

@ -3,7 +3,6 @@ using ICSharpCode.SharpZipLib.Zip;
using System; using System;
using System.Collections; using System.Collections;
using System.IO; using System.IO;
using System.Linq;
using UnityEngine; using UnityEngine;
using UnityEngine.Networking; using UnityEngine.Networking;

7
AxibugEmuOnline.Client/Assets/Script/Manager/RomLib/RomLib.cs
View File

@ -11,7 +11,8 @@ namespace AxibugEmuOnline.Client
public RomFile GetNesRomFile(string romFileName) public RomFile GetNesRomFile(string romFileName)
{ {
nesRomFileNameMapper.TryGetValue(romFileName, out RomFile romFile); RomFile romFile;
nesRomFileNameMapper.TryGetValue(romFileName, out romFile);
return romFile; return romFile;
} }
@ -29,8 +30,8 @@ namespace AxibugEmuOnline.Client
for (int i = 0; i < romList.gameList.Count; i++) for (int i = 0; i < romList.gameList.Count; i++)
{ {
var webData = romList.gameList[i]; var webData = romList.gameList[i];
RomFile targetRomFile;
nesRomFileIdMapper.TryGetValue(webData.id, out var targetRomFile); nesRomFileIdMapper.TryGetValue(webData.id, out targetRomFile);
if (targetRomFile == null) if (targetRomFile == null)
{ {
targetRomFile = new RomFile(EnumPlatform.NES); targetRomFile = new RomFile(EnumPlatform.NES);

5
AxibugEmuOnline.Client/Assets/Script/Manager/UserDataManager.cs
View File

@ -1,5 +1,4 @@
using AxibugEmuOnline.Client.ClientCore; using AxibugEmuOnline.Client.ClientCore;
using AxibugProtobuf;
namespace AxibugEmuOnline.Client.Manager namespace AxibugEmuOnline.Client.Manager
{ {
@ -21,10 +20,10 @@ namespace AxibugEmuOnline.Client.Manager
//注册重连成功事件，以便后续自动登录 //注册重连成功事件，以便后续自动登录
AppAxibugEmuOnline.networkHelper.OnReConnected += OnReConnected; AppAxibugEmuOnline.networkHelper.OnReConnected += OnReConnected;
} }
public MainUserDataBase userdata { get;private set; } = new MainUserDataBase(); public MainUserDataBase userdata { get; private set; } = new MainUserDataBase();
public bool IsLoggedIn => userdata.IsLoggedIn; public bool IsLoggedIn => userdata.IsLoggedIn;
public void InitMainUserData(string UName,long UID) public void InitMainUserData(string UName, long UID)
{ {
userdata.Account = UName; userdata.Account = UName;
userdata.IsLoggedIn = true; userdata.IsLoggedIn = true;

3
AxibugEmuOnline.Client/Assets/Script/NesEmulator/AudioProvider.cs
View File

@ -33,7 +33,8 @@ namespace AxibugEmuOnline.Client
for (int i = 0; i < data.Length; i += step) for (int i = 0; i < data.Length; i += step)
{ {
float rawFloat = 0; float rawFloat = 0;
if (_buffer.TryRead(out byte rawData)) byte rawData;
if (_buffer.TryRead(out rawData))
rawFloat = rawData / 255f; rawFloat = rawData / 255f;
data[i] = rawFloat; data[i] = rawFloat;

2
AxibugEmuOnline.Client/Assets/Script/NesEmulator/CoreDebuger.cs
View File

@ -1,5 +1,3 @@
using System.Collections;
using System.Collections.Generic;
using UnityEngine; using UnityEngine;
using VirtualNes.Core.Debug; using VirtualNes.Core.Debug;

2
AxibugEmuOnline.Client/Assets/Script/NesEmulator/CoreSupporter.cs
View File

@ -1,8 +1,6 @@
using AxibugEmuOnline.Client.ClientCore; using AxibugEmuOnline.Client.ClientCore;
using System; using System;
using System.IO; using System.IO;
using System.Linq;
using System.Xml.Linq;
using UnityEngine; using UnityEngine;
using VirtualNes.Core; using VirtualNes.Core;

1
AxibugEmuOnline.Client/Assets/Script/NesEmulator/NesEmulator.cs
View File

@ -1,7 +1,6 @@
using AxibugEmuOnline.Client.ClientCore; using AxibugEmuOnline.Client.ClientCore;
using System; using System;
using System.IO; using System.IO;
using System.Linq;
using System.Xml.Linq; using System.Xml.Linq;
using UnityEngine; using UnityEngine;
using VirtualNes.Core; using VirtualNes.Core;

9
AxibugEmuOnline.Client/Assets/Script/NesEmulator/PaletteDefine.cs
View File

@ -1,11 +1,4 @@
using Codice.CM.Client.Differences; using VirtualNes.Core;
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
using UnityEngine;
using VirtualNes.Core;
namespace AxibugEmuOnline.Client namespace AxibugEmuOnline.Client
{ {

4
AxibugEmuOnline.Client/Assets/Script/NesEmulator/RomDB.cs
View File

@ -31,8 +31,8 @@ namespace AxibugEmuOnline.Client.ClientCore
crc_Info_mapper[info.CRC] = info; crc_Info_mapper[info.CRC] = info;
} }
} }
RomInfo romInfo;
if (crc_Info_mapper.TryGetValue(crc, out var romInfo)) if (crc_Info_mapper.TryGetValue(crc, out romInfo))
{ {
mapperNo = romInfo.Mapper; mapperNo = romInfo.Mapper;
return true; return true;

8
AxibugEmuOnline.Client/Assets/VirtualNes.Core/APU.cs
View File

@ -1,9 +1,5 @@
using Codice.CM.Client.Differences; 
using System; using System;
using System.IO;
using System.Security.Principal;
using UnityEngine;
using VirtualNes.Core;
using VirtualNes.Core.Debug; using VirtualNes.Core.Debug;
namespace VirtualNes.Core namespace VirtualNes.Core
@ -80,7 +76,7 @@ namespace VirtualNes.Core
int nBits = Supporter.Config.sound.nBits; int nBits = Supporter.Config.sound.nBits;
uint dwLength = (uint)(dwSize / (nBits / 8)); uint dwLength = (uint)(dwSize / (nBits / 8));
int output; int output;
QUEUEDATA q = default; QUEUEDATA q = new QUEUEDATA();
uint writetime; uint writetime;
var pSoundBuf = m_SoundBuffer; var pSoundBuf = m_SoundBuffer;

2
AxibugEmuOnline.Client/Assets/VirtualNes.Core/ApuEX/APU_FME7.cs
View File

@ -1,6 +1,4 @@
using System; using System;
using static VirtualNes.Core.APU_INTERNAL;
using System.Net;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

4
AxibugEmuOnline.Client/Assets/VirtualNes.Core/ApuEX/APU_INTERNAL.cs
View File

@ -1,7 +1,5 @@
using Codice.CM.Client.Differences;
using System; using System;
using System.Runtime.CompilerServices;
using UnityEngine;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

2
AxibugEmuOnline.Client/Assets/VirtualNes.Core/ApuEX/APU_MMC5.cs
View File

@ -1,4 +1,4 @@
using Codice.CM.Client.Differences; 
using System; using System;
namespace VirtualNes.Core namespace VirtualNes.Core

32
AxibugEmuOnline.Client/Assets/VirtualNes.Core/ApuEX/APU_VRC6.cs
View File

@ -263,16 +263,16 @@ namespace VirtualNes.Core
public void ZeroMemory() public void ZeroMemory()
{ {
Array.Clear(reg, 0, reg.Length); Array.Clear(reg, 0, reg.Length);
enable = default; enable = 0;
gate = default; gate = 0;
volume = default; volume = 0;
phaseacc = default; phaseacc = 0;
freq = default; freq = 0;
output_vol = default; output_vol = 0;
adder = default; adder = 0;
duty_pos = default; duty_pos = 0;
} }
} }
@ -294,16 +294,16 @@ namespace VirtualNes.Core
public void ZeroMemory() public void ZeroMemory()
{ {
Array.Clear(reg, 0, reg.Length); Array.Clear(reg, 0, reg.Length);
enable = default; enable = 0;
volume = default; volume = 0;
phaseacc = default; phaseacc = 0;
freq = default; freq = 0;
output_vol = default; output_vol = 0;
adder = default; adder = 0;
accum = default; accum = 0;
phaseaccum = default; phaseaccum = 0;
} }
} }
} }

1
AxibugEmuOnline.Client/Assets/VirtualNes.Core/CPU.cs
View File

@ -1,7 +1,6 @@
#undef DPCM_SYNCCLOCK #undef DPCM_SYNCCLOCK
using System; using System;
using VirtualNes.Core.Debug;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

2
AxibugEmuOnline.Client/Assets/VirtualNes.Core/CoreLibs/Emu2413/Emu2413.cs
View File

@ -1,6 +1,4 @@
using System; using System;
using System.Runtime.ConstrainedExecution;
using System.Runtime.Remoting.Lifetime;
namespace VirtualNes.Core.Emu2413 namespace VirtualNes.Core.Emu2413
{ {
public static class Emu2413API public static class Emu2413API

8
AxibugEmuOnline.Client/Assets/VirtualNes.Core/CoreLibs/ISoundDataBuffer.cs
View File

@ -1,10 +1,4 @@
using System; namespace VirtualNes.Core
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Threading.Tasks;
namespace VirtualNes.Core
{ {
public interface ISoundDataBuffer public interface ISoundDataBuffer
{ {

1
AxibugEmuOnline.Client/Assets/VirtualNes.Core/CoreLibs/MemoryUtility.cs
View File

@ -1,5 +1,4 @@
using System; using System;
using System.Runtime.CompilerServices;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

4
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Debuger.cs
View File

@ -1,6 +1,4 @@
using System.Collections.Generic; namespace VirtualNes.Core.Debug
namespace VirtualNes.Core.Debug
{ {
public static class Debuger public static class Debuger
{ {

3
AxibugEmuOnline.Client/Assets/VirtualNes.Core/MMU.cs
View File

@ -1,5 +1,4 @@
using System; using VirtualNes.Core;
using VirtualNes.Core;
namespace VirtualNes namespace VirtualNes
{ {

4
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/EEPROM.cs
View File

@ -1,6 +1,4 @@
using System; namespace VirtualNes.Core
namespace VirtualNes.Core
{ {

34
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper.cs
View File

@ -81,23 +81,23 @@ namespace VirtualNes.Core
{ {
//todo : 实现加载mapper //todo : 实现加载mapper
switch (no) switch (no)
{ {
case 0: return new Mapper000(parent); case 0: return new Mapper000(parent);
case 1: return new Mapper001(parent); case 1: return new Mapper001(parent);
case 2: return new Mapper002(parent); case 2: return new Mapper002(parent);
case 3: return new Mapper003(parent); case 3: return new Mapper003(parent);
case 4: return new Mapper004(parent); case 4: return new Mapper004(parent);
case 5: return new Mapper005(parent); case 5: return new Mapper005(parent);
case 6: return new Mapper006(parent); case 6: return new Mapper006(parent);
case 7: return new Mapper007(parent); case 7: return new Mapper007(parent);
case 8: return new Mapper008(parent); case 8: return new Mapper008(parent);
case 9: return new Mapper009(parent); case 9: return new Mapper009(parent);
case 10: return new Mapper010(parent); case 10: return new Mapper010(parent);
case 11: return new Mapper011(parent); case 11: return new Mapper011(parent);
case 12: return new Mapper012(parent); case 12: return new Mapper012(parent);
case 13: return new Mapper013(parent); case 13: return new Mapper013(parent);
case 15: return new Mapper015(parent); case 15: return new Mapper015(parent);
case 16: return new Mapper016(parent); case 16: return new Mapper016(parent);
case 17: return new Mapper017(parent); case 17: return new Mapper017(parent);
case 18: return new Mapper018(parent); case 18: return new Mapper018(parent);
case 19: return new Mapper019(parent); case 19: return new Mapper019(parent);

69
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper000.cs
View File

@ -2,46 +2,43 @@
// Mapper000 // // Mapper000 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper000 : Mapper public class Mapper000 : Mapper
{ {
public Mapper000(NES parent) : base(parent) { } public Mapper000(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
switch (PROM_16K_SIZE) switch (PROM_16K_SIZE)
{ {
default: default:
case 1: // 16K only case 1: // 16K only
SetPROM_16K_Bank(4, 0); SetPROM_16K_Bank(4, 0);
SetPROM_16K_Bank(6, 0); SetPROM_16K_Bank(6, 0);
break; break;
case 2: // 32K case 2: // 32K
SetPROM_32K_Bank(0); SetPROM_32K_Bank(0);
break; break;
} }
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0x4e7db5af) if (crc == 0x4e7db5af)
{ // Circus Charlie(J) { // Circus Charlie(J)
nes.SetRenderMethod(EnumRenderMethod.POST_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_RENDER);
} }
if (crc == 0x57970078) if (crc == 0x57970078)
{ // F-1 Race(J) { // F-1 Race(J)
nes.SetRenderMethod(EnumRenderMethod.POST_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_RENDER);
} }
if (crc == 0xaf2bbcbc // Mach Rider(JU) if (crc == 0xaf2bbcbc // Mach Rider(JU)
|| crc == 0x3acd4bf1) || crc == 0x3acd4bf1)
{ // Mach Rider(Alt)(JU) { // Mach Rider(Alt)(JU)
nes.SetRenderMethod(EnumRenderMethod.POST_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_RENDER);
} }
} }
} }
} }

5
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper001.cs
View File

@ -2,10 +2,9 @@
// Mapper001 Nintendo MMC1 // // Mapper001 Nintendo MMC1 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

106
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper002.cs
View File

@ -2,71 +2,69 @@
// Mapper002 UNROM // // Mapper002 UNROM //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper002 : Mapper public class Mapper002 : Mapper
{ {
BYTE patch; BYTE patch;
public Mapper002(NES parent) : base(parent) { } public Mapper002(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
patch = 0; patch = 0;
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
// if( crc == 0x322c9b09 ) { // Metal Gear (Alt)(J) // if( crc == 0x322c9b09 ) { // Metal Gear (Alt)(J)
//// nes.SetFrameIRQmode( FALSE ); //// nes.SetFrameIRQmode( FALSE );
// } // }
// if( crc == 0xe7a3867b ) { // Dragon Quest 2(Alt)(J) // if( crc == 0xe7a3867b ) { // Dragon Quest 2(Alt)(J)
// nes.SetFrameIRQmode( FALSE ); // nes.SetFrameIRQmode( FALSE );
// } // }
//// if( crc == 0x9622fbd9 ) { // Ballblazer(J) //// if( crc == 0x9622fbd9 ) { // Ballblazer(J)
//// patch = 0; //// patch = 0;
//// } //// }
if (crc == 0x8c3d54e8 // Ikari(J) if (crc == 0x8c3d54e8 // Ikari(J)
|| crc == 0x655efeed // Ikari Warriors(U) || crc == 0x655efeed // Ikari Warriors(U)
|| crc == 0x538218b2) || crc == 0x538218b2)
{ // Ikari Warriors(E) { // Ikari Warriors(E)
patch = 1; patch = 1;
} }
if (crc == 0xb20c1030) if (crc == 0xb20c1030)
{ // Shanghai(J)(original) { // Shanghai(J)(original)
patch = 2; patch = 2;
} }
} }
//void Mapper002::WriteLow(WORD addr, BYTE data) //void Mapper002::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if (!nes.rom.IsSAVERAM()) if (!nes.rom.IsSAVERAM())
{ {
if (addr >= 0x5000 && patch == 1) if (addr >= 0x5000 && patch == 1)
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
} }
else else
{ {
base.WriteLow(addr, data); base.WriteLow(addr, data);
} }
} }
//void Mapper002::Write(WORD addr, BYTE data) //void Mapper002::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
if (patch != 2) if (patch != 2)
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
else else
SetPROM_16K_Bank(4, data >> 4); SetPROM_16K_Bank(4, data >> 4);
} }
} }
} }

5
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper003.cs
View File

@ -2,10 +2,7 @@
// Mapper003 CNROM // // Mapper003 CNROM //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

5
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper004.cs
View File

@ -1,7 +1,4 @@
using Codice.CM.Client.Differences; namespace VirtualNes.Core
using System;
namespace VirtualNes.Core
{ {
public class Mapper004 : Mapper public class Mapper004 : Mapper
{ {

1
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper005.cs
View File

@ -1,7 +1,6 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper005 Nintendo MMC5 // // Mapper005 Nintendo MMC5 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using System;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using static VirtualNes.Core.PPU; using static VirtualNes.Core.PPU;
using static VirtualNes.MMU; using static VirtualNes.MMU;

178
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper006.cs
View File

@ -1,112 +1,112 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper006 FFE F4xxx // // Mapper006 FFE F4xxx //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper006 : Mapper public class Mapper006 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
INT irq_counter; INT irq_counter;
public Mapper006(NES parent) : base(parent) { } public Mapper006(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, 14, 15); SetPROM_32K_Bank(0, 1, 14, 15);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
else else
{ {
SetCRAM_8K_Bank(0); SetCRAM_8K_Bank(0);
} }
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
} }
//void Mapper006::WriteLow(WORD addr, BYTE data) //void Mapper006::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x42FE: case 0x42FE:
if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_MIRROR4H); if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_MIRROR4H);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
break; break;
case 0x42FF: case 0x42FF:
if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
case 0x4501: case 0x4501:
irq_enable = 0; irq_enable = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0x4502: case 0x4502:
irq_counter = (irq_counter & 0xFF00) | data; irq_counter = (irq_counter & 0xFF00) | data;
break; break;
case 0x4503: case 0x4503:
irq_counter = (irq_counter & 0x00FF) | ((INT)data << 8); irq_counter = (irq_counter & 0x00FF) | ((INT)data << 8);
irq_enable = 0xFF; irq_enable = 0xFF;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
default: default:
base.WriteLow(addr, data); base.WriteLow(addr, data);
break; break;
} }
} }
//void Mapper006::Write(WORD addr, BYTE data) //void Mapper006::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
SetPROM_16K_Bank(4, (data & 0x3C) >> 2); SetPROM_16K_Bank(4, (data & 0x3C) >> 2);
SetCRAM_8K_Bank(data & 0x03); SetCRAM_8K_Bank(data & 0x03);
} }
//void Mapper006::HSync(INT scanline) //void Mapper006::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
irq_counter += 133; irq_counter += 133;
if (irq_counter >= 0xFFFF) if (irq_counter >= 0xFFFF)
{ {
// nes.cpu.IRQ(); // nes.cpu.IRQ();
irq_counter = 0; irq_counter = 0;
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
//void Mapper006::SaveState(LPBYTE p) //void Mapper006::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = irq_enable; //p[0] = irq_enable;
//*(INT*)&p[1] = irq_counter; //*(INT*)&p[1] = irq_counter;
} }
//void Mapper006::LoadState(LPBYTE p) //void Mapper006::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//irq_enable = p[0]; //irq_enable = p[0];
//irq_counter = *(INT*)&p[1]; //irq_counter = *(INT*)&p[1];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

74
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper007.cs
View File

@ -2,58 +2,54 @@
// Mapper007 AOROM/AMROM // // Mapper007 AOROM/AMROM //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences;
using UnityEngine.UIElements;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper007 : Mapper public class Mapper007 : Mapper
{ {
BYTE patch; BYTE patch;
public Mapper007(NES parent) : base(parent) { } public Mapper007(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
patch = 0; patch = 0;
SetPROM_32K_Bank(0); SetPROM_32K_Bank(0);
SetVRAM_Mirror(VRAM_MIRROR4L); SetVRAM_Mirror(VRAM_MIRROR4L);
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0x3c9fe649) if (crc == 0x3c9fe649)
{ // WWF Wrestlemania Challenge(U) { // WWF Wrestlemania Challenge(U)
SetVRAM_Mirror(VRAM_VMIRROR); SetVRAM_Mirror(VRAM_VMIRROR);
patch = 1; patch = 1;
} }
if (crc == 0x09874777) if (crc == 0x09874777)
{ // Marble Madness(U) { // Marble Madness(U)
nes.SetRenderMethod( EnumRenderMethod.TILE_RENDER); nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER);
} }
if (crc == 0x279710DC // Battletoads (U) if (crc == 0x279710DC // Battletoads (U)
|| crc == 0xCEB65B06) || crc == 0xCEB65B06)
{ // Battletoads Double Dragon (U) { // Battletoads Double Dragon (U)
nes.SetRenderMethod( EnumRenderMethod.PRE_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.PRE_ALL_RENDER);
//::memset(WRAM, 0, sizeof(WRAM)); //::memset(WRAM, 0, sizeof(WRAM));
MemoryUtility.ZEROMEMORY(WRAM, WRAM.Length); MemoryUtility.ZEROMEMORY(WRAM, WRAM.Length);
} }
} }
//void Mapper007::Write(WORD addr, BYTE data) //void Mapper007::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
SetPROM_32K_Bank(data & 0x07); SetPROM_32K_Bank(data & 0x07);
if (patch!=0) if (patch != 0)
{ {
if ((data & 0x10)!=0) SetVRAM_Mirror(VRAM_MIRROR4H); if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_MIRROR4H);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
} }
} }
} }
} }

35
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper008.cs
View File

@ -2,31 +2,28 @@
// Mapper008 FFE F3xxx // // Mapper008 FFE F3xxx //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper008 : Mapper public class Mapper008 : Mapper
{ {
public Mapper008(NES parent) : base(parent) { } public Mapper008(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, 2, 3); SetPROM_32K_Bank(0, 1, 2, 3);
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
//void Mapper008::Write(WORD addr, BYTE data) //void Mapper008::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
SetPROM_16K_Bank(4, (data & 0xF8) >> 3); SetPROM_16K_Bank(4, (data & 0xF8) >> 3);
SetVROM_8K_Bank(data & 0x07); SetVROM_8K_Bank(data & 0x07);
} }
} }
} }

218
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper009.cs
View File

@ -2,128 +2,126 @@
// Mapper009 Nintendo MMC2 // // Mapper009 Nintendo MMC2 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper009 : Mapper public class Mapper009 : Mapper
{ {
BYTE[] reg = new byte[4]; BYTE[] reg = new byte[4];
BYTE latch_a, latch_b; BYTE latch_a, latch_b;
public Mapper009(NES parent) : base(parent) { } public Mapper009(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, PROM_8K_SIZE - 3, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, PROM_8K_SIZE - 3, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
reg[0] = 0; reg[1] = 4; reg[0] = 0; reg[1] = 4;
reg[2] = 0; reg[3] = 0; reg[2] = 0; reg[3] = 0;
latch_a = 0xFE; latch_a = 0xFE;
latch_b = 0xFE; latch_b = 0xFE;
SetVROM_4K_Bank(0, 4); SetVROM_4K_Bank(0, 4);
SetVROM_4K_Bank(4, 0); SetVROM_4K_Bank(4, 0);
nes.ppu.SetChrLatchMode(true); nes.ppu.SetChrLatchMode(true);
} }
//void Mapper009::Write(WORD addr, BYTE data) //void Mapper009::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF000) switch (addr & 0xF000)
{ {
case 0xA000: case 0xA000:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0xB000: case 0xB000:
reg[0] = data; reg[0] = data;
if (latch_a == 0xFD) if (latch_a == 0xFD)
{ {
SetVROM_4K_Bank(0, reg[0]); SetVROM_4K_Bank(0, reg[0]);
} }
break; break;
case 0xC000: case 0xC000:
reg[1] = data; reg[1] = data;
if (latch_a == 0xFE) if (latch_a == 0xFE)
{ {
SetVROM_4K_Bank(0, reg[1]); SetVROM_4K_Bank(0, reg[1]);
} }
break; break;
case 0xD000: case 0xD000:
reg[2] = data; reg[2] = data;
if (latch_b == 0xFD) if (latch_b == 0xFD)
{ {
SetVROM_4K_Bank(4, reg[2]); SetVROM_4K_Bank(4, reg[2]);
} }
break; break;
case 0xE000: case 0xE000:
reg[3] = data; reg[3] = data;
if (latch_b == 0xFE) if (latch_b == 0xFE)
{ {
SetVROM_4K_Bank(4, reg[3]); SetVROM_4K_Bank(4, reg[3]);
} }
break; break;
case 0xF000: case 0xF000:
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
} }
} }
//void Mapper009::PPU_ChrLatch(WORD addr) //void Mapper009::PPU_ChrLatch(WORD addr)
public override void PPU_ChrLatch(ushort addr) public override void PPU_ChrLatch(ushort addr)
{ {
if ((addr & 0x1FF0) == 0x0FD0 && latch_a != 0xFD) if ((addr & 0x1FF0) == 0x0FD0 && latch_a != 0xFD)
{ {
latch_a = 0xFD; latch_a = 0xFD;
SetVROM_4K_Bank(0, reg[0]); SetVROM_4K_Bank(0, reg[0]);
} }
else if ((addr & 0x1FF0) == 0x0FE0 && latch_a != 0xFE) else if ((addr & 0x1FF0) == 0x0FE0 && latch_a != 0xFE)
{ {
latch_a = 0xFE; latch_a = 0xFE;
SetVROM_4K_Bank(0, reg[1]); SetVROM_4K_Bank(0, reg[1]);
} }
else if ((addr & 0x1FF0) == 0x1FD0 && latch_b != 0xFD) else if ((addr & 0x1FF0) == 0x1FD0 && latch_b != 0xFD)
{ {
latch_b = 0xFD; latch_b = 0xFD;
SetVROM_4K_Bank(4, reg[2]); SetVROM_4K_Bank(4, reg[2]);
} }
else if ((addr & 0x1FF0) == 0x1FE0 && latch_b != 0xFE) else if ((addr & 0x1FF0) == 0x1FE0 && latch_b != 0xFE)
{ {
latch_b = 0xFE; latch_b = 0xFE;
SetVROM_4K_Bank(4, reg[3]); SetVROM_4K_Bank(4, reg[3]);
} }
} }
//void Mapper009::SaveState(LPBYTE p) //void Mapper009::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg[0]; p[0] = reg[0];
p[1] = reg[1]; p[1] = reg[1];
p[2] = reg[2]; p[2] = reg[2];
p[3] = reg[3]; p[3] = reg[3];
p[4] = latch_a; p[4] = latch_a;
p[5] = latch_b; p[5] = latch_b;
} }
//void Mapper009::LoadState(LPBYTE p) //void Mapper009::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg[0] = p[0]; reg[0] = p[0];
reg[1] = p[1]; reg[1] = p[1];
reg[2] = p[2]; reg[2] = p[2];
reg[3] = p[3]; reg[3] = p[3];
latch_a = p[4]; latch_a = p[4];
latch_b = p[5]; latch_b = p[5];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

220
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper010.cs
View File

@ -2,128 +2,126 @@
// Mapper010 Nintendo MMC4 // // Mapper010 Nintendo MMC4 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper010 : Mapper public class Mapper010 : Mapper
{ {
BYTE[] reg = new byte[4]; BYTE[] reg = new byte[4];
BYTE latch_a, latch_b; BYTE latch_a, latch_b;
public Mapper010(NES parent) : base(parent) { } public Mapper010(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
reg[0] = 0; reg[1] = 4; reg[0] = 0; reg[1] = 4;
reg[2] = 0; reg[3] = 0; reg[2] = 0; reg[3] = 0;
latch_a = 0xFE; latch_a = 0xFE;
latch_b = 0xFE; latch_b = 0xFE;
SetVROM_4K_Bank(0, 4); SetVROM_4K_Bank(0, 4);
SetVROM_4K_Bank(4, 0); SetVROM_4K_Bank(4, 0);
nes.ppu.SetChrLatchMode(true); nes.ppu.SetChrLatchMode(true);
} }
//void Mapper010::Write(WORD addr, BYTE data) //void Mapper010::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF000) switch (addr & 0xF000)
{ {
case 0xA000: case 0xA000:
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
break; break;
case 0xB000: case 0xB000:
reg[0] = data; reg[0] = data;
if (latch_a == 0xFD) if (latch_a == 0xFD)
{ {
SetVROM_4K_Bank(0, reg[0]); SetVROM_4K_Bank(0, reg[0]);
} }
break; break;
case 0xC000: case 0xC000:
reg[1] = data; reg[1] = data;
if (latch_a == 0xFE) if (latch_a == 0xFE)
{ {
SetVROM_4K_Bank(0, reg[1]); SetVROM_4K_Bank(0, reg[1]);
} }
break; break;
case 0xD000: case 0xD000:
reg[2] = data; reg[2] = data;
if (latch_b == 0xFD) if (latch_b == 0xFD)
{ {
SetVROM_4K_Bank(4, reg[2]); SetVROM_4K_Bank(4, reg[2]);
} }
break; break;
case 0xE000: case 0xE000:
reg[3] = data; reg[3] = data;
if (latch_b == 0xFE) if (latch_b == 0xFE)
{ {
SetVROM_4K_Bank(4, reg[3]); SetVROM_4K_Bank(4, reg[3]);
} }
break; break;
case 0xF000: case 0xF000:
if ((data & 0x01) != 0) if ((data & 0x01) != 0)
SetVRAM_Mirror(VRAM_HMIRROR); SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
} }
} }
//void Mapper010::PPU_ChrLatch(WORD addr) //void Mapper010::PPU_ChrLatch(WORD addr)
public override void PPU_ChrLatch(ushort addr) public override void PPU_ChrLatch(ushort addr)
{ {
if ((addr & 0x1FF0) == 0x0FD0 && latch_a != 0xFD) if ((addr & 0x1FF0) == 0x0FD0 && latch_a != 0xFD)
{ {
latch_a = 0xFD; latch_a = 0xFD;
SetVROM_4K_Bank(0, reg[0]); SetVROM_4K_Bank(0, reg[0]);
} }
else if ((addr & 0x1FF0) == 0x0FE0 && latch_a != 0xFE) else if ((addr & 0x1FF0) == 0x0FE0 && latch_a != 0xFE)
{ {
latch_a = 0xFE; latch_a = 0xFE;
SetVROM_4K_Bank(0, reg[1]); SetVROM_4K_Bank(0, reg[1]);
} }
else if ((addr & 0x1FF0) == 0x1FD0 && latch_b != 0xFD) else if ((addr & 0x1FF0) == 0x1FD0 && latch_b != 0xFD)
{ {
latch_b = 0xFD; latch_b = 0xFD;
SetVROM_4K_Bank(4, reg[2]); SetVROM_4K_Bank(4, reg[2]);
} }
else if ((addr & 0x1FF0) == 0x1FE0 && latch_b != 0xFE) else if ((addr & 0x1FF0) == 0x1FE0 && latch_b != 0xFE)
{ {
latch_b = 0xFE; latch_b = 0xFE;
SetVROM_4K_Bank(4, reg[3]); SetVROM_4K_Bank(4, reg[3]);
} }
} }
//void Mapper010::SaveState(LPBYTE p) //void Mapper010::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg[0]; p[0] = reg[0];
p[1] = reg[1]; p[1] = reg[1];
p[2] = reg[2]; p[2] = reg[2];
p[3] = reg[3]; p[3] = reg[3];
p[4] = latch_a; p[4] = latch_a;
p[5] = latch_b; p[5] = latch_b;
} }
//void Mapper010::LoadState(LPBYTE p) //void Mapper010::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg[0] = p[0]; reg[0] = p[0];
reg[1] = p[1]; reg[1] = p[1];
reg[2] = p[2]; reg[2] = p[2];
reg[3] = p[3]; reg[3] = p[3];
latch_a = p[4]; latch_a = p[4];
latch_b = p[5]; latch_b = p[5];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

53
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper011.cs
View File

@ -2,41 +2,38 @@
// Mapper011 Color Dreams // // Mapper011 Color Dreams //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper011 : Mapper public class Mapper011 : Mapper
{ {
public Mapper011(NES parent) : base(parent) { } public Mapper011(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0); SetPROM_32K_Bank(0);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
// SetVROM_8K_Bank( 1 ); // SetVROM_8K_Bank( 1 );
} }
SetVRAM_Mirror(VRAM_VMIRROR); SetVRAM_Mirror(VRAM_VMIRROR);
} }
//void Mapper011::Write(WORD addr, BYTE data) //void Mapper011::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
//DEBUGOUT("WR A:%04X D:%02X\n", addr, data); //DEBUGOUT("WR A:%04X D:%02X\n", addr, data);
SetPROM_32K_Bank(data); SetPROM_32K_Bank(data);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(data >> 4); SetVROM_8K_Bank(data >> 4);
} }
} }
} }
} }

612
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper012.cs
View File

@ -1,331 +1,331 @@
using static VirtualNes.MMU; using static VirtualNes.Core.CPU;
using static VirtualNes.Core.CPU; using static VirtualNes.MMU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper012 : Mapper public class Mapper012 : Mapper
{ {
uint vb0, vb1; uint vb0, vb1;
BYTE[] reg = new byte[8]; BYTE[] reg = new byte[8];
BYTE prg0, prg1; BYTE prg0, prg1;
BYTE chr01, chr23, chr4, chr5, chr6, chr7; BYTE chr01, chr23, chr4, chr5, chr6, chr7;
BYTE we_sram; BYTE we_sram;
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
BYTE irq_request; BYTE irq_request;
BYTE irq_preset; BYTE irq_preset;
BYTE irq_preset_vbl; BYTE irq_preset_vbl;
public Mapper012(NES parent) : base(parent) { } public Mapper012(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
reg[i] = 0x00; reg[i] = 0x00;
} }
prg0 = 0; prg0 = 0;
prg1 = 1; prg1 = 1;
SetBank_CPU(); SetBank_CPU();
vb0 = 0; vb0 = 0;
vb1 = 0; vb1 = 0;
chr01 = 0; chr01 = 0;
chr23 = 2; chr23 = 2;
chr4 = 4; chr4 = 4;
chr5 = 5; chr5 = 5;
chr6 = 6; chr6 = 6;
chr7 = 7; chr7 = 7;
SetBank_PPU(); SetBank_PPU();
we_sram = 0; // Disable we_sram = 0; // Disable
irq_enable = 0; // Disable irq_enable = 0; // Disable
irq_counter = 0; irq_counter = 0;
irq_latch = 0xFF; irq_latch = 0xFF;
irq_request = 0; irq_request = 0;
irq_preset = 0; irq_preset = 0;
irq_preset_vbl = 0; irq_preset_vbl = 0;
} }
//void Mapper012::WriteLow(WORD addr, BYTE data) //void Mapper012::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if (addr > 0x4100 && addr < 0x6000) if (addr > 0x4100 && addr < 0x6000)
{ {
vb0 = (byte)((data & 0x01) << 8); vb0 = (byte)((data & 0x01) << 8);
vb1 = (byte)((data & 0x10) << 4); vb1 = (byte)((data & 0x10) << 4);
SetBank_PPU(); SetBank_PPU();
} }
else else
{ {
base.WriteLow(addr, data); base.WriteLow(addr, data);
} }
} }
//BYTE Mapper012::ReadLow(WORD addr) //BYTE Mapper012::ReadLow(WORD addr)
public override byte ReadLow(ushort addr) public override byte ReadLow(ushort addr)
{ {
return 0x01; return 0x01;
} }
//void Mapper012::Write(WORD addr, BYTE data) //void Mapper012::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() ); //DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() );
switch (addr & 0xE001) switch (addr & 0xE001)
{ {
case 0x8000: case 0x8000:
reg[0] = data; reg[0] = data;
SetBank_CPU(); SetBank_CPU();
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x8001: case 0x8001:
reg[1] = data; reg[1] = data;
switch (reg[0] & 0x07) switch (reg[0] & 0x07)
{ {
case 0x00: case 0x00:
chr01 = (byte)(data & 0xFE); chr01 = (byte)(data & 0xFE);
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x01: case 0x01:
chr23 = (byte)(data & 0xFE); chr23 = (byte)(data & 0xFE);
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x02: case 0x02:
chr4 = data; chr4 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x03: case 0x03:
chr5 = data; chr5 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x04: case 0x04:
chr6 = data; chr6 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x05: case 0x05:
chr7 = data; chr7 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x06: case 0x06:
prg0 = data; prg0 = data;
SetBank_CPU(); SetBank_CPU();
break; break;
case 0x07: case 0x07:
prg1 = data; prg1 = data;
SetBank_CPU(); SetBank_CPU();
break; break;
} }
break; break;
case 0xA000: case 0xA000:
reg[2] = data; reg[2] = data;
if (!nes.rom.Is4SCREEN()) if (!nes.rom.Is4SCREEN())
{ {
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
} }
break; break;
case 0xA001: case 0xA001:
reg[3] = data; reg[3] = data;
break; break;
case 0xC000: case 0xC000:
reg[4] = data; reg[4] = data;
irq_latch = data; irq_latch = data;
break; break;
case 0xC001: case 0xC001:
reg[5] = data; reg[5] = data;
if (nes.GetScanline() < 240) if (nes.GetScanline() < 240)
{ {
irq_counter |= 0x80; irq_counter |= 0x80;
irq_preset = 0xFF; irq_preset = 0xFF;
} }
else else
{ {
irq_counter |= 0x80; irq_counter |= 0x80;
irq_preset_vbl = 0xFF; irq_preset_vbl = 0xFF;
irq_preset = 0; irq_preset = 0;
} }
break; break;
case 0xE000: case 0xE000:
reg[6] = data; reg[6] = data;
irq_enable = 0; irq_enable = 0;
irq_request = 0; irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xE001: case 0xE001:
reg[7] = data; reg[7] = data;
irq_enable = 1; irq_enable = 1;
irq_request = 0; irq_request = 0;
break; break;
} }
} }
//void Mapper012::HSync(INT scanline) //void Mapper012::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if ((scanline >= 0 && scanline <= 239) && nes.ppu.IsDispON()) if ((scanline >= 0 && scanline <= 239) && nes.ppu.IsDispON())
{ {
if (irq_preset_vbl != 0) if (irq_preset_vbl != 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
irq_preset_vbl = 0; irq_preset_vbl = 0;
} }
if (irq_preset != 0) if (irq_preset != 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
irq_preset = 0; irq_preset = 0;
} }
else if (irq_counter > 0) else if (irq_counter > 0)
{ {
irq_counter--; irq_counter--;
} }
if (irq_counter == 0) if (irq_counter == 0)
{ {
// Some game set irq_latch to zero to disable irq. So check it here. // Some game set irq_latch to zero to disable irq. So check it here.
if (irq_enable != 0 && irq_latch != 0) if (irq_enable != 0 && irq_latch != 0)
{ {
irq_request = 0xFF; irq_request = 0xFF;
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
irq_preset = 0xFF; irq_preset = 0xFF;
} }
} }
} }
void SetBank_CPU() void SetBank_CPU()
{ {
if ((reg[0] & 0x40) != 0) if ((reg[0] & 0x40) != 0)
{ {
SetPROM_32K_Bank(PROM_8K_SIZE - 2, prg1, prg0, PROM_8K_SIZE - 1); SetPROM_32K_Bank(PROM_8K_SIZE - 2, prg1, prg0, PROM_8K_SIZE - 1);
} }
else else
{ {
SetPROM_32K_Bank(prg0, prg1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(prg0, prg1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
} }
} }
void SetBank_PPU() void SetBank_PPU()
{ {
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
if ((reg[0] & 0x80) != 0) if ((reg[0] & 0x80) != 0)
{ {
SetVROM_8K_Bank( SetVROM_8K_Bank(
(int)(vb0 + chr4), (int)(vb0 + chr4),
(int)(vb0 + chr5), (int)(vb0 + chr5),
(int)(vb0 + chr6), (int)(vb0 + chr6),
(int)(vb0 + chr7), (int)(vb0 + chr7),
(int)(vb1 + chr01), (int)(vb1 + chr01),
(int)(vb1 + chr01 + 1), (int)(vb1 + chr01 + 1),
(int)(vb1 + chr23), (int)(vb1 + chr23),
(int)(vb1 + chr23 + 1) (int)(vb1 + chr23 + 1)
); );
} }
else else
{ {
SetVROM_8K_Bank( SetVROM_8K_Bank(
(int)(vb0 + chr01), (int)(vb0 + chr01),
(int)(vb0 + chr01 + 1), (int)(vb0 + chr01 + 1),
(int)(vb0 + chr23), (int)(vb0 + chr23),
(int)(vb0 + chr23 + 1), (int)(vb0 + chr23 + 1),
(int)(vb1 + chr4), (int)(vb1 + chr4),
(int)(vb1 + chr5), (int)(vb1 + chr5),
(int)(vb1 + chr6), (int)(vb1 + chr6),
(int)(vb1 + chr7)) (int)(vb1 + chr7))
; ;
} }
} }
else else
{ {
if ((reg[0] & 0x80) != 0) if ((reg[0] & 0x80) != 0)
{ {
SetCRAM_1K_Bank(4, (chr01 + 0) & 0x07); SetCRAM_1K_Bank(4, (chr01 + 0) & 0x07);
SetCRAM_1K_Bank(5, (chr01 + 1) & 0x07); SetCRAM_1K_Bank(5, (chr01 + 1) & 0x07);
SetCRAM_1K_Bank(6, (chr23 + 0) & 0x07); SetCRAM_1K_Bank(6, (chr23 + 0) & 0x07);
SetCRAM_1K_Bank(7, (chr23 + 1) & 0x07); SetCRAM_1K_Bank(7, (chr23 + 1) & 0x07);
SetCRAM_1K_Bank(0, chr4 & 0x07); SetCRAM_1K_Bank(0, chr4 & 0x07);
SetCRAM_1K_Bank(1, chr5 & 0x07); SetCRAM_1K_Bank(1, chr5 & 0x07);
SetCRAM_1K_Bank(2, chr6 & 0x07); SetCRAM_1K_Bank(2, chr6 & 0x07);
SetCRAM_1K_Bank(3, chr7 & 0x07); SetCRAM_1K_Bank(3, chr7 & 0x07);
} }
else else
{ {
SetCRAM_1K_Bank(0, (chr01 + 0) & 0x07); SetCRAM_1K_Bank(0, (chr01 + 0) & 0x07);
SetCRAM_1K_Bank(1, (chr01 + 1) & 0x07); SetCRAM_1K_Bank(1, (chr01 + 1) & 0x07);
SetCRAM_1K_Bank(2, (chr23 + 0) & 0x07); SetCRAM_1K_Bank(2, (chr23 + 0) & 0x07);
SetCRAM_1K_Bank(3, (chr23 + 1) & 0x07); SetCRAM_1K_Bank(3, (chr23 + 1) & 0x07);
SetCRAM_1K_Bank(4, chr4 & 0x07); SetCRAM_1K_Bank(4, chr4 & 0x07);
SetCRAM_1K_Bank(5, chr5 & 0x07); SetCRAM_1K_Bank(5, chr5 & 0x07);
SetCRAM_1K_Bank(6, chr6 & 0x07); SetCRAM_1K_Bank(6, chr6 & 0x07);
SetCRAM_1K_Bank(7, chr7 & 0x07); SetCRAM_1K_Bank(7, chr7 & 0x07);
} }
} }
} }
//void Mapper012::SaveState(LPBYTE p) //void Mapper012::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//for (INT i = 0; i < 8; i++) //for (INT i = 0; i < 8; i++)
//{ //{
// p[i] = reg[i]; // p[i] = reg[i];
//} //}
//p[8] = prg0; //p[8] = prg0;
//p[9] = prg1; //p[9] = prg1;
//p[10] = chr01; //p[10] = chr01;
//p[11] = chr23; //p[11] = chr23;
//p[12] = chr4; //p[12] = chr4;
//p[13] = chr5; //p[13] = chr5;
//p[14] = chr6; //p[14] = chr6;
//p[15] = chr7; //p[15] = chr7;
//p[16] = irq_enable; //p[16] = irq_enable;
//p[17] = (BYTE)irq_counter; //p[17] = (BYTE)irq_counter;
//p[18] = irq_latch; //p[18] = irq_latch;
//p[19] = irq_request; //p[19] = irq_request;
//p[20] = irq_preset; //p[20] = irq_preset;
//p[21] = irq_preset_vbl; //p[21] = irq_preset_vbl;
//*((DWORD*)&p[22]) = vb0; //*((DWORD*)&p[22]) = vb0;
//*((DWORD*)&p[26]) = vb1; //*((DWORD*)&p[26]) = vb1;
} }
//void Mapper012::LoadState(LPBYTE p) //void Mapper012::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//for (INT i = 0; i < 8; i++) //for (INT i = 0; i < 8; i++)
//{ //{
// reg[i] = p[i]; // reg[i] = p[i];
//} //}
//prg0 = p[8]; //prg0 = p[8];
//prg1 = p[9]; //prg1 = p[9];
//chr01 = p[10]; //chr01 = p[10];
//chr23 = p[11]; //chr23 = p[11];
//chr4 = p[12]; //chr4 = p[12];
//chr5 = p[13]; //chr5 = p[13];
//chr6 = p[14]; //chr6 = p[14];
//chr7 = p[15]; //chr7 = p[15];
//irq_enable = p[16]; //irq_enable = p[16];
//irq_counter = (INT)p[17]; //irq_counter = (INT)p[17];
//irq_latch = p[18]; //irq_latch = p[18];
//irq_request = p[19]; //irq_request = p[19];
//irq_preset = p[20]; //irq_preset = p[20];
//irq_preset_vbl = p[21]; //irq_preset_vbl = p[21];
//vb0 = *((DWORD*)&p[22]); //vb0 = *((DWORD*)&p[22]);
//vb1 = *((DWORD*)&p[26]); //vb1 = *((DWORD*)&p[26]);
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

37
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper013.cs
View File

@ -2,32 +2,29 @@
// Mapper013 CPROM // // Mapper013 CPROM //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper013 : Mapper public class Mapper013 : Mapper
{ {
public Mapper013(NES parent) : base(parent) { } public Mapper013(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, 2, 3); SetPROM_32K_Bank(0, 1, 2, 3);
SetCRAM_4K_Bank(0, 0); SetCRAM_4K_Bank(0, 0);
SetCRAM_4K_Bank(4, 0); SetCRAM_4K_Bank(4, 0);
} }
//void Mapper013::Write(WORD addr, BYTE data) //void Mapper013::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
SetPROM_32K_Bank((data & 0x30) >> 4); SetPROM_32K_Bank((data & 0x30) >> 4);
SetCRAM_4K_Bank(4, data & 0x03); SetCRAM_4K_Bank(4, data & 0x03);
} }
} }
} }

157
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper015.cs
View File

@ -2,92 +2,89 @@
// Mapper015 100-in-1 chip // // Mapper015 100-in-1 chip //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper015 : Mapper public class Mapper015 : Mapper
{ {
public Mapper015(NES parent) : base(parent) { } public Mapper015(NES parent) : base(parent) { }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, 2, 3); SetPROM_32K_Bank(0, 1, 2, 3);
} }
//void Mapper015::Write(WORD addr, BYTE data) //void Mapper015::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
if ((data & 0x80) != 0) if ((data & 0x80) != 0)
{ {
SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 1); SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 1);
SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 0); SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 0);
SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 3); SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 3);
SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 2); SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 2);
} }
else else
{ {
SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 0); SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 0);
SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 1); SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 1);
SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 2); SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 2);
SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 3); SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 3);
} }
if ((data & 0x40) != 0) if ((data & 0x40) != 0)
SetVRAM_Mirror(VRAM_HMIRROR); SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
case 0x8001: case 0x8001:
if ((data & 0x80) != 0) if ((data & 0x80) != 0)
{ {
SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 1); SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 1);
SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 0); SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 0);
} }
else else
{ {
SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 0); SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 0);
SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 1); SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 1);
} }
break; break;
case 0x8002: case 0x8002:
if ((data & 0x80) != 0) if ((data & 0x80) != 0)
{ {
SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 1); SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 1);
SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 1); SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 1);
SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 1); SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 1);
SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 1); SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 1);
} }
else else
{ {
SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 0); SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 0);
SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 0); SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 0);
SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 0); SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 0);
SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 0); SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 0);
} }
break; break;
case 0x8003: case 0x8003:
if ((data & 0x80) != 0) if ((data & 0x80) != 0)
{ {
SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 1); SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 1);
SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 0); SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 0);
} }
else else
{ {
SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 0); SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 0);
SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 1); SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 1);
} }
if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
} }
} }
} }
} }

214
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper017.cs
View File

@ -1,127 +1,127 @@
using static VirtualNes.MMU; using static VirtualNes.Core.CPU;
using static VirtualNes.Core.CPU; using static VirtualNes.MMU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper017 : Mapper public class Mapper017 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
INT irq_counter; INT irq_counter;
INT irq_latch; INT irq_latch;
public Mapper017(NES parent) : base(parent) public Mapper017(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
} }
//void Mapper017::WriteLow(WORD addr, BYTE data) //void Mapper017::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x42FE: case 0x42FE:
if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_MIRROR4H); if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_MIRROR4H);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
break; break;
case 0x42FF: case 0x42FF:
if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
case 0x4501: case 0x4501:
irq_enable = 0; irq_enable = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0x4502: case 0x4502:
irq_latch = (irq_latch & 0xFF00) | data; irq_latch = (irq_latch & 0xFF00) | data;
break; break;
case 0x4503: case 0x4503:
irq_latch = (irq_latch & 0x00FF) | ((INT)data << 8); irq_latch = (irq_latch & 0x00FF) | ((INT)data << 8);
irq_counter = irq_latch; irq_counter = irq_latch;
irq_enable = 0xFF; irq_enable = 0xFF;
break; break;
case 0x4504: case 0x4504:
case 0x4505: case 0x4505:
case 0x4506: case 0x4506:
case 0x4507: case 0x4507:
SetPROM_8K_Bank((byte)(addr & 0x07), data); SetPROM_8K_Bank((byte)(addr & 0x07), data);
break; break;
case 0x4510: case 0x4510:
case 0x4511: case 0x4511:
case 0x4512: case 0x4512:
case 0x4513: case 0x4513:
case 0x4514: case 0x4514:
case 0x4515: case 0x4515:
case 0x4516: case 0x4516:
case 0x4517: case 0x4517:
SetVROM_1K_Bank((byte)(addr & 0x07), data); SetVROM_1K_Bank((byte)(addr & 0x07), data);
break; break;
default: default:
base.WriteLow(addr, data); base.WriteLow(addr, data);
break; break;
} }
} }
//void Mapper017::HSync(INT scanline) //void Mapper017::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if (irq_counter >= 0xFFFF - 113) if (irq_counter >= 0xFFFF - 113)
{ {
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
// nes.cpu.IRQ(); // nes.cpu.IRQ();
// irq_counter = 0; // irq_counter = 0;
// irq_enable = 0; // irq_enable = 0;
irq_counter &= 0xFFFF; irq_counter &= 0xFFFF;
} }
else else
{ {
irq_counter += 113; irq_counter += 113;
} }
} }
} }
//void Mapper017::SaveState(LPBYTE p) //void Mapper017::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = irq_enable; //p[0] = irq_enable;
//*(INT*)&p[1] = irq_counter; //*(INT*)&p[1] = irq_counter;
//*(INT*)&p[5] = irq_latch; //*(INT*)&p[5] = irq_latch;
} }
//void Mapper017::LoadState(LPBYTE p) //void Mapper017::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//irq_enable = p[0]; //irq_enable = p[0];
//irq_counter = *(INT*)&p[1]; //irq_counter = *(INT*)&p[1];
//irq_latch = *(INT*)&p[5]; //irq_latch = *(INT*)&p[5];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

488
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper018.cs
View File

@ -1,278 +1,278 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper018 Jaleco SS8806 // // Mapper018 Jaleco SS8806 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper018 : Mapper public class Mapper018 : Mapper
{ {
BYTE[] reg = new byte[11]; BYTE[] reg = new byte[11];
BYTE irq_enable; BYTE irq_enable;
BYTE irq_mode; BYTE irq_mode;
INT irq_latch; INT irq_latch;
INT irq_counter; INT irq_counter;
public Mapper018(NES parent) : base(parent) public Mapper018(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
for (INT i = 0; i < 11; i++) for (INT i = 0; i < 11; i++)
{ {
reg[i] = 0; reg[i] = 0;
} }
reg[2] = (byte)(PROM_8K_SIZE - 2); reg[2] = (byte)(PROM_8K_SIZE - 2);
reg[3] = (byte)(PROM_8K_SIZE - 1); reg[3] = (byte)(PROM_8K_SIZE - 1);
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
irq_enable = 0; irq_enable = 0;
irq_mode = 0; irq_mode = 0;
irq_counter = 0xFFFF; irq_counter = 0xFFFF;
irq_latch = 0xFFFF; irq_latch = 0xFFFF;
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0xefb1df9e) if (crc == 0xefb1df9e)
{ // The Lord of King(J) { // The Lord of King(J)
nes.SetRenderMethod(EnumRenderMethod.PRE_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.PRE_ALL_RENDER);
} }
if (crc == 0x3746f951) if (crc == 0x3746f951)
{ // Pizza Pop!(J) { // Pizza Pop!(J)
nes.SetRenderMethod(EnumRenderMethod.PRE_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.PRE_ALL_RENDER);
} }
// nes.SetRenderMethod( NES::PRE_ALL_RENDER ); // nes.SetRenderMethod( NES::PRE_ALL_RENDER );
// nes.SetRenderMethod( NES::POST_ALL_RENDER ); // nes.SetRenderMethod( NES::POST_ALL_RENDER );
} }
//void Mapper018::Write(WORD addr, BYTE data) //void Mapper018::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
reg[0] = (byte)((reg[0] & 0xF0) | (data & 0x0F)); reg[0] = (byte)((reg[0] & 0xF0) | (data & 0x0F));
SetPROM_8K_Bank(4, reg[0]); SetPROM_8K_Bank(4, reg[0]);
break; break;
case 0x8001: case 0x8001:
reg[0] = (byte)((reg[0] & 0x0F) | ((data & 0x0F) << 4)); reg[0] = (byte)((reg[0] & 0x0F) | ((data & 0x0F) << 4));
SetPROM_8K_Bank(4, reg[0]); SetPROM_8K_Bank(4, reg[0]);
break; break;
case 0x8002: case 0x8002:
reg[1] = (byte)((reg[1] & 0xF0) | (data & 0x0F)); reg[1] = (byte)((reg[1] & 0xF0) | (data & 0x0F));
SetPROM_8K_Bank(5, reg[1]); SetPROM_8K_Bank(5, reg[1]);
break; break;
case 0x8003: case 0x8003:
reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x0F) << 4)); reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x0F) << 4));
SetPROM_8K_Bank(5, reg[1]); SetPROM_8K_Bank(5, reg[1]);
break; break;
case 0x9000: case 0x9000:
reg[2] = (byte)((reg[2] & 0xF0) | (data & 0x0F)); reg[2] = (byte)((reg[2] & 0xF0) | (data & 0x0F));
SetPROM_8K_Bank(6, reg[2]); SetPROM_8K_Bank(6, reg[2]);
break; break;
case 0x9001: case 0x9001:
reg[2] = (byte)((reg[2] & 0x0F) | ((data & 0x0F) << 4)); reg[2] = (byte)((reg[2] & 0x0F) | ((data & 0x0F) << 4));
SetPROM_8K_Bank(6, reg[2]); SetPROM_8K_Bank(6, reg[2]);
break; break;
case 0xA000: case 0xA000:
reg[3] = (byte)((reg[3] & 0xF0) | (data & 0x0F)); reg[3] = (byte)((reg[3] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(0, reg[3]); SetVROM_1K_Bank(0, reg[3]);
break; break;
case 0xA001: case 0xA001:
reg[3] = (byte)((reg[3] & 0x0F) | ((data & 0x0F) << 4)); reg[3] = (byte)((reg[3] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(0, reg[3]); SetVROM_1K_Bank(0, reg[3]);
break; break;
case 0xA002: case 0xA002:
reg[4] = (byte)((reg[4] & 0xF0) | (data & 0x0F)); reg[4] = (byte)((reg[4] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(1, reg[4]); SetVROM_1K_Bank(1, reg[4]);
break; break;
case 0xA003: case 0xA003:
reg[4] = (byte)((reg[4] & 0x0F) | ((data & 0x0F) << 4)); reg[4] = (byte)((reg[4] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(1, reg[4]); SetVROM_1K_Bank(1, reg[4]);
break; break;
case 0xB000: case 0xB000:
reg[5] = (byte)((reg[5] & 0xF0) | (data & 0x0F)); reg[5] = (byte)((reg[5] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(2, reg[5]); SetVROM_1K_Bank(2, reg[5]);
break; break;
case 0xB001: case 0xB001:
reg[5] = (byte)((reg[5] & 0x0F) | ((data & 0x0F) << 4)); reg[5] = (byte)((reg[5] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(2, reg[5]); SetVROM_1K_Bank(2, reg[5]);
break; break;
case 0xB002: case 0xB002:
reg[6] = (byte)((reg[6] & 0xF0) | (data & 0x0F)); reg[6] = (byte)((reg[6] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(3, reg[6]); SetVROM_1K_Bank(3, reg[6]);
break; break;
case 0xB003: case 0xB003:
reg[6] = (byte)((reg[6] & 0x0F) | ((data & 0x0F) << 4)); reg[6] = (byte)((reg[6] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(3, reg[6]); SetVROM_1K_Bank(3, reg[6]);
break; break;
case 0xC000: case 0xC000:
reg[7] = (byte)((reg[7] & 0xF0) | (data & 0x0F)); reg[7] = (byte)((reg[7] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(4, reg[7]); SetVROM_1K_Bank(4, reg[7]);
break; break;
case 0xC001: case 0xC001:
reg[7] = (byte)((reg[7] & 0x0F) | ((data & 0x0F) << 4)); reg[7] = (byte)((reg[7] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(4, reg[7]); SetVROM_1K_Bank(4, reg[7]);
break; break;
case 0xC002: case 0xC002:
reg[8] = (byte)((reg[8] & 0xF0) | (data & 0x0F)); reg[8] = (byte)((reg[8] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(5, reg[8]); SetVROM_1K_Bank(5, reg[8]);
break; break;
case 0xC003: case 0xC003:
reg[8] = (byte)((reg[8] & 0x0F) | ((data & 0x0F) << 4)); reg[8] = (byte)((reg[8] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(5, reg[8]); SetVROM_1K_Bank(5, reg[8]);
break; break;
case 0xD000: case 0xD000:
reg[9] = (byte)((reg[9] & 0xF0) | (data & 0x0F)); reg[9] = (byte)((reg[9] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(6, reg[9]); SetVROM_1K_Bank(6, reg[9]);
break; break;
case 0xD001: case 0xD001:
reg[9] = (byte)((reg[9] & 0x0F) | ((data & 0x0F) << 4)); reg[9] = (byte)((reg[9] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(6, reg[9]); SetVROM_1K_Bank(6, reg[9]);
break; break;
case 0xD002: case 0xD002:
reg[10] = (byte)((reg[10] & 0xF0) | (data & 0x0F)); reg[10] = (byte)((reg[10] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(7, reg[10]); SetVROM_1K_Bank(7, reg[10]);
break; break;
case 0xD003: case 0xD003:
reg[10] = (byte)((reg[10] & 0x0F) | ((data & 0x0F) << 4)); reg[10] = (byte)((reg[10] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(7, reg[10]); SetVROM_1K_Bank(7, reg[10]);
break; break;
case 0xE000: case 0xE000:
irq_latch = (irq_latch & 0xFFF0) | (data & 0x0F); irq_latch = (irq_latch & 0xFFF0) | (data & 0x0F);
break; break;
case 0xE001: case 0xE001:
irq_latch = (irq_latch & 0xFF0F) | ((data & 0x0F) << 4); irq_latch = (irq_latch & 0xFF0F) | ((data & 0x0F) << 4);
break; break;
case 0xE002: case 0xE002:
irq_latch = (irq_latch & 0xF0FF) | ((data & 0x0F) << 8); irq_latch = (irq_latch & 0xF0FF) | ((data & 0x0F) << 8);
break; break;
case 0xE003: case 0xE003:
irq_latch = (irq_latch & 0x0FFF) | ((data & 0x0F) << 12); irq_latch = (irq_latch & 0x0FFF) | ((data & 0x0F) << 12);
break; break;
case 0xF000: case 0xF000:
// if( data & 0x01 ) { // if( data & 0x01 ) {
irq_counter = irq_latch; irq_counter = irq_latch;
// } else { // } else {
// irq_counter = 0; // irq_counter = 0;
// } // }
break; break;
case 0xF001: case 0xF001:
irq_mode = (byte)((data >> 1) & 0x07); irq_mode = (byte)((data >> 1) & 0x07);
irq_enable = ((byte)(data & 0x01)); irq_enable = ((byte)(data & 0x01));
// if( !irq_enable ) { // if( !irq_enable ) {
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
// } // }
break; break;
case 0xF002: case 0xF002:
data &= 0x03; data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_HMIRROR); if (data == 0) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_VMIRROR); else if (data == 1) SetVRAM_Mirror(VRAM_VMIRROR);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
break; break;
} }
} }
//void Mapper018::Clock(INT cycles) //void Mapper018::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
bool bIRQ = false; bool bIRQ = false;
INT irq_counter_old = irq_counter; INT irq_counter_old = irq_counter;
if (irq_enable != 0 && irq_counter != 0) if (irq_enable != 0 && irq_counter != 0)
{ {
irq_counter -= cycles; irq_counter -= cycles;
switch (irq_mode) switch (irq_mode)
{ {
case 0: case 0:
if (irq_counter <= 0) if (irq_counter <= 0)
{ {
bIRQ = true; bIRQ = true;
} }
break; break;
case 1: case 1:
if ((irq_counter & 0xF000) != (irq_counter_old & 0xF000)) if ((irq_counter & 0xF000) != (irq_counter_old & 0xF000))
{ {
bIRQ = true; bIRQ = true;
} }
break; break;
case 2: case 2:
case 3: case 3:
if ((irq_counter & 0xFF00) != (irq_counter_old & 0xFF00)) if ((irq_counter & 0xFF00) != (irq_counter_old & 0xFF00))
{ {
bIRQ = true; bIRQ = true;
} }
break; break;
case 4: case 4:
case 5: case 5:
case 6: case 6:
case 7: case 7:
if ((irq_counter & 0xFFF0) != (irq_counter_old & 0xFFF0)) if ((irq_counter & 0xFFF0) != (irq_counter_old & 0xFFF0))
{ {
bIRQ = true; bIRQ = true;
} }
break; break;
} }
if (bIRQ) if (bIRQ)
{ {
//// irq_enable = 0; //// irq_enable = 0;
// irq_counter = irq_latch; // irq_counter = irq_latch;
irq_counter = 0; irq_counter = 0;
irq_enable = 0; irq_enable = 0;
// nes.cpu.IRQ_NotPending(); // nes.cpu.IRQ_NotPending();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
//void Mapper018::SaveState(LPBYTE p) //void Mapper018::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//for (INT i = 0; i < 11; i++) //for (INT i = 0; i < 11; i++)
//{ //{
// p[i] = reg[i]; // p[i] = reg[i];
//} //}
//p[11] = irq_enable; //p[11] = irq_enable;
//p[12] = irq_mode; //p[12] = irq_mode;
//*(INT*)&p[13] = irq_counter; //*(INT*)&p[13] = irq_counter;
//*(INT*)&p[17] = irq_latch; //*(INT*)&p[17] = irq_latch;
} }
//void Mapper018::LoadState(LPBYTE p) //void Mapper018::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//for (INT i = 0; i < 11; i++) //for (INT i = 0; i < 11; i++)
//{ //{
// p[i] = reg[i]; // p[i] = reg[i];
//} //}
//irq_enable = p[11]; //irq_enable = p[11];
//irq_mode = p[12]; //irq_mode = p[12];
//irq_counter = *(INT*)&p[13]; //irq_counter = *(INT*)&p[13];
//irq_latch = *(INT*)&p[17]; //irq_latch = *(INT*)&p[17];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

5
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper019.cs
View File

@ -1,11 +1,10 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper019 Namcot 106 // // Mapper019 Namcot 106 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

438
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper021.cs
View File

@ -1,255 +1,255 @@
////////////////// //////////////////
// Mapper021 Konami VRC4 (Address mask $F006 or $F0C0) // // Mapper021 Konami VRC4 (Address mask $F006 or $F0C0) //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper021 : Mapper public class Mapper021 : Mapper
{ {
BYTE[] reg = new byte[9]; BYTE[] reg = new byte[9];
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
INT irq_clock; INT irq_clock;
public Mapper021(NES parent) : base(parent) public Mapper021(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
for (byte i = 0; i < 8; i++) for (byte i = 0; i < 8; i++)
{ {
reg[i] = i; reg[i] = i;
} }
reg[8] = 0; reg[8] = 0;
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
irq_clock = 0; irq_clock = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
} }
//void Mapper021::Write(WORD addr, BYTE data) //void Mapper021::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF0CF) switch (addr & 0xF0CF)
{ {
case 0x8000: case 0x8000:
if ((reg[8] & 0x02) != 0) if ((reg[8] & 0x02) != 0)
{ {
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
} }
else else
{ {
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
} }
break; break;
case 0xA000: case 0xA000:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0x9000: case 0x9000:
data &= 0x03; data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR); if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L); else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L);
else SetVRAM_Mirror(VRAM_MIRROR4H); else SetVRAM_Mirror(VRAM_MIRROR4H);
break; break;
case 0x9002: case 0x9002:
case 0x9080: case 0x9080:
reg[8] = data; reg[8] = data;
break; break;
case 0xB000: case 0xB000:
reg[0] = (byte)((reg[0] & 0xF0) | (data & 0x0F)); reg[0] = (byte)((reg[0] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(0, reg[0]); SetVROM_1K_Bank(0, reg[0]);
break; break;
case 0xB002: case 0xB002:
case 0xB040: case 0xB040:
reg[0] = (byte)((reg[0] & 0x0F) | ((data & 0x0F) << 4)); reg[0] = (byte)((reg[0] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(0, reg[0]); SetVROM_1K_Bank(0, reg[0]);
break; break;
case 0xB001: case 0xB001:
case 0xB004: case 0xB004:
case 0xB080: case 0xB080:
reg[1] = (byte)((reg[1] & 0xF0) | (data & 0x0F)); reg[1] = (byte)((reg[1] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(1, reg[1]); SetVROM_1K_Bank(1, reg[1]);
break; break;
case 0xB003: case 0xB003:
case 0xB006: case 0xB006:
case 0xB0C0: case 0xB0C0:
reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x0F) << 4)); reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(1, reg[1]); SetVROM_1K_Bank(1, reg[1]);
break; break;
case 0xC000: case 0xC000:
reg[2] = (byte)((reg[2] & 0xF0) | (data & 0x0F)); reg[2] = (byte)((reg[2] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(2, reg[2]); SetVROM_1K_Bank(2, reg[2]);
break; break;
case 0xC002: case 0xC002:
case 0xC040: case 0xC040:
reg[2] = (byte)((reg[2] & 0x0F) | ((data & 0x0F) << 4)); reg[2] = (byte)((reg[2] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(2, reg[2]); SetVROM_1K_Bank(2, reg[2]);
break; break;
case 0xC001: case 0xC001:
case 0xC004: case 0xC004:
case 0xC080: case 0xC080:
reg[3] = (byte)((reg[3] & 0xF0) | (data & 0x0F)); reg[3] = (byte)((reg[3] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(3, reg[3]); SetVROM_1K_Bank(3, reg[3]);
break; break;
case 0xC003: case 0xC003:
case 0xC006: case 0xC006:
case 0xC0C0: case 0xC0C0:
reg[3] = (byte)((reg[3] & 0x0F) | ((data & 0x0F) << 4)); reg[3] = (byte)((reg[3] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(3, reg[3]); SetVROM_1K_Bank(3, reg[3]);
break; break;
case 0xD000: case 0xD000:
reg[4] = (byte)((reg[4] & 0xF0) | (data & 0x0F)); reg[4] = (byte)((reg[4] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(4, reg[4]); SetVROM_1K_Bank(4, reg[4]);
break; break;
case 0xD002: case 0xD002:
case 0xD040: case 0xD040:
reg[4] = (byte)((reg[4] & 0x0F) | ((data & 0x0F) << 4)); reg[4] = (byte)((reg[4] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(4, reg[4]); SetVROM_1K_Bank(4, reg[4]);
break; break;
case 0xD001: case 0xD001:
case 0xD004: case 0xD004:
case 0xD080: case 0xD080:
reg[5] = (byte)((reg[5] & 0xF0) | (data & 0x0F)); reg[5] = (byte)((reg[5] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(5, reg[5]); SetVROM_1K_Bank(5, reg[5]);
break; break;
case 0xD003: case 0xD003:
case 0xD006: case 0xD006:
case 0xD0C0: case 0xD0C0:
reg[5] = (byte)((reg[5] & 0x0F) | ((data & 0x0F) << 4)); reg[5] = (byte)((reg[5] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(5, reg[5]); SetVROM_1K_Bank(5, reg[5]);
break; break;
case 0xE000: case 0xE000:
reg[6] = (byte)((reg[6] & 0xF0) | (data & 0x0F)); reg[6] = (byte)((reg[6] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(6, reg[6]); SetVROM_1K_Bank(6, reg[6]);
break; break;
case 0xE002: case 0xE002:
case 0xE040: case 0xE040:
reg[6] = (byte)((reg[6] & 0x0F) | ((data & 0x0F) << 4)); reg[6] = (byte)((reg[6] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(6, reg[6]); SetVROM_1K_Bank(6, reg[6]);
break; break;
case 0xE001: case 0xE001:
case 0xE004: case 0xE004:
case 0xE080: case 0xE080:
reg[7] = (byte)((reg[7] & 0xF0) | (data & 0x0F)); reg[7] = (byte)((reg[7] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(7, reg[7]); SetVROM_1K_Bank(7, reg[7]);
break; break;
case 0xE003: case 0xE003:
case 0xE006: case 0xE006:
case 0xE0C0: case 0xE0C0:
reg[7] = (byte)((reg[7] & 0x0F) | ((data & 0x0F) << 4)); reg[7] = (byte)((reg[7] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(7, reg[7]); SetVROM_1K_Bank(7, reg[7]);
break; break;
case 0xF000: case 0xF000:
irq_latch = (byte)((irq_latch & 0xF0) | (data & 0x0F)); irq_latch = (byte)((irq_latch & 0xF0) | (data & 0x0F));
break; break;
case 0xF002: case 0xF002:
case 0xF040: case 0xF040:
irq_latch = (byte)((irq_latch & 0x0F) | ((data & 0x0F) << 4)); irq_latch = (byte)((irq_latch & 0x0F) | ((data & 0x0F) << 4));
break; break;
case 0xF003: case 0xF003:
case 0xF0C0: case 0xF0C0:
case 0xF006: case 0xF006:
irq_enable = (byte)((irq_enable & 0x01) * 3); irq_enable = (byte)((irq_enable & 0x01) * 3);
irq_clock = 0; irq_clock = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF004: case 0xF004:
case 0xF080: case 0xF080:
irq_enable = (byte)(data & 0x03); irq_enable = (byte)(data & 0x03);
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
irq_clock = 0; irq_clock = 0;
} }
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
// case 0xF006: // case 0xF006:
// nes.cpu.ClrIRQ( IRQ_MAPPER ); // nes.cpu.ClrIRQ( IRQ_MAPPER );
// break; // break;
} }
} }
//void Mapper021::Clock(INT cycles) //void Mapper021::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
if ((irq_clock -= cycles) < 0) if ((irq_clock -= cycles) < 0)
{ {
irq_clock += 0x72; irq_clock += 0x72;
if (irq_counter == 0xFF) if (irq_counter == 0xFF)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
// irq_enable = (irq_enable & 0x01) * 3; // irq_enable = (irq_enable & 0x01) * 3;
// nes.cpu.IRQ_NotPending(); // nes.cpu.IRQ_NotPending();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
else else
{ {
irq_counter++; irq_counter++;
} }
} }
} }
} }
//void Mapper021::SaveState(LPBYTE p) //void Mapper021::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//for (INT i = 0; i < 9; i++) //for (INT i = 0; i < 9; i++)
//{ //{
// p[i] = reg[i]; // p[i] = reg[i];
//} //}
//p[9] = irq_enable; //p[9] = irq_enable;
//p[10] = irq_counter; //p[10] = irq_counter;
//p[11] = irq_latch; //p[11] = irq_latch;
//*(INT*)&p[12] = irq_clock; //*(INT*)&p[12] = irq_clock;
} }
//void Mapper021::LoadState(LPBYTE p) //void Mapper021::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//for (INT i = 0; i < 9; i++) //for (INT i = 0; i < 9; i++)
//{ //{
// reg[i] = p[i]; // reg[i] = p[i];
//} //}
//irq_enable = p[9]; //irq_enable = p[9];
//irq_counter = p[10]; //irq_counter = p[10];
//irq_latch = p[11]; //irq_latch = p[11];
//irq_clock = *(INT*)&p[12]; //irq_clock = *(INT*)&p[12];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

113
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper022.cs
View File

@ -2,80 +2,77 @@
// Mapper022 Konami VRC2 type A // // Mapper022 Konami VRC2 type A //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper022 : Mapper public class Mapper022 : Mapper
{ {
public Mapper022(NES parent) : base(parent) public Mapper022(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
} }
//void Mapper022::Write(WORD addr, BYTE data) //void Mapper022::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0x9000: case 0x9000:
data &= 0x03; data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR); if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4H); else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4H);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
break; break;
case 0xA000: case 0xA000:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0xB000: case 0xB000:
SetVROM_1K_Bank(0, data >> 1); SetVROM_1K_Bank(0, data >> 1);
break; break;
case 0xB001: case 0xB001:
SetVROM_1K_Bank(1, data >> 1); SetVROM_1K_Bank(1, data >> 1);
break; break;
case 0xC000: case 0xC000:
SetVROM_1K_Bank(2, data >> 1); SetVROM_1K_Bank(2, data >> 1);
break; break;
case 0xC001: case 0xC001:
SetVROM_1K_Bank(3, data >> 1); SetVROM_1K_Bank(3, data >> 1);
break; break;
case 0xD000: case 0xD000:
SetVROM_1K_Bank(4, data >> 1); SetVROM_1K_Bank(4, data >> 1);
break; break;
case 0xD001: case 0xD001:
SetVROM_1K_Bank(5, data >> 1); SetVROM_1K_Bank(5, data >> 1);
break; break;
case 0xE000: case 0xE000:
SetVROM_1K_Bank(6, data >> 1); SetVROM_1K_Bank(6, data >> 1);
break; break;
case 0xE001: case 0xE001:
SetVROM_1K_Bank(7, data >> 1); SetVROM_1K_Bank(7, data >> 1);
break; break;
} }
} }
} }
} }

448
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper023.cs
View File

@ -1,271 +1,271 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper023 Konami VRC2 type B // // Mapper023 Konami VRC2 type B //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper023 : Mapper public class Mapper023 : Mapper
{ {
ushort addrmask; ushort addrmask;
BYTE[] reg = new byte[9]; BYTE[] reg = new byte[9];
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
INT irq_clock; INT irq_clock;
public Mapper023(NES parent) : base(parent) public Mapper023(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
addrmask = 0xFFFF; addrmask = 0xFFFF;
for (byte i = 0; i < 8; i++) for (byte i = 0; i < 8; i++)
{ {
reg[i] = i; reg[i] = i;
} }
reg[8] = 0; reg[8] = 0;
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
irq_clock = 0; irq_clock = 0;
reg[9] = 1; reg[9] = 1;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
// nes.SetRenderMethod( NES::POST_RENDER ); // nes.SetRenderMethod( NES::POST_RENDER );
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0x93794634 // Akumajou Special Boku Dracula Kun(J) if (crc == 0x93794634 // Akumajou Special Boku Dracula Kun(J)
|| crc == 0xc7829dae // Akumajou Special Boku Dracula Kun(T-Eng) || crc == 0xc7829dae // Akumajou Special Boku Dracula Kun(T-Eng)
|| crc == 0xf82dc02f) || crc == 0xf82dc02f)
{ // Akumajou Special Boku Dracula Kun(T-Eng v1.02) { // Akumajou Special Boku Dracula Kun(T-Eng v1.02)
addrmask = 0xF00C; addrmask = 0xF00C;
nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER);
} }
if (crc == 0xdd53c4ae) if (crc == 0xdd53c4ae)
{ // Tiny Toon Adventures(J) { // Tiny Toon Adventures(J)
nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER);
} }
} }
//void Mapper023::Write(WORD addr, BYTE data) //void Mapper023::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() ); //DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() );
switch (addr & addrmask) switch (addr & addrmask)
{ {
case 0x8000: case 0x8000:
case 0x8004: case 0x8004:
case 0x8008: case 0x8008:
case 0x800C: case 0x800C:
if (reg[8] != 0) if (reg[8] != 0)
{ {
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
} }
else else
{ {
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
} }
break; break;
case 0x9000: case 0x9000:
if (data != 0xFF) if (data != 0xFF)
{ {
data &= 0x03; data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR); if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L); else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L);
else SetVRAM_Mirror(VRAM_MIRROR4H); else SetVRAM_Mirror(VRAM_MIRROR4H);
} }
break; break;
case 0x9008: case 0x9008:
reg[8] = (byte)(data & 0x02); reg[8] = (byte)(data & 0x02);
break; break;
case 0xA000: case 0xA000:
case 0xA004: case 0xA004:
case 0xA008: case 0xA008:
case 0xA00C: case 0xA00C:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0xB000: case 0xB000:
reg[0] = (byte)((reg[0] & 0xF0) | (data & 0x0F)); reg[0] = (byte)((reg[0] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(0, reg[0]); SetVROM_1K_Bank(0, reg[0]);
break; break;
case 0xB001: case 0xB001:
case 0xB004: case 0xB004:
reg[0] = ((byte)((reg[0] & 0x0F) | ((data & 0x0F) << 4))); reg[0] = ((byte)((reg[0] & 0x0F) | ((data & 0x0F) << 4)));
SetVROM_1K_Bank(0, reg[0]); SetVROM_1K_Bank(0, reg[0]);
break; break;
case 0xB002: case 0xB002:
case 0xB008: case 0xB008:
reg[1] = (byte)((reg[1] & 0xF0) | (data & 0x0F)); reg[1] = (byte)((reg[1] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(1, reg[1]); SetVROM_1K_Bank(1, reg[1]);
break; break;
case 0xB003: case 0xB003:
case 0xB00C: case 0xB00C:
reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x0F) << 4)); reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(1, reg[1]); SetVROM_1K_Bank(1, reg[1]);
break; break;
case 0xC000: case 0xC000:
reg[2] = (byte)((reg[2] & 0xF0) | (data & 0x0F)); reg[2] = (byte)((reg[2] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(2, reg[2]); SetVROM_1K_Bank(2, reg[2]);
break; break;
case 0xC001: case 0xC001:
case 0xC004: case 0xC004:
reg[2] = (byte)((reg[2] & 0x0F) | ((data & 0x0F) << 4)); reg[2] = (byte)((reg[2] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(2, reg[2]); SetVROM_1K_Bank(2, reg[2]);
break; break;
case 0xC002: case 0xC002:
case 0xC008: case 0xC008:
reg[3] = (byte)((reg[3] & 0xF0) | (data & 0x0F)); reg[3] = (byte)((reg[3] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(3, reg[3]); SetVROM_1K_Bank(3, reg[3]);
break; break;
case 0xC003: case 0xC003:
case 0xC00C: case 0xC00C:
reg[3] = (byte)((reg[3] & 0x0F) | ((data & 0x0F) << 4)); reg[3] = (byte)((reg[3] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(3, reg[3]); SetVROM_1K_Bank(3, reg[3]);
break; break;
case 0xD000: case 0xD000:
reg[4] = (byte)((reg[4] & 0xF0) | (data & 0x0F)); reg[4] = (byte)((reg[4] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(4, reg[4]); SetVROM_1K_Bank(4, reg[4]);
break; break;
case 0xD001: case 0xD001:
case 0xD004: case 0xD004:
reg[4] = (byte)((reg[4] & 0x0F) | ((data & 0x0F) << 4)); reg[4] = (byte)((reg[4] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(4, reg[4]); SetVROM_1K_Bank(4, reg[4]);
break; break;
case 0xD002: case 0xD002:
case 0xD008: case 0xD008:
reg[5] = (byte)((reg[5] & 0xF0) | (data & 0x0F)); reg[5] = (byte)((reg[5] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(5, reg[5]); SetVROM_1K_Bank(5, reg[5]);
break; break;
case 0xD003: case 0xD003:
case 0xD00C: case 0xD00C:
reg[5] = (byte)((reg[5] & 0x0F) | ((data & 0x0F) << 4)); reg[5] = (byte)((reg[5] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(5, reg[5]); SetVROM_1K_Bank(5, reg[5]);
break; break;
case 0xE000: case 0xE000:
reg[6] = (byte)((reg[6] & 0xF0) | (data & 0x0F)); reg[6] = (byte)((reg[6] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(6, reg[6]); SetVROM_1K_Bank(6, reg[6]);
break; break;
case 0xE001: case 0xE001:
case 0xE004: case 0xE004:
reg[6] = (byte)((reg[6] & 0x0F) | ((data & 0x0F) << 4)); reg[6] = (byte)((reg[6] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(6, reg[6]); SetVROM_1K_Bank(6, reg[6]);
break; break;
case 0xE002: case 0xE002:
case 0xE008: case 0xE008:
reg[7] = (byte)((reg[7] & 0xF0) | (data & 0x0F)); reg[7] = (byte)((reg[7] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(7, reg[7]); SetVROM_1K_Bank(7, reg[7]);
break; break;
case 0xE003: case 0xE003:
case 0xE00C: case 0xE00C:
reg[7] = ((byte)((reg[7] & 0x0F) | ((data & 0x0F) << 4))); reg[7] = ((byte)((reg[7] & 0x0F) | ((data & 0x0F) << 4)));
SetVROM_1K_Bank(7, reg[7]); SetVROM_1K_Bank(7, reg[7]);
break; break;
case 0xF000: case 0xF000:
irq_latch = (byte)((irq_latch & 0xF0) | (data & 0x0F)); irq_latch = (byte)((irq_latch & 0xF0) | (data & 0x0F));
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF004: case 0xF004:
irq_latch = (byte)((irq_latch & 0x0F) | ((data & 0x0F) << 4)); irq_latch = (byte)((irq_latch & 0x0F) | ((data & 0x0F) << 4));
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF008: case 0xF008:
irq_enable = (byte)(data & 0x03); irq_enable = (byte)(data & 0x03);
irq_counter = irq_latch; irq_counter = irq_latch;
irq_clock = 0; irq_clock = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF00C: case 0xF00C:
irq_enable = (byte)((irq_enable & 0x01) * 3); irq_enable = (byte)((irq_enable & 0x01) * 3);
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
} }
} }
//void Mapper023::Clock(INT cycles) //void Mapper023::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
irq_clock += cycles * 3; irq_clock += cycles * 3;
while (irq_clock >= 341) while (irq_clock >= 341)
{ {
irq_clock -= 341; irq_clock -= 341;
irq_counter++; irq_counter++;
if (irq_counter == 0) if (irq_counter == 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
} }
//void Mapper023::SaveState(LPBYTE p) //void Mapper023::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//for (INT i = 0; i < 9; i++) //for (INT i = 0; i < 9; i++)
//{ //{
// p[i] = reg[i]; // p[i] = reg[i];
//} //}
//p[9] = irq_enable; //p[9] = irq_enable;
//p[10] = irq_counter; //p[10] = irq_counter;
//p[11] = irq_latch; //p[11] = irq_latch;
//*(INT*)&p[12] = irq_clock; //*(INT*)&p[12] = irq_clock;
} }
//void Mapper023::LoadState(LPBYTE p) //void Mapper023::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//for (INT i = 0; i < 9; i++) //for (INT i = 0; i < 9; i++)
//{ //{
// reg[i] = p[i]; // reg[i] = p[i];
//} //}
//irq_enable = p[9]; //irq_enable = p[9];
//irq_counter = p[10]; //irq_counter = p[10];
//irq_latch = p[11]; //irq_latch = p[11];
//irq_clock = *(INT*)&p[12]; //irq_clock = *(INT*)&p[12];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

280
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper024.cs
View File

@ -1,174 +1,174 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper024 Konami VRC6 (Normal) // // Mapper024 Konami VRC6 (Normal) //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper024 : Mapper public class Mapper024 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
INT irq_clock; INT irq_clock;
public Mapper024(NES parent) : base(parent) public Mapper024(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
irq_clock = 0; irq_clock = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
nes.SetRenderMethod(EnumRenderMethod.POST_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_RENDER);
// nes.SetRenderMethod( NES::PRE_RENDER ); // nes.SetRenderMethod( NES::PRE_RENDER );
nes.apu.SelectExSound(1); nes.apu.SelectExSound(1);
} }
//void Mapper024::Write(WORD addr, BYTE data) //void Mapper024::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF003) switch (addr & 0xF003)
{ {
case 0x8000: case 0x8000:
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
break; break;
case 0x9000: case 0x9000:
case 0x9001: case 0x9001:
case 0x9002: case 0x9002:
case 0xA000: case 0xA000:
case 0xA001: case 0xA001:
case 0xA002: case 0xA002:
case 0xB000: case 0xB000:
case 0xB001: case 0xB001:
case 0xB002: case 0xB002:
nes.apu.ExWrite(addr, data); nes.apu.ExWrite(addr, data);
break; break;
case 0xB003: case 0xB003:
data = (byte)(data & 0x0C); data = (byte)(data & 0x0C);
if (data == 0x00) SetVRAM_Mirror(VRAM_VMIRROR); if (data == 0x00) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 0x04) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 0x04) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 0x08) SetVRAM_Mirror(VRAM_MIRROR4L); else if (data == 0x08) SetVRAM_Mirror(VRAM_MIRROR4L);
else if (data == 0x0C) SetVRAM_Mirror(VRAM_MIRROR4H); else if (data == 0x0C) SetVRAM_Mirror(VRAM_MIRROR4H);
break; break;
case 0xC000: case 0xC000:
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
break; break;
case 0xD000: case 0xD000:
SetVROM_1K_Bank(0, data); SetVROM_1K_Bank(0, data);
break; break;
case 0xD001: case 0xD001:
SetVROM_1K_Bank(1, data); SetVROM_1K_Bank(1, data);
break; break;
case 0xD002: case 0xD002:
SetVROM_1K_Bank(2, data); SetVROM_1K_Bank(2, data);
break; break;
case 0xD003: case 0xD003:
SetVROM_1K_Bank(3, data); SetVROM_1K_Bank(3, data);
break; break;
case 0xE000: case 0xE000:
SetVROM_1K_Bank(4, data); SetVROM_1K_Bank(4, data);
break; break;
case 0xE001: case 0xE001:
SetVROM_1K_Bank(5, data); SetVROM_1K_Bank(5, data);
break; break;
case 0xE002: case 0xE002:
SetVROM_1K_Bank(6, data); SetVROM_1K_Bank(6, data);
break; break;
case 0xE003: case 0xE003:
SetVROM_1K_Bank(7, data); SetVROM_1K_Bank(7, data);
break; break;
case 0xF000: case 0xF000:
irq_latch = data; irq_latch = data;
break; break;
case 0xF001: case 0xF001:
irq_enable = (byte)(data & 0x03); irq_enable = (byte)(data & 0x03);
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
irq_clock = 0; irq_clock = 0;
} }
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF002: case 0xF002:
irq_enable = (byte)((irq_enable & 0x01) * 3); irq_enable = (byte)((irq_enable & 0x01) * 3);
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
} }
} }
//void Mapper024::Clock(INT cycles) //void Mapper024::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
if ((irq_clock += cycles) >= 0x72) if ((irq_clock += cycles) >= 0x72)
{ {
irq_clock -= 0x72; irq_clock -= 0x72;
if (irq_counter == 0xFF) if (irq_counter == 0xFF)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
// nes.cpu.IRQ_NotPending(); // nes.cpu.IRQ_NotPending();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
else else
{ {
irq_counter++; irq_counter++;
} }
} }
} }
} }
//void Mapper024::SaveState(LPBYTE p) //void Mapper024::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = irq_enable; //p[0] = irq_enable;
//p[1] = irq_counter; //p[1] = irq_counter;
//p[2] = irq_latch; //p[2] = irq_latch;
//*(INT*)&p[3] = irq_clock; //*(INT*)&p[3] = irq_clock;
} }
//void Mapper024::LoadState(LPBYTE p) //void Mapper024::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//irq_enable = p[0]; //irq_enable = p[0];
//irq_counter = p[1]; //irq_counter = p[1];
//irq_latch = p[2]; //irq_latch = p[2];
//irq_clock = *(INT*)&p[3]; //irq_clock = *(INT*)&p[3];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

482
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper025.cs
View File

@ -1,278 +1,278 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper025 Konami VRC4 (Normal) // // Mapper025 Konami VRC4 (Normal) //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper025 : Mapper public class Mapper025 : Mapper
{ {
BYTE[] reg = new byte[11]; BYTE[] reg = new byte[11];
BYTE irq_enable; BYTE irq_enable;
BYTE irq_latch; BYTE irq_latch;
BYTE irq_occur; BYTE irq_occur;
BYTE irq_counter; BYTE irq_counter;
INT irq_clock; INT irq_clock;
public Mapper025(NES parent) : base(parent) public Mapper025(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
for (INT i = 0; i < 11; i++) for (INT i = 0; i < 11; i++)
{ {
reg[i] = 0; reg[i] = 0;
} }
reg[9] = (byte)(PROM_8K_SIZE - 2); reg[9] = (byte)(PROM_8K_SIZE - 2);
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
irq_occur = 0; irq_occur = 0;
irq_clock = 0; irq_clock = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0xc71d4ce7) if (crc == 0xc71d4ce7)
{ // Gradius II(J) { // Gradius II(J)
// nes.SetRenderMethod( NES::POST_RENDER ); // nes.SetRenderMethod( NES::POST_RENDER );
} }
if (crc == 0xa2e68da8) if (crc == 0xa2e68da8)
{ // For Racer Mini Yonku - Japan Cup(J) { // For Racer Mini Yonku - Japan Cup(J)
nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER); nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER);
} }
if (crc == 0xea74c587) if (crc == 0xea74c587)
{ // For Teenage Mutant Ninja Turtles(J) { // For Teenage Mutant Ninja Turtles(J)
nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER); nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER);
} }
if (crc == 0x5f82cb7d) if (crc == 0x5f82cb7d)
{ // For Teenage Mutant Ninja Turtles 2(J) { // For Teenage Mutant Ninja Turtles 2(J)
} }
if (crc == 0x0bbd85ff) if (crc == 0x0bbd85ff)
{ // For Bio Miracle Bokutte Upa(J) { // For Bio Miracle Bokutte Upa(J)
nes.SetRenderMethod(EnumRenderMethod.PRE_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.PRE_ALL_RENDER);
} }
} }
//void Mapper025::Write(WORD addr, BYTE data) //void Mapper025::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
//if( addr >= 0xF000 ) //if( addr >= 0xF000 )
//DEBUGOUT( "M25 WR $%04X=$%02X L=%3d\n", addr, data, nes.GetScanline() ); //DEBUGOUT( "M25 WR $%04X=$%02X L=%3d\n", addr, data, nes.GetScanline() );
switch (addr & 0xF000) switch (addr & 0xF000)
{ {
case 0x8000: case 0x8000:
if ((reg[10] & 0x02) != 0) if ((reg[10] & 0x02) != 0)
{ {
reg[9] = data; reg[9] = data;
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
} }
else else
{ {
reg[8] = data; reg[8] = data;
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
} }
break; break;
case 0xA000: case 0xA000:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
} }
switch (addr & 0xF00F) switch (addr & 0xF00F)
{ {
case 0x9000: case 0x9000:
data &= 0x03; data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR); if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L); else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L);
else SetVRAM_Mirror(VRAM_MIRROR4H); else SetVRAM_Mirror(VRAM_MIRROR4H);
break; break;
case 0x9001: case 0x9001:
case 0x9004: case 0x9004:
if ((reg[10] & 0x02) != (data & 0x02)) if ((reg[10] & 0x02) != (data & 0x02))
{ {
BYTE swap = reg[8]; BYTE swap = reg[8];
reg[8] = reg[9]; reg[8] = reg[9];
reg[9] = swap; reg[9] = swap;
SetPROM_8K_Bank(4, reg[8]); SetPROM_8K_Bank(4, reg[8]);
SetPROM_8K_Bank(6, reg[9]); SetPROM_8K_Bank(6, reg[9]);
} }
reg[10] = data; reg[10] = data;
break; break;
case 0xB000: case 0xB000:
reg[0] = (byte)((reg[0] & 0xF0) | (data & 0x0F)); reg[0] = (byte)((reg[0] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(0, reg[0]); SetVROM_1K_Bank(0, reg[0]);
break; break;
case 0xB002: case 0xB002:
case 0xB008: case 0xB008:
reg[0] = (byte)((reg[0] & 0x0F) | ((data & 0x0F) << 4)); reg[0] = (byte)((reg[0] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(0, reg[0]); SetVROM_1K_Bank(0, reg[0]);
break; break;
case 0xB001: case 0xB001:
case 0xB004: case 0xB004:
reg[1] = (byte)((reg[1] & 0xF0) | (data & 0x0F)); reg[1] = (byte)((reg[1] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(1, reg[1]); SetVROM_1K_Bank(1, reg[1]);
break; break;
case 0xB003: case 0xB003:
case 0xB00C: case 0xB00C:
reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x0F) << 4)); reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(1, reg[1]); SetVROM_1K_Bank(1, reg[1]);
break; break;
case 0xC000: case 0xC000:
reg[2] = (byte)((reg[2] & 0xF0) | (data & 0x0F)); reg[2] = (byte)((reg[2] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(2, reg[2]); SetVROM_1K_Bank(2, reg[2]);
break; break;
case 0xC002: case 0xC002:
case 0xC008: case 0xC008:
reg[2] = (byte)((reg[2] & 0x0F) | ((data & 0x0F) << 4)); reg[2] = (byte)((reg[2] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(2, reg[2]); SetVROM_1K_Bank(2, reg[2]);
break; break;
case 0xC001: case 0xC001:
case 0xC004: case 0xC004:
reg[3] = (byte)((reg[3] & 0xF0) | (data & 0x0F)); reg[3] = (byte)((reg[3] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(3, reg[3]); SetVROM_1K_Bank(3, reg[3]);
break; break;
case 0xC003: case 0xC003:
case 0xC00C: case 0xC00C:
reg[3] = (byte)((reg[3] & 0x0F) | ((data & 0x0F) << 4)); reg[3] = (byte)((reg[3] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(3, reg[3]); SetVROM_1K_Bank(3, reg[3]);
break; break;
case 0xD000: case 0xD000:
reg[4] = (byte)((reg[4] & 0xF0) | (data & 0x0F)); reg[4] = (byte)((reg[4] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(4, reg[4]); SetVROM_1K_Bank(4, reg[4]);
break; break;
case 0xD002: case 0xD002:
case 0xD008: case 0xD008:
reg[4] = (byte)((reg[4] & 0x0F) | ((data & 0x0F) << 4)); reg[4] = (byte)((reg[4] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(4, reg[4]); SetVROM_1K_Bank(4, reg[4]);
break; break;
case 0xD001: case 0xD001:
case 0xD004: case 0xD004:
reg[5] = (byte)((reg[5] & 0xF0) | (data & 0x0F)); reg[5] = (byte)((reg[5] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(5, reg[5]); SetVROM_1K_Bank(5, reg[5]);
break; break;
case 0xD003: case 0xD003:
case 0xD00C: case 0xD00C:
reg[5] = (byte)((reg[5] & 0x0F) | ((data & 0x0F) << 4)); reg[5] = (byte)((reg[5] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(5, reg[5]); SetVROM_1K_Bank(5, reg[5]);
break; break;
case 0xE000: case 0xE000:
reg[6] = (byte)((reg[6] & 0xF0) | (data & 0x0F)); reg[6] = (byte)((reg[6] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(6, reg[6]); SetVROM_1K_Bank(6, reg[6]);
break; break;
case 0xE002: case 0xE002:
case 0xE008: case 0xE008:
reg[6] = (byte)((reg[6] & 0x0F) | ((data & 0x0F) << 4)); reg[6] = (byte)((reg[6] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(6, reg[6]); SetVROM_1K_Bank(6, reg[6]);
break; break;
case 0xE001: case 0xE001:
case 0xE004: case 0xE004:
reg[7] = (byte)((reg[7] & 0xF0) | (data & 0x0F)); reg[7] = (byte)((reg[7] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(7, reg[7]); SetVROM_1K_Bank(7, reg[7]);
break; break;
case 0xE003: case 0xE003:
case 0xE00C: case 0xE00C:
reg[7] = (byte)((reg[7] & 0x0F) | ((data & 0x0F) << 4)); reg[7] = (byte)((reg[7] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(7, reg[7]); SetVROM_1K_Bank(7, reg[7]);
break; break;
case 0xF000: case 0xF000:
irq_latch = (byte)((irq_latch & 0xF0) | (data & 0x0F)); irq_latch = (byte)((irq_latch & 0xF0) | (data & 0x0F));
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF002: case 0xF002:
case 0xF008: case 0xF008:
irq_latch = (byte)((irq_latch & 0x0F) | ((data & 0x0F) << 4)); irq_latch = (byte)((irq_latch & 0x0F) | ((data & 0x0F) << 4));
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF001: case 0xF001:
case 0xF004: case 0xF004:
irq_enable = (byte)(data & 0x03); irq_enable = (byte)(data & 0x03);
// irq_counter = 0x100 - irq_latch; // irq_counter = 0x100 - irq_latch;
irq_counter = irq_latch; irq_counter = irq_latch;
irq_clock = 0; irq_clock = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF003: case 0xF003:
case 0xF00C: case 0xF00C:
irq_enable = (byte)((irq_enable & 0x01) * 3); irq_enable = (byte)((irq_enable & 0x01) * 3);
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
} }
} }
//void Mapper025::Clock(INT cycles) //void Mapper025::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
irq_clock += cycles * 3; irq_clock += cycles * 3;
while (irq_clock >= 341) while (irq_clock >= 341)
{ {
irq_clock -= 341; irq_clock -= 341;
irq_counter++; irq_counter++;
if (irq_counter == 0) if (irq_counter == 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
} }
//void Mapper025::SaveState(LPBYTE p) //void Mapper025::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//for (INT i = 0; i < 11; i++) //for (INT i = 0; i < 11; i++)
//{ //{
// p[i] = reg[i]; // p[i] = reg[i];
//} //}
//p[11] = irq_enable; //p[11] = irq_enable;
//p[12] = irq_occur; //p[12] = irq_occur;
//p[13] = irq_latch; //p[13] = irq_latch;
//p[14] = irq_counter; //p[14] = irq_counter;
//*((INT*)&p[15]) = irq_clock; //*((INT*)&p[15]) = irq_clock;
} }
//void Mapper025::LoadState(LPBYTE p) //void Mapper025::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//for (INT i = 0; i < 11; i++) //for (INT i = 0; i < 11; i++)
//{ //{
// reg[i] = p[i]; // reg[i] = p[i];
//} //}
//irq_enable = p[11]; //irq_enable = p[11];
//irq_occur = p[12]; //irq_occur = p[12];
//irq_latch = p[13]; //irq_latch = p[13];
//irq_counter = p[14]; //irq_counter = p[14];
//irq_clock = *((INT*)&p[15]); //irq_clock = *((INT*)&p[15]);
} }
} }
} }

302
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper026.cs
View File

@ -1,185 +1,185 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper026 Konami VRC6 (PA0,PA1 reverse) // // Mapper026 Konami VRC6 (PA0,PA1 reverse) //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper026 : Mapper public class Mapper026 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
INT irq_clock; INT irq_clock;
public Mapper026(NES parent) : base(parent) public Mapper026(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
irq_clock = 0; irq_clock = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0x30e64d03) if (crc == 0x30e64d03)
{ // Esper Dream 2 - Aratanaru Tatakai(J) { // Esper Dream 2 - Aratanaru Tatakai(J)
nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER);
} }
if (crc == 0x836cc1ab) if (crc == 0x836cc1ab)
{ // Mouryou Senki Madara(J) { // Mouryou Senki Madara(J)
nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER);
} }
nes.apu.SelectExSound(1); nes.apu.SelectExSound(1);
} }
//void Mapper026::Write(WORD addr, BYTE data) //void Mapper026::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF003) switch (addr & 0xF003)
{ {
case 0x8000: case 0x8000:
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
break; break;
case 0x9000: case 0x9000:
case 0x9001: case 0x9001:
case 0x9002: case 0x9002:
case 0x9003: case 0x9003:
case 0xA000: case 0xA000:
case 0xA001: case 0xA001:
case 0xA002: case 0xA002:
case 0xA003: case 0xA003:
case 0xB000: case 0xB000:
case 0xB001: case 0xB001:
case 0xB002: case 0xB002:
addr = (ushort)((addr & 0xfffc) | ((addr & 1) << 1) | ((addr & 2) >> 1)); addr = (ushort)((addr & 0xfffc) | ((addr & 1) << 1) | ((addr & 2) >> 1));
nes.apu.ExWrite(addr, data); nes.apu.ExWrite(addr, data);
break; break;
case 0xB003: case 0xB003:
data = (byte)(data & 0x7F); data = (byte)(data & 0x7F);
if (data == 0x08 || data == 0x2C) SetVRAM_Mirror(VRAM_MIRROR4H); if (data == 0x08 || data == 0x2C) SetVRAM_Mirror(VRAM_MIRROR4H);
else if (data == 0x20) SetVRAM_Mirror(VRAM_VMIRROR); else if (data == 0x20) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 0x24) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 0x24) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 0x28) SetVRAM_Mirror(VRAM_MIRROR4L); else if (data == 0x28) SetVRAM_Mirror(VRAM_MIRROR4L);
break; break;
case 0xC000: case 0xC000:
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
break; break;
case 0xD000: case 0xD000:
SetVROM_1K_Bank(0, data); SetVROM_1K_Bank(0, data);
break; break;
case 0xD001: case 0xD001:
SetVROM_1K_Bank(2, data); SetVROM_1K_Bank(2, data);
break; break;
case 0xD002: case 0xD002:
SetVROM_1K_Bank(1, data); SetVROM_1K_Bank(1, data);
break; break;
case 0xD003: case 0xD003:
SetVROM_1K_Bank(3, data); SetVROM_1K_Bank(3, data);
break; break;
case 0xE000: case 0xE000:
SetVROM_1K_Bank(4, data); SetVROM_1K_Bank(4, data);
break; break;
case 0xE001: case 0xE001:
SetVROM_1K_Bank(6, data); SetVROM_1K_Bank(6, data);
break; break;
case 0xE002: case 0xE002:
SetVROM_1K_Bank(5, data); SetVROM_1K_Bank(5, data);
break; break;
case 0xE003: case 0xE003:
SetVROM_1K_Bank(7, data); SetVROM_1K_Bank(7, data);
break; break;
case 0xF000: case 0xF000:
irq_latch = data; irq_latch = data;
break; break;
case 0xF001: case 0xF001:
irq_enable = (byte)((irq_enable & 0x01) * 3); irq_enable = (byte)((irq_enable & 0x01) * 3);
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF002: case 0xF002:
irq_enable = (byte)(data & 0x03); irq_enable = (byte)(data & 0x03);
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
irq_clock = 0; irq_clock = 0;
} }
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
} }
} }
//void Mapper026::Clock(INT cycles) //void Mapper026::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
if ((irq_clock += cycles) >= 0x72) if ((irq_clock += cycles) >= 0x72)
{ {
irq_clock -= 0x72; irq_clock -= 0x72;
if (irq_counter >= 0xFF) if (irq_counter >= 0xFF)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
// nes.cpu.IRQ_NotPending(); // nes.cpu.IRQ_NotPending();
//// nes.cpu.IRQ(); //// nes.cpu.IRQ();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
else else
{ {
irq_counter++; irq_counter++;
} }
} }
} }
} }
//void Mapper026::SaveState(LPBYTE p) //void Mapper026::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = irq_enable; //p[0] = irq_enable;
//p[1] = irq_counter; //p[1] = irq_counter;
//p[2] = irq_latch; //p[2] = irq_latch;
//*(INT*)&p[3] = irq_clock; //*(INT*)&p[3] = irq_clock;
} }
//void Mapper026::LoadState(LPBYTE p) //void Mapper026::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//irq_enable = p[0]; //irq_enable = p[0];
//irq_counter = p[1]; //irq_counter = p[1];
//irq_latch = p[2]; //irq_latch = p[2];
//irq_clock = *(INT*)&p[3]; //irq_clock = *(INT*)&p[3];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

388
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper027.cs
View File

@ -1,228 +1,228 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper027 Konami VRC4 (World Hero) // // Mapper027 Konami VRC4 (World Hero) //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper027 : Mapper public class Mapper027 : Mapper
{ {
ushort[] reg = new ushort[9]; ushort[] reg = new ushort[9];
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
INT irq_clock; INT irq_clock;
public Mapper027(NES parent) : base(parent) public Mapper027(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
reg[i] = (byte)i; reg[i] = (byte)i;
} }
reg[8] = 0; reg[8] = 0;
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
irq_clock = 0; irq_clock = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0x47DCBCC4) if (crc == 0x47DCBCC4)
{ // Gradius II(sample) { // Gradius II(sample)
nes.SetRenderMethod(EnumRenderMethod.POST_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_RENDER);
} }
if (crc == 0x468F21FC) if (crc == 0x468F21FC)
{ // Racer Mini 4 ku(sample) { // Racer Mini 4 ku(sample)
nes.SetRenderMethod(EnumRenderMethod.POST_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_RENDER);
} }
} }
//void Mapper027::Write(WORD addr, BYTE data) //void Mapper027::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF0CF) switch (addr & 0xF0CF)
{ {
case 0x8000: case 0x8000:
if ((reg[8] & 0x02) != 0) if ((reg[8] & 0x02) != 0)
{ {
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
} }
else else
{ {
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
} }
break; break;
case 0xA000: case 0xA000:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0x9000: case 0x9000:
data &= 0x03; data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR); if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L); else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L);
else SetVRAM_Mirror(VRAM_MIRROR4H); else SetVRAM_Mirror(VRAM_MIRROR4H);
break; break;
case 0x9002: case 0x9002:
case 0x9080: case 0x9080:
reg[8] = data; reg[8] = data;
break; break;
case 0xB000: case 0xB000:
reg[0] = (ushort)((reg[0] & 0xFF0) | (data & 0x0F)); reg[0] = (ushort)((reg[0] & 0xFF0) | (data & 0x0F));
SetVROM_1K_Bank(0, reg[0]); SetVROM_1K_Bank(0, reg[0]);
break; break;
case 0xB001: case 0xB001:
reg[0] = (ushort)((reg[0] & 0x0F) | (data << 4)); reg[0] = (ushort)((reg[0] & 0x0F) | (data << 4));
SetVROM_1K_Bank(0, reg[0]); SetVROM_1K_Bank(0, reg[0]);
break; break;
case 0xB002: case 0xB002:
reg[1] = (ushort)((reg[1] & 0xFF0) | (data & 0x0F)); reg[1] = (ushort)((reg[1] & 0xFF0) | (data & 0x0F));
SetVROM_1K_Bank(1, reg[1]); SetVROM_1K_Bank(1, reg[1]);
break; break;
case 0xB003: case 0xB003:
reg[1] = (ushort)((reg[1] & 0x0F) | (data << 4)); reg[1] = (ushort)((reg[1] & 0x0F) | (data << 4));
SetVROM_1K_Bank(1, reg[1]); SetVROM_1K_Bank(1, reg[1]);
break; break;
case 0xC000: case 0xC000:
reg[2] = (ushort)((reg[2] & 0xFF0) | (data & 0x0F)); reg[2] = (ushort)((reg[2] & 0xFF0) | (data & 0x0F));
SetVROM_1K_Bank(2, reg[2]); SetVROM_1K_Bank(2, reg[2]);
break; break;
case 0xC001: case 0xC001:
reg[2] = (ushort)((reg[2] & 0x0F) | (data << 4)); reg[2] = (ushort)((reg[2] & 0x0F) | (data << 4));
SetVROM_1K_Bank(2, reg[2]); SetVROM_1K_Bank(2, reg[2]);
break; break;
case 0xC002: case 0xC002:
reg[3] = (ushort)((reg[3] & 0xFF0) | (data & 0x0F)); reg[3] = (ushort)((reg[3] & 0xFF0) | (data & 0x0F));
SetVROM_1K_Bank(3, reg[3]); SetVROM_1K_Bank(3, reg[3]);
break; break;
case 0xC003: case 0xC003:
reg[3] = (ushort)((reg[3] & 0x0F) | (data << 4)); reg[3] = (ushort)((reg[3] & 0x0F) | (data << 4));
SetVROM_1K_Bank(3, reg[3]); SetVROM_1K_Bank(3, reg[3]);
break; break;
case 0xD000: case 0xD000:
reg[4] = (ushort)((reg[4] & 0xFF0) | (data & 0x0F)); reg[4] = (ushort)((reg[4] & 0xFF0) | (data & 0x0F));
SetVROM_1K_Bank(4, reg[4]); SetVROM_1K_Bank(4, reg[4]);
break; break;
case 0xD001: case 0xD001:
reg[4] = (ushort)((reg[4] & 0x0F) | (data << 4)); reg[4] = (ushort)((reg[4] & 0x0F) | (data << 4));
SetVROM_1K_Bank(4, reg[4]); SetVROM_1K_Bank(4, reg[4]);
break; break;
case 0xD002: case 0xD002:
reg[5] = (ushort)((reg[5] & 0xFF0) | (data & 0x0F)); reg[5] = (ushort)((reg[5] & 0xFF0) | (data & 0x0F));
SetVROM_1K_Bank(5, reg[5]); SetVROM_1K_Bank(5, reg[5]);
break; break;
case 0xD003: case 0xD003:
reg[5] = (ushort)((reg[5] & 0x0F) | (data << 4)); reg[5] = (ushort)((reg[5] & 0x0F) | (data << 4));
SetVROM_1K_Bank(5, reg[5]); SetVROM_1K_Bank(5, reg[5]);
break; break;
case 0xE000: case 0xE000:
reg[6] = (ushort)((reg[6] & 0xFF0) | (data & 0x0F)); reg[6] = (ushort)((reg[6] & 0xFF0) | (data & 0x0F));
SetVROM_1K_Bank(6, reg[6]); SetVROM_1K_Bank(6, reg[6]);
break; break;
case 0xE001: case 0xE001:
reg[6] = (ushort)((reg[6] & 0x0F) | (data << 4)); reg[6] = (ushort)((reg[6] & 0x0F) | (data << 4));
SetVROM_1K_Bank(6, reg[6]); SetVROM_1K_Bank(6, reg[6]);
break; break;
case 0xE002: case 0xE002:
reg[7] = (ushort)((reg[7] & 0xFF0) | (data & 0x0F)); reg[7] = (ushort)((reg[7] & 0xFF0) | (data & 0x0F));
SetVROM_1K_Bank(7, reg[7]); SetVROM_1K_Bank(7, reg[7]);
break; break;
case 0xE003: case 0xE003:
reg[7] = (ushort)((reg[7] & 0x0F) | (data << 4)); reg[7] = (ushort)((reg[7] & 0x0F) | (data << 4));
SetVROM_1K_Bank(7, reg[7]); SetVROM_1K_Bank(7, reg[7]);
break; break;
case 0xF000: case 0xF000:
irq_latch = (byte)((irq_latch & 0xF0) | (data & 0x0F)); irq_latch = (byte)((irq_latch & 0xF0) | (data & 0x0F));
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF001: case 0xF001:
irq_latch = (byte)((irq_latch & 0x0F) | ((data & 0x0F) << 4)); irq_latch = (byte)((irq_latch & 0x0F) | ((data & 0x0F) << 4));
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF003: case 0xF003:
irq_enable = (byte)((irq_enable & 0x01) * 3); irq_enable = (byte)((irq_enable & 0x01) * 3);
irq_clock = 0; irq_clock = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF002: case 0xF002:
irq_enable = (byte)(data & 0x03); irq_enable = (byte)(data & 0x03);
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
irq_clock = 0; irq_clock = 0;
} }
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
} }
} }
//void Mapper027::HSync(INT scanline) //void Mapper027::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
if (irq_counter == 0xFF) if (irq_counter == 0xFF)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
// nes.cpu.IRQ_NotPending(); // nes.cpu.IRQ_NotPending();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
else else
{ {
irq_counter++; irq_counter++;
} }
} }
} }
//void Mapper027::SaveState(LPBYTE p) //void Mapper027::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//for (INT i = 0; i < 9; i++) //for (INT i = 0; i < 9; i++)
//{ //{
// p[i] = reg[i]; // p[i] = reg[i];
//} //}
//p[9] = irq_enable; //p[9] = irq_enable;
//p[10] = irq_counter; //p[10] = irq_counter;
//p[11] = irq_latch; //p[11] = irq_latch;
//*(INT*)&p[12] = irq_clock; //*(INT*)&p[12] = irq_clock;
} }
//void Mapper027::LoadState(LPBYTE p) //void Mapper027::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//for (INT i = 0; i < 9; i++) //for (INT i = 0; i < 9; i++)
//{ //{
// reg[i] = p[i]; // reg[i] = p[i];
//} //}
//irq_enable = p[9]; //irq_enable = p[9];
//irq_counter = p[10]; //irq_counter = p[10];
//irq_latch = p[11]; //irq_latch = p[11];
//irq_clock = *(INT*)&p[12]; //irq_clock = *(INT*)&p[12];
} }
} }
} }

190
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper032.cs
View File

@ -2,122 +2,120 @@
// Mapper032 Irem G101 // // Mapper032 Irem G101 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper032 : Mapper public class Mapper032 : Mapper
{ {
BYTE patch; BYTE patch;
BYTE reg; BYTE reg;
public Mapper032(NES parent) : base(parent) public Mapper032(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
patch = 0; patch = 0;
reg = 0; reg = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_8K_SIZE != 0) if (VROM_8K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
// For Major League(J) // For Major League(J)
if (crc == 0xc0fed437) if (crc == 0xc0fed437)
{ {
patch = 1; patch = 1;
} }
// For Ai Sensei no Oshiete - Watashi no Hoshi(J) // For Ai Sensei no Oshiete - Watashi no Hoshi(J)
if (crc == 0xfd3fc292) if (crc == 0xfd3fc292)
{ {
SetPROM_32K_Bank(30, 31, 30, 31); SetPROM_32K_Bank(30, 31, 30, 31);
} }
} }
//void Mapper032::Write(WORD addr, BYTE data) //void Mapper032::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF000) switch (addr & 0xF000)
{ {
case 0x8000: case 0x8000:
if ((reg & 0x02) != 0) if ((reg & 0x02) != 0)
{ {
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
} }
else else
{ {
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
} }
break; break;
case 0x9000: case 0x9000:
reg = data; reg = data;
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
case 0xA000: case 0xA000:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
} }
switch (addr & 0xF007) switch (addr & 0xF007)
{ {
case 0xB000: case 0xB000:
case 0xB001: case 0xB001:
case 0xB002: case 0xB002:
case 0xB003: case 0xB003:
case 0xB004: case 0xB004:
case 0xB005: case 0xB005:
SetVROM_1K_Bank((byte)(addr & 0x0007), data); SetVROM_1K_Bank((byte)(addr & 0x0007), data);
break; break;
case 0xB006: case 0xB006:
SetVROM_1K_Bank(6, data); SetVROM_1K_Bank(6, data);
if (patch != 0 && ((data & 0x40) != 0)) if (patch != 0 && ((data & 0x40) != 0))
{ {
SetVRAM_Mirror(0, 0, 0, 1); SetVRAM_Mirror(0, 0, 0, 1);
} }
break; break;
case 0xB007: case 0xB007:
SetVROM_1K_Bank(7, data); SetVROM_1K_Bank(7, data);
if (patch != 0 && ((data & 0x40) != 0)) if (patch != 0 && ((data & 0x40) != 0))
{ {
SetVRAM_Mirror(0, 0, 0, 0); SetVRAM_Mirror(0, 0, 0, 0);
} }
break; break;
} }
} }
//void Mapper032::SaveState(LPBYTE p) //void Mapper032::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg; p[0] = reg;
} }
//void Mapper032::LoadState(LPBYTE p) //void Mapper032::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg = p[0]; reg = p[0];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

374
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper033.cs
View File

@ -1,131 +1,131 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper033 Taito TC0190 // // Mapper033 Taito TC0190 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper033 : Mapper public class Mapper033 : Mapper
{ {
BYTE[] reg = new byte[7]; BYTE[] reg = new byte[7];
BYTE patch; BYTE patch;
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
public Mapper033(NES parent) : base(parent) public Mapper033(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
patch = 0; patch = 0;
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
reg[0] = 0; reg[0] = 0;
reg[1] = 2; reg[1] = 2;
reg[2] = 4; reg[2] = 4;
reg[3] = 5; reg[3] = 5;
reg[4] = 6; reg[4] = 6;
reg[5] = 7; reg[5] = 7;
reg[6] = 1; reg[6] = 1;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_8K_SIZE != 0) if (VROM_8K_SIZE != 0)
{ {
SetBank(); SetBank();
} }
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
// Check For Old #33 games.... (CRC code by NesToy) // Check For Old #33 games.... (CRC code by NesToy)
if (crc == 0x5e9bc161 // Akira(J) if (crc == 0x5e9bc161 // Akira(J)
|| crc == 0xecdbafa4 // Bakushou!! Jinsei Gekijou(J) || crc == 0xecdbafa4 // Bakushou!! Jinsei Gekijou(J)
|| crc == 0x59cd0c31 // Don Doko Don(J) || crc == 0x59cd0c31 // Don Doko Don(J)
|| crc == 0x837c1342 // Golf Ko Open(J) || crc == 0x837c1342 // Golf Ko Open(J)
|| crc == 0x42d893e4 // Operation Wolf(J) || crc == 0x42d893e4 // Operation Wolf(J)
|| crc == 0x1388aeb9 // Operation Wolf(U) || crc == 0x1388aeb9 // Operation Wolf(U)
|| crc == 0x07ee6d8f // Power Blazer(J) || crc == 0x07ee6d8f // Power Blazer(J)
|| crc == 0x5193fb54 // Takeshi no Sengoku Fuuunji(J) || crc == 0x5193fb54 // Takeshi no Sengoku Fuuunji(J)
|| crc == 0xa71c3452) || crc == 0xa71c3452)
{ // Insector X(J) { // Insector X(J)
patch = 1; patch = 1;
} }
nes.SetRenderMethod(EnumRenderMethod.PRE_RENDER); nes.SetRenderMethod(EnumRenderMethod.PRE_RENDER);
if (crc == 0x202df297) if (crc == 0x202df297)
{ // Captain Saver(J) { // Captain Saver(J)
nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER); nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER);
} }
if (crc == 0x63bb86b5) if (crc == 0x63bb86b5)
{ // The Jetsons(J) { // The Jetsons(J)
nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER); nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER);
} }
} }
//void Mapper033::Write(WORD addr, BYTE data) //void Mapper033::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
// LOG( "Mapper033 addr=%04X data=%02X", addr&0xFFFF, data&0xFF ); // LOG( "Mapper033 addr=%04X data=%02X", addr&0xFFFF, data&0xFF );
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
if (patch != 0) if (patch != 0)
{ {
if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
SetPROM_8K_Bank(4, data & 0x1F); SetPROM_8K_Bank(4, data & 0x1F);
} }
else else
{ {
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
} }
break; break;
case 0x8001: case 0x8001:
if (patch != 0) if (patch != 0)
{ {
SetPROM_8K_Bank(5, data & 0x1F); SetPROM_8K_Bank(5, data & 0x1F);
} }
else else
{ {
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
} }
break; break;
case 0x8002: case 0x8002:
reg[0] = data; reg[0] = data;
SetBank(); SetBank();
break; break;
case 0x8003: case 0x8003:
reg[1] = data; reg[1] = data;
SetBank(); SetBank();
break; break;
case 0xA000: case 0xA000:
reg[2] = data; reg[2] = data;
SetBank(); SetBank();
break; break;
case 0xA001: case 0xA001:
reg[3] = data; reg[3] = data;
SetBank(); SetBank();
break; break;
case 0xA002: case 0xA002:
reg[4] = data; reg[4] = data;
SetBank(); SetBank();
break; break;
case 0xA003: case 0xA003:
reg[5] = data; reg[5] = data;
SetBank(); SetBank();
break; break;
#if FLASE//0 #if FLASE//0
case 0xC003: case 0xC003:
@ -147,36 +147,36 @@ namespace VirtualNes.Core
// nes.cpu.ClrIRQ( IRQ_MAPPER ); // nes.cpu.ClrIRQ( IRQ_MAPPER );
break; break;
#else #else
case 0xC000: case 0xC000:
irq_latch = data; irq_latch = data;
irq_counter = irq_latch; irq_counter = irq_latch;
break; break;
case 0xC001: case 0xC001:
irq_counter = irq_latch; irq_counter = irq_latch;
break; break;
case 0xC002: case 0xC002:
irq_enable = 1; irq_enable = 1;
break; break;
case 0xC003: case 0xC003:
irq_enable = 0; irq_enable = 0;
break; break;
case 0xE001: case 0xE001:
case 0xE002: case 0xE002:
case 0xE003: case 0xE003:
break; break;
#endif #endif
case 0xE000: case 0xE000:
if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
} }
} }
//void Mapper033::HSync(INT scanline) //void Mapper033::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
#if FALSE//0 #if FALSE//0
// nes.cpu.ClrIRQ( IRQ_MAPPER ); // nes.cpu.ClrIRQ( IRQ_MAPPER );
if( scanline >= 0 && scanline <= 239 ) { if( scanline >= 0 && scanline <= 239 ) {
@ -194,67 +194,67 @@ namespace VirtualNes.Core
} }
} }
#else #else
if (scanline >= 0 && scanline <= 239 && nes.ppu.IsDispON()) if (scanline >= 0 && scanline <= 239 && nes.ppu.IsDispON())
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if (++irq_counter == 0) if (++irq_counter == 0)
{ {
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
nes.cpu.SetIRQ(IRQ_TRIGGER); nes.cpu.SetIRQ(IRQ_TRIGGER);
} }
} }
} }
#endif #endif
} }
void SetBank() void SetBank()
{ {
SetVROM_2K_Bank(0, reg[0]); SetVROM_2K_Bank(0, reg[0]);
SetVROM_2K_Bank(2, reg[1]); SetVROM_2K_Bank(2, reg[1]);
// if( reg[6] & 0x01 ) { // if( reg[6] & 0x01 ) {
SetVROM_1K_Bank(4, reg[2]); SetVROM_1K_Bank(4, reg[2]);
SetVROM_1K_Bank(5, reg[3]); SetVROM_1K_Bank(5, reg[3]);
SetVROM_1K_Bank(6, reg[4]); SetVROM_1K_Bank(6, reg[4]);
SetVROM_1K_Bank(7, reg[5]); SetVROM_1K_Bank(7, reg[5]);
// } else { // } else {
// SetVROM_2K_Bank( 4, reg[0] ); // SetVROM_2K_Bank( 4, reg[0] );
// SetVROM_2K_Bank( 6, reg[1] ); // SetVROM_2K_Bank( 6, reg[1] );
// } // }
} }
//void Mapper033::SaveState(LPBYTE p) //void Mapper033::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
for (INT i = 0; i < 7; i++) for (INT i = 0; i < 7; i++)
{ {
p[i] = reg[i]; p[i] = reg[i];
} }
p[7] = irq_enable; p[7] = irq_enable;
p[8] = irq_counter; p[8] = irq_counter;
p[9] = irq_latch; p[9] = irq_latch;
} }
//void Mapper033::LoadState(LPBYTE p) //void Mapper033::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
for (INT i = 0; i < 7; i++) for (INT i = 0; i < 7; i++)
{ {
reg[i] = p[i]; reg[i] = p[i];
} }
irq_enable = p[7]; irq_enable = p[7];
irq_counter = p[8]; irq_counter = p[8];
irq_latch = p[9]; irq_latch = p[9];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

75
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper034.cs
View File

@ -2,53 +2,50 @@
// Mapper034 Nina-1 // // Mapper034 Nina-1 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper034 : Mapper public class Mapper034 : Mapper
{ {
public Mapper034(NES parent) : base(parent) public Mapper034(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper034::WriteLow(WORD addr, BYTE data) //void Mapper034::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x7FFD: case 0x7FFD:
SetPROM_32K_Bank(data); SetPROM_32K_Bank(data);
break; break;
case 0x7FFE: case 0x7FFE:
SetVROM_4K_Bank(0, data); SetVROM_4K_Bank(0, data);
break; break;
case 0x7FFF: case 0x7FFF:
SetVROM_4K_Bank(4, data); SetVROM_4K_Bank(4, data);
break; break;
} }
} }
//void Mapper034::Write(WORD addr, BYTE data) //void Mapper034::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
SetPROM_32K_Bank(data); SetPROM_32K_Bank(data);
} }
} }
} }

19
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper035.cs
View File

@ -1,26 +1,25 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper035 // // Mapper035 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper035 : Mapper public class Mapper035 : Mapper
{ {
BYTE[] reg = new byte[8]; BYTE[] reg = new byte[8];
BYTE[] chr = new byte[8]; BYTE[] chr = new byte[8];
ushort IRQCount, IRQa; ushort IRQCount, IRQa;
public Mapper035(NES parent) : base(parent) public Mapper035(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
for (int i = 0; i < 8; i++) for (int i = 0; i < 8; i++)
reg[i] = chr[i] = 0; reg[i] = chr[i] = 0;
@ -103,7 +102,7 @@ namespace VirtualNes.Core
{ {
if (nes.ppu.IsDispON()) if (nes.ppu.IsDispON())
{ {
if (IRQa!=0) if (IRQa != 0)
{ {
IRQCount--; IRQCount--;
if (IRQCount == 0) if (IRQCount == 0)
@ -118,7 +117,7 @@ namespace VirtualNes.Core
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

142
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper040.cs
View File

@ -1,90 +1,90 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper040 SMB2J // // Mapper040 SMB2J //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper040 : Mapper public class Mapper040 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
INT irq_line; INT irq_line;
public Mapper040(NES parent) : base(parent) public Mapper040(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
irq_enable = 0; irq_enable = 0;
irq_line = 0; irq_line = 0;
SetPROM_8K_Bank(3, 6); SetPROM_8K_Bank(3, 6);
SetPROM_32K_Bank(4, 5, 0, 7); SetPROM_32K_Bank(4, 5, 0, 7);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper040::Write(WORD addr, BYTE data) //void Mapper040::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xE000) switch (addr & 0xE000)
{ {
case 0x8000: case 0x8000:
irq_enable = 0; irq_enable = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xA000: case 0xA000:
irq_enable = 0xFF; irq_enable = 0xFF;
irq_line = 37; irq_line = 37;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xC000: case 0xC000:
break; break;
case 0xE000: case 0xE000:
SetPROM_8K_Bank(6, data & 0x07); SetPROM_8K_Bank(6, data & 0x07);
break; break;
} }
} }
//void Mapper040::HSync(INT scanline) //void Mapper040::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if (--irq_line <= 0) if (--irq_line <= 0)
{ {
// nes.cpu.IRQ(); // nes.cpu.IRQ();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
//void Mapper040::SaveState(LPBYTE p) //void Mapper040::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = irq_enable; //p[0] = irq_enable;
//*(INT*)&p[1] = irq_line; //*(INT*)&p[1] = irq_line;
} }
//void Mapper040::LoadState(LPBYTE p) //void Mapper040::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//irq_enable = p[0]; //irq_enable = p[0];
//irq_line = *(INT*)&p[1]; //irq_line = *(INT*)&p[1];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

116
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper041.cs
View File

@ -2,77 +2,75 @@
// Mapper041 Caltron 6-in-1 // // Mapper041 Caltron 6-in-1 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper041 : Mapper public class Mapper041 : Mapper
{ {
BYTE[] reg = new byte[2]; BYTE[] reg = new byte[2];
public Mapper041(NES parent) : base(parent) public Mapper041(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
reg[0] = reg[1] = 0; reg[0] = reg[1] = 0;
SetPROM_32K_Bank(0, 1, 2, 3); SetPROM_32K_Bank(0, 1, 2, 3);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper041::WriteLow(WORD addr, BYTE data) //void Mapper041::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if (addr >= 0x6000 && addr < 0x6800) if (addr >= 0x6000 && addr < 0x6800)
{ {
SetPROM_32K_Bank(addr & 0x07); SetPROM_32K_Bank(addr & 0x07);
reg[0] = (byte)(addr & 0x04); reg[0] = (byte)(addr & 0x04);
reg[1] &= 0x03; reg[1] &= 0x03;
reg[1] |= (byte)((addr >> 1) & 0x0C); reg[1] |= (byte)((addr >> 1) & 0x0C);
SetVROM_8K_Bank(reg[1]); SetVROM_8K_Bank(reg[1]);
if ((addr & 0x20) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((addr & 0x20) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
} }
} }
//void Mapper041::Write(WORD addr, BYTE data) //void Mapper041::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
if (reg[0] != 0) if (reg[0] != 0)
{ {
reg[1] &= 0x0C; reg[1] &= 0x0C;
reg[1] |= (byte)(addr & 0x03); reg[1] |= (byte)(addr & 0x03);
SetVROM_8K_Bank(reg[1]); SetVROM_8K_Bank(reg[1]);
} }
} }
//void Mapper041::SaveState(LPBYTE p) //void Mapper041::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg[0]; p[0] = reg[0];
p[1] = reg[1]; p[1] = reg[1];
} }
//void Mapper041::LoadState(LPBYTE p) //void Mapper041::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg[0] = p[0]; reg[0] = p[0];
reg[1] = p[1]; reg[1] = p[1];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

163
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper042.cs
View File

@ -1,103 +1,102 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper042 Mario Baby // // Mapper042 Mario Baby //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper042 : Mapper public class Mapper042 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
public Mapper042(NES parent) : base(parent) public Mapper042(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
SetPROM_8K_Bank(3, 0); SetPROM_8K_Bank(3, 0);
SetPROM_32K_Bank(PROM_8K_SIZE - 4, PROM_8K_SIZE - 3, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(PROM_8K_SIZE - 4, PROM_8K_SIZE - 3, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper042::Write(WORD addr, BYTE data) //void Mapper042::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xE003) switch (addr & 0xE003)
{ {
case 0xE000: case 0xE000:
SetPROM_8K_Bank(3, data & 0x0F); SetPROM_8K_Bank(3, data & 0x0F);
break; break;
case 0xE001: case 0xE001:
if ((data & 0x08) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x08) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
case 0xE002: case 0xE002:
if ((data & 0x02) != 0) if ((data & 0x02) != 0)
{ {
irq_enable = 0xFF; irq_enable = 0xFF;
} }
else else
{ {
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
} }
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
} }
} }
//void Mapper042::HSync(INT scanline) //void Mapper042::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
if (irq_enable != 0) if (irq_enable != 0)
{ {
if (irq_counter < 215) if (irq_counter < 215)
{ {
irq_counter++; irq_counter++;
} }
if (irq_counter == 215) if (irq_counter == 215)
{ {
irq_enable = 0; irq_enable = 0;
// nes.cpu.IRQ(); // nes.cpu.IRQ();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
//void Mapper042::SaveState(LPBYTE p) //void Mapper042::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = irq_enable; p[0] = irq_enable;
p[1] = irq_counter; p[1] = irq_counter;
} }
//void Mapper042::LoadState(LPBYTE p) //void Mapper042::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
irq_enable = p[0]; irq_enable = p[0];
irq_counter = p[1]; irq_counter = p[1];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

232
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper043.cs
View File

@ -1,138 +1,138 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper043 SMB2J // // Mapper043 SMB2J //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper043 : Mapper public class Mapper043 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
INT irq_counter; INT irq_counter;
public Mapper043(NES parent) : base(parent) public Mapper043(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
irq_enable = 0xFF; irq_enable = 0xFF;
irq_counter = 0; irq_counter = 0;
SetPROM_8K_Bank(3, 2); SetPROM_8K_Bank(3, 2);
SetPROM_32K_Bank(1, 0, 4, 9); SetPROM_32K_Bank(1, 0, 4, 9);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//BYTE Mapper043::ReadLow(WORD addr) //BYTE Mapper043::ReadLow(WORD addr)
public override byte ReadLow(ushort addr) public override byte ReadLow(ushort addr)
{ {
if (0x5000 <= addr && addr < 0x6000) if (0x5000 <= addr && addr < 0x6000)
{ {
byte[] pPtr = nes.rom.GetPROM(); byte[] pPtr = nes.rom.GetPROM();
return pPtr[0x2000 * 8 + 0x1000 + (addr - 0x5000)]; return pPtr[0x2000 * 8 + 0x1000 + (addr - 0x5000)];
} }
return (BYTE)(addr >> 8); return (BYTE)(addr >> 8);
} }
//void Mapper043::ExWrite(WORD addr, BYTE data) //void Mapper043::ExWrite(WORD addr, BYTE data)
public override void ExWrite(ushort addr, byte data) public override void ExWrite(ushort addr, byte data)
{ {
if ((addr & 0xF0FF) == 0x4022) if ((addr & 0xF0FF) == 0x4022)
{ {
switch (data & 0x07) switch (data & 0x07)
{ {
case 0x00: case 0x00:
case 0x02: case 0x02:
case 0x03: case 0x03:
case 0x04: case 0x04:
SetPROM_8K_Bank(6, 4); SetPROM_8K_Bank(6, 4);
break; break;
case 0x01: case 0x01:
SetPROM_8K_Bank(6, 3); SetPROM_8K_Bank(6, 3);
break; break;
case 0x05: case 0x05:
SetPROM_8K_Bank(6, 7); SetPROM_8K_Bank(6, 7);
break; break;
case 0x06: case 0x06:
SetPROM_8K_Bank(6, 5); SetPROM_8K_Bank(6, 5);
break; break;
case 0x07: case 0x07:
SetPROM_8K_Bank(6, 6); SetPROM_8K_Bank(6, 6);
break; break;
} }
} }
} }
//void Mapper043::WriteLow(WORD addr, BYTE data) //void Mapper043::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if ((addr & 0xF0FF) == 0x4022) if ((addr & 0xF0FF) == 0x4022)
{ {
ExWrite(addr, data); ExWrite(addr, data);
} }
} }
//void Mapper043::Write(WORD addr, BYTE data) //void Mapper043::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
if (addr == 0x8122) if (addr == 0x8122)
{ {
if ((data & 0x03) != 0) if ((data & 0x03) != 0)
{ {
irq_enable = 1; irq_enable = 1;
} }
else else
{ {
irq_counter = 0; irq_counter = 0;
irq_enable = 0; irq_enable = 0;
} }
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
} }
} }
//void Mapper043::HSync(INT scanline) //void Mapper043::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
if (irq_enable != 0) if (irq_enable != 0)
{ {
irq_counter += 341; irq_counter += 341;
if (irq_counter >= 12288) if (irq_counter >= 12288)
{ {
irq_counter = 0; irq_counter = 0;
// nes.cpu.IRQ(); // nes.cpu.IRQ();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
//void Mapper043::SaveState(LPBYTE p) //void Mapper043::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = irq_enable; //p[0] = irq_enable;
//*(INT*)&p[1] = irq_counter; //*(INT*)&p[1] = irq_counter;
} }
//void Mapper043::LoadState(LPBYTE p) //void Mapper043::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//irq_enable = p[0]; //irq_enable = p[0];
//irq_counter = *(INT*)&p[1]; //irq_counter = *(INT*)&p[1];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

524
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper044.cs
View File

@ -1,289 +1,289 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper044 Super HiK 7-in-1 // // Mapper044 Super HiK 7-in-1 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper044 : Mapper public class Mapper044 : Mapper
{ {
BYTE[] reg = new byte[8]; BYTE[] reg = new byte[8];
BYTE patch; BYTE patch;
BYTE bank; BYTE bank;
BYTE prg0, prg1; BYTE prg0, prg1;
BYTE chr01, chr23, chr4, chr5, chr6, chr7; BYTE chr01, chr23, chr4, chr5, chr6, chr7;
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
public Mapper044(NES parent) : base(parent) public Mapper044(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
patch = 0; patch = 0;
if (nes.rom.GetPROM_CRC() == 0x7eef434c) if (nes.rom.GetPROM_CRC() == 0x7eef434c)
{ {
patch = 1; patch = 1;
} }
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
reg[i] = 0; reg[i] = 0;
} }
bank = 0; bank = 0;
prg0 = 0; prg0 = 0;
prg1 = 1; prg1 = 1;
// set VROM banks // set VROM banks
if (VROM_1K_SIZE!=0) if (VROM_1K_SIZE != 0)
{ {
chr01 = 0; chr01 = 0;
chr23 = 2; chr23 = 2;
chr4 = 4; chr4 = 4;
chr5 = 5; chr5 = 5;
chr6 = 6; chr6 = 6;
chr7 = 7; chr7 = 7;
} }
else else
{ {
chr01 = chr23 = chr4 = chr5 = chr6 = chr7 = 0; chr01 = chr23 = chr4 = chr5 = chr6 = chr7 = 0;
} }
SetBank_CPU(); SetBank_CPU();
SetBank_PPU(); SetBank_PPU();
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
} }
//void Mapper044::WriteLow(WORD addr, BYTE data) //void Mapper044::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if (addr == 0x6000) if (addr == 0x6000)
{ {
if (patch!=0) if (patch != 0)
{ {
bank = (byte)((data & 0x06) >> 1); bank = (byte)((data & 0x06) >> 1);
} }
else else
{ {
bank = (byte)((data & 0x01) << 1); bank = (byte)((data & 0x01) << 1);
} }
SetBank_CPU(); SetBank_CPU();
SetBank_PPU(); SetBank_PPU();
} }
} }
//void Mapper044::Write(WORD addr, BYTE data) //void Mapper044::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xE001) switch (addr & 0xE001)
{ {
case 0x8000: case 0x8000:
reg[0] = data; reg[0] = data;
SetBank_CPU(); SetBank_CPU();
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x8001: case 0x8001:
reg[1] = data; reg[1] = data;
switch (reg[0] & 0x07) switch (reg[0] & 0x07)
{ {
case 0x00: case 0x00:
chr01 = (byte)(data & 0xFE); chr01 = (byte)(data & 0xFE);
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x01: case 0x01:
chr23 = (byte)(data & 0xFE); chr23 = (byte)(data & 0xFE);
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x02: case 0x02:
chr4 = data; chr4 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x03: case 0x03:
chr5 = data; chr5 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x04: case 0x04:
chr6 = data; chr6 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x05: case 0x05:
chr7 = data; chr7 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x06: case 0x06:
prg0 = data; prg0 = data;
SetBank_CPU(); SetBank_CPU();
break; break;
case 0x07: case 0x07:
prg1 = data; prg1 = data;
SetBank_CPU(); SetBank_CPU();
break; break;
} }
break; break;
case 0xA000: case 0xA000:
reg[2] = data; reg[2] = data;
if (!nes.rom.Is4SCREEN()) if (!nes.rom.Is4SCREEN())
{ {
if ((data & 0x01)!=0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
} }
break; break;
case 0xA001: case 0xA001:
reg[3] = data; reg[3] = data;
bank = (byte)(data & 0x07); bank = (byte)(data & 0x07);
if (bank == 7) if (bank == 7)
{ {
bank = 6; bank = 6;
} }
SetBank_CPU(); SetBank_CPU();
SetBank_PPU(); SetBank_PPU();
break; break;
case 0xC000: case 0xC000:
reg[4] = data; reg[4] = data;
irq_counter = data; irq_counter = data;
break; break;
case 0xC001: case 0xC001:
reg[5] = data; reg[5] = data;
irq_latch = data; irq_latch = data;
break; break;
case 0xE000: case 0xE000:
reg[6] = data; reg[6] = data;
irq_enable = 0; irq_enable = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xE001: case 0xE001:
reg[7] = data; reg[7] = data;
irq_enable = 1; irq_enable = 1;
// nes.cpu.ClrIRQ( IRQ_MAPPER ); // nes.cpu.ClrIRQ( IRQ_MAPPER );
break; break;
} }
} }
//void Mapper044::HSync(INT scanline) //void Mapper044::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if ((scanline >= 0 && scanline <= 239)) if ((scanline >= 0 && scanline <= 239))
{ {
if (nes.ppu.IsDispON()) if (nes.ppu.IsDispON())
{ {
if (irq_enable!=0) if (irq_enable != 0)
{ {
if ((--irq_counter)==0) if ((--irq_counter) == 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
// nes.cpu.IRQ(); // nes.cpu.IRQ();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
} }
} }
void SetBank_CPU() void SetBank_CPU()
{ {
if ((reg[0] & 0x40)!=0) if ((reg[0] & 0x40) != 0)
{ {
SetPROM_8K_Bank(4, ((bank == 6) ? 0x1e : 0x0e) | (bank << 4)); SetPROM_8K_Bank(4, ((bank == 6) ? 0x1e : 0x0e) | (bank << 4));
SetPROM_8K_Bank(5, ((bank == 6) ? 0x1f & prg1 : 0x0f & prg1) | (bank << 4)); SetPROM_8K_Bank(5, ((bank == 6) ? 0x1f & prg1 : 0x0f & prg1) | (bank << 4));
SetPROM_8K_Bank(6, ((bank == 6) ? 0x1f & prg0 : 0x0f & prg0) | (bank << 4)); SetPROM_8K_Bank(6, ((bank == 6) ? 0x1f & prg0 : 0x0f & prg0) | (bank << 4));
SetPROM_8K_Bank(7, ((bank == 6) ? 0x1f : 0x0f) | (bank << 4)); SetPROM_8K_Bank(7, ((bank == 6) ? 0x1f : 0x0f) | (bank << 4));
} }
else else
{ {
SetPROM_8K_Bank(4, ((bank == 6) ? 0x1f & prg0 : 0x0f & prg0) | (bank << 4)); SetPROM_8K_Bank(4, ((bank == 6) ? 0x1f & prg0 : 0x0f & prg0) | (bank << 4));
SetPROM_8K_Bank(5, ((bank == 6) ? 0x1f & prg1 : 0x0f & prg1) | (bank << 4)); SetPROM_8K_Bank(5, ((bank == 6) ? 0x1f & prg1 : 0x0f & prg1) | (bank << 4));
SetPROM_8K_Bank(6, ((bank == 6) ? 0x1e : 0x0e) | (bank << 4)); SetPROM_8K_Bank(6, ((bank == 6) ? 0x1e : 0x0e) | (bank << 4));
SetPROM_8K_Bank(7, ((bank == 6) ? 0x1f : 0x0f) | (bank << 4)); SetPROM_8K_Bank(7, ((bank == 6) ? 0x1f : 0x0f) | (bank << 4));
} }
} }
void SetBank_PPU() void SetBank_PPU()
{ {
if (VROM_1K_SIZE!=0) if (VROM_1K_SIZE != 0)
{ {
if ((reg[0] & 0x80)!=0) if ((reg[0] & 0x80) != 0)
{ {
SetVROM_1K_Bank(0, ((bank == 6) ? 0xff & chr4 : 0x7f & chr4) | (bank << 7)); SetVROM_1K_Bank(0, ((bank == 6) ? 0xff & chr4 : 0x7f & chr4) | (bank << 7));
SetVROM_1K_Bank(1, ((bank == 6) ? 0xff & chr5 : 0x7f & chr5) | (bank << 7)); SetVROM_1K_Bank(1, ((bank == 6) ? 0xff & chr5 : 0x7f & chr5) | (bank << 7));
SetVROM_1K_Bank(2, ((bank == 6) ? 0xff & chr6 : 0x7f & chr6) | (bank << 7)); SetVROM_1K_Bank(2, ((bank == 6) ? 0xff & chr6 : 0x7f & chr6) | (bank << 7));
SetVROM_1K_Bank(3, ((bank == 6) ? 0xff & chr7 : 0x7f & chr7) | (bank << 7)); SetVROM_1K_Bank(3, ((bank == 6) ? 0xff & chr7 : 0x7f & chr7) | (bank << 7));
SetVROM_1K_Bank(4, ((bank == 6) ? 0xff & chr01 : 0x7f & chr01) | (bank << 7)); SetVROM_1K_Bank(4, ((bank == 6) ? 0xff & chr01 : 0x7f & chr01) | (bank << 7));
SetVROM_1K_Bank(5, ((bank == 6) ? 0xff & (chr01 + 1) : 0x7f & (chr01 + 1)) | (bank << 7)); SetVROM_1K_Bank(5, ((bank == 6) ? 0xff & (chr01 + 1) : 0x7f & (chr01 + 1)) | (bank << 7));
SetVROM_1K_Bank(6, ((bank == 6) ? 0xff & chr23 : 0x7f & chr23) | (bank << 7)); SetVROM_1K_Bank(6, ((bank == 6) ? 0xff & chr23 : 0x7f & chr23) | (bank << 7));
SetVROM_1K_Bank(7, ((bank == 6) ? 0xff & (chr23 + 1) : 0x7f & (chr23 + 1)) | (bank << 7)); SetVROM_1K_Bank(7, ((bank == 6) ? 0xff & (chr23 + 1) : 0x7f & (chr23 + 1)) | (bank << 7));
} }
else else
{ {
SetVROM_1K_Bank(0, ((bank == 6) ? 0xff & chr01 : 0x7f & chr01) | (bank << 7)); SetVROM_1K_Bank(0, ((bank == 6) ? 0xff & chr01 : 0x7f & chr01) | (bank << 7));
SetVROM_1K_Bank(1, ((bank == 6) ? 0xff & (chr01 + 1) : 0x7f & (chr01 + 1)) | (bank << 7)); SetVROM_1K_Bank(1, ((bank == 6) ? 0xff & (chr01 + 1) : 0x7f & (chr01 + 1)) | (bank << 7));
SetVROM_1K_Bank(2, ((bank == 6) ? 0xff & chr23 : 0x7f & chr23) | (bank << 7)); SetVROM_1K_Bank(2, ((bank == 6) ? 0xff & chr23 : 0x7f & chr23) | (bank << 7));
SetVROM_1K_Bank(3, ((bank == 6) ? 0xff & (chr23 + 1) : 0x7f & (chr23 + 1)) | (bank << 7)); SetVROM_1K_Bank(3, ((bank == 6) ? 0xff & (chr23 + 1) : 0x7f & (chr23 + 1)) | (bank << 7));
SetVROM_1K_Bank(4, ((bank == 6) ? 0xff & chr4 : 0x7f & chr4) | (bank << 7)); SetVROM_1K_Bank(4, ((bank == 6) ? 0xff & chr4 : 0x7f & chr4) | (bank << 7));
SetVROM_1K_Bank(5, ((bank == 6) ? 0xff & chr5 : 0x7f & chr5) | (bank << 7)); SetVROM_1K_Bank(5, ((bank == 6) ? 0xff & chr5 : 0x7f & chr5) | (bank << 7));
SetVROM_1K_Bank(6, ((bank == 6) ? 0xff & chr6 : 0x7f & chr6) | (bank << 7)); SetVROM_1K_Bank(6, ((bank == 6) ? 0xff & chr6 : 0x7f & chr6) | (bank << 7));
SetVROM_1K_Bank(7, ((bank == 6) ? 0xff & chr7 : 0x7f & chr7) | (bank << 7)); SetVROM_1K_Bank(7, ((bank == 6) ? 0xff & chr7 : 0x7f & chr7) | (bank << 7));
} }
} }
} }
//void Mapper044::SaveState(LPBYTE p) //void Mapper044::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
p[i] = reg[i]; p[i] = reg[i];
} }
p[8] = prg0; p[8] = prg0;
p[9] = prg1; p[9] = prg1;
p[10] = chr01; p[10] = chr01;
p[11] = chr23; p[11] = chr23;
p[12] = chr4; p[12] = chr4;
p[13] = chr5; p[13] = chr5;
p[14] = chr6; p[14] = chr6;
p[15] = chr7; p[15] = chr7;
p[16] = irq_enable; p[16] = irq_enable;
p[17] = irq_counter; p[17] = irq_counter;
p[18] = irq_latch; p[18] = irq_latch;
p[19] = bank; p[19] = bank;
} }
//void Mapper044::LoadState(LPBYTE p) //void Mapper044::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
reg[i] = p[i]; reg[i] = p[i];
} }
prg0 = p[8]; prg0 = p[8];
prg1 = p[9]; prg1 = p[9];
chr01 = p[10]; chr01 = p[10];
chr23 = p[11]; chr23 = p[11];
chr4 = p[12]; chr4 = p[12];
chr5 = p[13]; chr5 = p[13];
chr6 = p[14]; chr6 = p[14];
chr7 = p[15]; chr7 = p[15];
irq_enable = p[16]; irq_enable = p[16];
irq_counter = p[17]; irq_counter = p[17];
irq_latch = p[18]; irq_latch = p[18];
bank = p[19]; bank = p[19];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

704
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper045.cs
View File

@ -1,387 +1,387 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper045 1000000-in-1 // // Mapper045 1000000-in-1 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using Codice.CM.Client.Differences; using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper045 : Mapper public class Mapper045 : Mapper
{ {
BYTE[] reg = new byte[8]; BYTE[] reg = new byte[8];
BYTE patch; BYTE patch;
BYTE prg0, prg1, prg2, prg3; BYTE prg0, prg1, prg2, prg3;
BYTE chr0, chr1, chr2, chr3, chr4, chr5, chr6, chr7; BYTE chr0, chr1, chr2, chr3, chr4, chr5, chr6, chr7;
BYTE[] p = new byte[4]; BYTE[] p = new byte[4];
INT[] c = new int[8]; INT[] c = new int[8];
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
BYTE irq_latched; BYTE irq_latched;
BYTE irq_reset; BYTE irq_reset;
public Mapper045(NES parent) : base(parent) public Mapper045(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
patch = 0; patch = 0;
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
reg[i] = 0; reg[i] = 0;
} }
prg0 = 0; prg0 = 0;
prg1 = 1; prg1 = 1;
prg2 = (byte)(PROM_8K_SIZE - 2); prg2 = (byte)(PROM_8K_SIZE - 2);
prg3 = (byte)(PROM_8K_SIZE - 1); prg3 = (byte)(PROM_8K_SIZE - 1);
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0x58bcacf6 // Kunio 8-in-1 (Pirate Cart) if (crc == 0x58bcacf6 // Kunio 8-in-1 (Pirate Cart)
|| crc == 0x9103cfd6 // HIK 7-in-1 (Pirate Cart) || crc == 0x9103cfd6 // HIK 7-in-1 (Pirate Cart)
|| crc == 0xc082e6d3) || crc == 0xc082e6d3)
{ // Super 8-in-1 (Pirate Cart) { // Super 8-in-1 (Pirate Cart)
patch = 1; patch = 1;
prg2 = 62; prg2 = 62;
prg3 = 63; prg3 = 63;
} }
if (crc == 0xe0dd259d) if (crc == 0xe0dd259d)
{ // Super 3-in-1 (Pirate Cart) { // Super 3-in-1 (Pirate Cart)
patch = 2; patch = 2;
} }
SetPROM_32K_Bank(prg0, prg1, prg2, prg3); SetPROM_32K_Bank(prg0, prg1, prg2, prg3);
p[0] = prg0; p[0] = prg0;
p[1] = prg1; p[1] = prg1;
p[2] = prg2; p[2] = prg2;
p[3] = prg3; p[3] = prg3;
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
// chr0 = c[0] = 0; // chr0 = c[0] = 0;
// chr1 = c[1] = 0 // chr1 = c[1] = 0
// chr2 = c[2] = 0; // chr2 = c[2] = 0;
// chr3 = c[3] = 0; // chr3 = c[3] = 0;
// chr4 = c[4] = 0; // chr4 = c[4] = 0;
// chr5 = c[5] = 0; // chr5 = c[5] = 0;
// chr6 = c[6] = 0; // chr6 = c[6] = 0;
// chr7 = c[7] = 0; // chr7 = c[7] = 0;
c[0] = chr0 = 0; c[0] = chr0 = 0;
c[1] = chr1 = 1; c[1] = chr1 = 1;
c[2] = chr2 = 2; c[2] = chr2 = 2;
c[3] = chr3 = 3; c[3] = chr3 = 3;
c[4] = chr4 = 4; c[4] = chr4 = 4;
c[5] = chr5 = 5; c[5] = chr5 = 5;
c[6] = chr6 = 6; c[6] = chr6 = 6;
c[7] = chr7 = 7; c[7] = chr7 = 7;
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
irq_latched = 0; irq_latched = 0;
irq_reset = 0; irq_reset = 0;
} }
//void Mapper045::WriteLow(WORD addr, BYTE data) //void Mapper045::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
// if( addr == 0x6000 ) { // if( addr == 0x6000 ) {
// if( addr == 0x6000 && !(reg[3]&0x40) ) { // if( addr == 0x6000 && !(reg[3]&0x40) ) {
if ((reg[3] & 0x40) == 0) if ((reg[3] & 0x40) == 0)
{ {
reg[reg[5]] = data; reg[reg[5]] = data;
reg[5] = (byte)((reg[5] + 1) & 0x03); reg[5] = (byte)((reg[5] + 1) & 0x03);
SetBank_CPU_4(prg0); SetBank_CPU_4(prg0);
SetBank_CPU_5(prg1); SetBank_CPU_5(prg1);
SetBank_CPU_6(prg2); SetBank_CPU_6(prg2);
SetBank_CPU_7(prg3); SetBank_CPU_7(prg3);
SetBank_PPU(); SetBank_PPU();
} }
} }
//void Mapper045::Write(WORD addr, BYTE data) //void Mapper045::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xE001) switch (addr & 0xE001)
{ {
case 0x8000: case 0x8000:
if ((data & 0x40) != (reg[6] & 0x40)) if ((data & 0x40) != (reg[6] & 0x40))
{ {
BYTE swp; BYTE swp;
swp = prg0; prg0 = prg2; prg2 = swp; swp = prg0; prg0 = prg2; prg2 = swp;
swp = p[0]; p[0] = p[2]; p[2] = swp; swp = p[0]; p[0] = p[2]; p[2] = swp;
SetBank_CPU_4(p[0]); SetBank_CPU_4(p[0]);
SetBank_CPU_5(p[1]); SetBank_CPU_5(p[1]);
} }
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
if ((data & 0x80) != (reg[6] & 0x80)) if ((data & 0x80) != (reg[6] & 0x80))
{ {
INT swp; INT swp;
swp = chr4; chr4 = chr0; chr0 = (byte)swp; swp = chr4; chr4 = chr0; chr0 = (byte)swp;
swp = chr5; chr5 = chr1; chr1 = (byte)swp; swp = chr5; chr5 = chr1; chr1 = (byte)swp;
swp = chr6; chr6 = chr2; chr2 = (byte)swp; swp = chr6; chr6 = chr2; chr2 = (byte)swp;
swp = chr7; chr7 = chr3; chr3 = (byte)swp; swp = chr7; chr7 = chr3; chr3 = (byte)swp;
swp = c[4]; c[4] = c[0]; c[0] = swp; swp = c[4]; c[4] = c[0]; c[0] = swp;
swp = c[5]; c[5] = c[1]; c[1] = swp; swp = c[5]; c[5] = c[1]; c[1] = swp;
swp = c[6]; c[6] = c[2]; c[2] = swp; swp = c[6]; c[6] = c[2]; c[2] = swp;
swp = c[7]; c[7] = c[3]; c[3] = swp; swp = c[7]; c[7] = c[3]; c[3] = swp;
SetVROM_8K_Bank(c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]); SetVROM_8K_Bank(c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
} }
} }
reg[6] = data; reg[6] = data;
break; break;
case 0x8001: case 0x8001:
switch (reg[6] & 0x07) switch (reg[6] & 0x07)
{ {
case 0x00: case 0x00:
chr0 = (byte)((data & 0xFE) + 0); chr0 = (byte)((data & 0xFE) + 0);
chr1 = (byte)((data & 0xFE) + 1); chr1 = (byte)((data & 0xFE) + 1);
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x01: case 0x01:
chr2 = (byte)((data & 0xFE) + 0); chr2 = (byte)((data & 0xFE) + 0);
chr3 = (byte)((data & 0xFE) + 1); chr3 = (byte)((data & 0xFE) + 1);
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x02: case 0x02:
chr4 = data; chr4 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x03: case 0x03:
chr5 = data; chr5 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x04: case 0x04:
chr6 = data; chr6 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x05: case 0x05:
chr7 = data; chr7 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x06: case 0x06:
if ((reg[6] & 0x40) != 0) if ((reg[6] & 0x40) != 0)
{ {
prg2 = (byte)(data & 0x3F); prg2 = (byte)(data & 0x3F);
SetBank_CPU_6(data); SetBank_CPU_6(data);
} }
else else
{ {
prg0 = (byte)(data & 0x3F); prg0 = (byte)(data & 0x3F);
SetBank_CPU_4(data); SetBank_CPU_4(data);
} }
break; break;
case 0x07: case 0x07:
prg1 = (byte)(data & 0x3F); prg1 = (byte)(data & 0x3F);
SetBank_CPU_5(data); SetBank_CPU_5(data);
break; break;
} }
break; break;
case 0xA000: case 0xA000:
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
case 0xC000: case 0xC000:
if (patch == 2) if (patch == 2)
{ {
if (data == 0x29 || data == 0x70) if (data == 0x29 || data == 0x70)
data = 0x07; data = 0x07;
} }
irq_latch = data; irq_latch = data;
irq_latched = 1; irq_latched = 1;
if (irq_reset != 0) if (irq_reset != 0)
{ {
irq_counter = data; irq_counter = data;
irq_latched = 0; irq_latched = 0;
} }
// irq_counter = data; // irq_counter = data;
break; break;
case 0xC001: case 0xC001:
// irq_latch = data; // irq_latch = data;
irq_counter = irq_latch; irq_counter = irq_latch;
break; break;
case 0xE000: case 0xE000:
irq_enable = 0; irq_enable = 0;
irq_reset = 1; irq_reset = 1;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xE001: case 0xE001:
irq_enable = 1; irq_enable = 1;
if (irq_latched != 0) if (irq_latched != 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
} }
break; break;
} }
} }
//void Mapper045::HSync(INT scanline) //void Mapper045::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
irq_reset = 0; irq_reset = 0;
if ((scanline >= 0 && scanline <= 239) && nes.ppu.IsDispON()) if ((scanline >= 0 && scanline <= 239) && nes.ppu.IsDispON())
{ {
if (irq_counter != 0) if (irq_counter != 0)
{ {
irq_counter--; irq_counter--;
if (irq_counter == 0) if (irq_counter == 0)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
} }
} }
void SetBank_CPU_4(INT data) void SetBank_CPU_4(INT data)
{ {
data &= (reg[3] & 0x3F) ^ 0xFF; data &= (reg[3] & 0x3F) ^ 0xFF;
data &= 0x3F; data &= 0x3F;
data |= reg[1]; data |= reg[1];
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
p[0] = (byte)data; p[0] = (byte)data;
} }
void SetBank_CPU_5(INT data) void SetBank_CPU_5(INT data)
{ {
data &= (reg[3] & 0x3F) ^ 0xFF; data &= (reg[3] & 0x3F) ^ 0xFF;
data &= 0x3F; data &= 0x3F;
data |= reg[1]; data |= reg[1];
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
p[1] = (byte)data; p[1] = (byte)data;
} }
void SetBank_CPU_6(INT data) void SetBank_CPU_6(INT data)
{ {
data &= (reg[3] & 0x3F) ^ 0xFF; data &= (reg[3] & 0x3F) ^ 0xFF;
data &= 0x3F; data &= 0x3F;
data |= reg[1]; data |= reg[1];
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
p[2] = (byte)data; p[2] = (byte)data;
} }
void SetBank_CPU_7(INT data) void SetBank_CPU_7(INT data)
{ {
data &= (reg[3] & 0x3F) ^ 0xFF; data &= (reg[3] & 0x3F) ^ 0xFF;
data &= 0x3F; data &= 0x3F;
data |= reg[1]; data |= reg[1];
SetPROM_8K_Bank(7, data); SetPROM_8K_Bank(7, data);
p[3] = (byte)data; p[3] = (byte)data;
} }
void SetBank_PPU() void SetBank_PPU()
{ {
BYTE[] table = new byte[] { BYTE[] table = new byte[] {
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x01,0x03,0x07,0x0F,0x1F,0x3F,0x7F,0xFF 0x01,0x03,0x07,0x0F,0x1F,0x3F,0x7F,0xFF
}; };
c[0] = chr0; c[0] = chr0;
c[1] = chr1; c[1] = chr1;
c[2] = chr2; c[2] = chr2;
c[3] = chr3; c[3] = chr3;
c[4] = chr4; c[4] = chr4;
c[5] = chr5; c[5] = chr5;
c[6] = chr6; c[6] = chr6;
c[7] = chr7; c[7] = chr7;
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
c[i] &= table[reg[2] & 0x0F]; c[i] &= table[reg[2] & 0x0F];
c[i] |= reg[0] & ((patch != 1) ? 0xFF : 0xC0); c[i] |= reg[0] & ((patch != 1) ? 0xFF : 0xC0);
c[i] += (reg[2] & ((patch != 1) ? 0x10 : 0x30)) << 4; c[i] += (reg[2] & ((patch != 1) ? 0x10 : 0x30)) << 4;
} }
if ((reg[6] & 0x80) != 0) if ((reg[6] & 0x80) != 0)
{ {
SetVROM_8K_Bank(c[4], c[5], c[6], c[7], c[0], c[1], c[2], c[3]); SetVROM_8K_Bank(c[4], c[5], c[6], c[7], c[0], c[1], c[2], c[3]);
} }
else else
{ {
SetVROM_8K_Bank(c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]); SetVROM_8K_Bank(c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
} }
} }
//void Mapper045::SaveState(LPBYTE ps) //void Mapper045::SaveState(LPBYTE ps)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//INT i; //INT i;
//for (i = 0; i < 8; i++) //for (i = 0; i < 8; i++)
//{ //{
// ps[i] = reg[i]; // ps[i] = reg[i];
//} //}
//for (i = 0; i < 4; i++) //for (i = 0; i < 4; i++)
//{ //{
// ps[i + 8] = p[i]; // ps[i + 8] = p[i];
//} //}
//for (i = 0; i < 8; i++) //for (i = 0; i < 8; i++)
//{ //{
// *(INT*)&ps[i * 4 + 64] = c[i]; // *(INT*)&ps[i * 4 + 64] = c[i];
//} //}
//ps[20] = prg0; //ps[20] = prg0;
//ps[21] = prg1; //ps[21] = prg1;
//ps[22] = prg2; //ps[22] = prg2;
//ps[23] = prg3; //ps[23] = prg3;
//ps[24] = chr0; //ps[24] = chr0;
//ps[25] = chr1; //ps[25] = chr1;
//ps[26] = chr2; //ps[26] = chr2;
//ps[27] = chr3; //ps[27] = chr3;
//ps[28] = chr4; //ps[28] = chr4;
//ps[29] = chr5; //ps[29] = chr5;
//ps[30] = chr6; //ps[30] = chr6;
//ps[31] = chr7; //ps[31] = chr7;
//ps[32] = irq_enable; //ps[32] = irq_enable;
//ps[33] = irq_counter; //ps[33] = irq_counter;
//ps[34] = irq_latch; //ps[34] = irq_latch;
} }
//void Mapper045::LoadState(LPBYTE ps) //void Mapper045::LoadState(LPBYTE ps)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//INT i; //INT i;
//for (i = 0; i < 8; i++) //for (i = 0; i < 8; i++)
//{ //{
// reg[i] = ps[i]; // reg[i] = ps[i];
//} //}
//for (i = 0; i < 4; i++) //for (i = 0; i < 4; i++)
//{ //{
// p[i] = ps[i + 8]; // p[i] = ps[i + 8];
//} //}
//for (i = 0; i < 8; i++) //for (i = 0; i < 8; i++)
//{ //{
// c[i] = *(INT*)&ps[i * 4 + 64]; // c[i] = *(INT*)&ps[i * 4 + 64];
//} //}
//prg0 = ps[20]; //prg0 = ps[20];
//prg1 = ps[21]; //prg1 = ps[21];
//prg2 = ps[22]; //prg2 = ps[22];
//prg3 = ps[23]; //prg3 = ps[23];
//chr0 = ps[24]; //chr0 = ps[24];
//chr1 = ps[25]; //chr1 = ps[25];
//chr2 = ps[26]; //chr2 = ps[26];
//chr3 = ps[27]; //chr3 = ps[27];
//chr4 = ps[28]; //chr4 = ps[28];
//chr5 = ps[29]; //chr5 = ps[29];
//chr6 = ps[30]; //chr6 = ps[30];
//chr7 = ps[31]; //chr7 = ps[31];
//irq_enable = ps[32]; //irq_enable = ps[32];
//irq_counter = ps[33]; //irq_counter = ps[33];
//irq_latch = ps[34]; //irq_latch = ps[34];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

135
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper046.cs
View File

@ -2,87 +2,84 @@
// Mapper046 Rumble Station // // Mapper046 Rumble Station //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper046 : Mapper public class Mapper046 : Mapper
{ {
int[] reg = new int[4]; int[] reg = new int[4];
public Mapper046(NES parent) : base(parent) public Mapper046(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
reg[0] = 0; reg[0] = 0;
reg[1] = 0; reg[1] = 0;
reg[2] = 0; reg[2] = 0;
reg[3] = 0; reg[3] = 0;
SetBank(); SetBank();
SetVRAM_Mirror(VRAM_VMIRROR); SetVRAM_Mirror(VRAM_VMIRROR);
} }
//void Mapper046::WriteLow(WORD addr, BYTE data) //void Mapper046::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
reg[0] = data & 0x0F; reg[0] = data & 0x0F;
reg[1] = (data & 0xF0) >> 4; reg[1] = (data & 0xF0) >> 4;
SetBank(); SetBank();
} }
//void Mapper046::Write(WORD addr, BYTE data) //void Mapper046::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
reg[2] = data & 0x01; reg[2] = data & 0x01;
reg[3] = (data & 0x70) >> 4; reg[3] = (data & 0x70) >> 4;
SetBank(); SetBank();
} }
void SetBank() void SetBank()
{ {
SetPROM_8K_Bank(4, reg[0] * 8 + reg[2] * 4 + 0); SetPROM_8K_Bank(4, reg[0] * 8 + reg[2] * 4 + 0);
SetPROM_8K_Bank(5, reg[0] * 8 + reg[2] * 4 + 1); SetPROM_8K_Bank(5, reg[0] * 8 + reg[2] * 4 + 1);
SetPROM_8K_Bank(6, reg[0] * 8 + reg[2] * 4 + 2); SetPROM_8K_Bank(6, reg[0] * 8 + reg[2] * 4 + 2);
SetPROM_8K_Bank(7, reg[0] * 8 + reg[2] * 4 + 3); SetPROM_8K_Bank(7, reg[0] * 8 + reg[2] * 4 + 3);
SetVROM_1K_Bank(0, reg[1] * 64 + reg[3] * 8 + 0); SetVROM_1K_Bank(0, reg[1] * 64 + reg[3] * 8 + 0);
SetVROM_1K_Bank(1, reg[1] * 64 + reg[3] * 8 + 1); SetVROM_1K_Bank(1, reg[1] * 64 + reg[3] * 8 + 1);
SetVROM_1K_Bank(2, reg[1] * 64 + reg[3] * 8 + 2); SetVROM_1K_Bank(2, reg[1] * 64 + reg[3] * 8 + 2);
SetVROM_1K_Bank(3, reg[1] * 64 + reg[3] * 8 + 3); SetVROM_1K_Bank(3, reg[1] * 64 + reg[3] * 8 + 3);
SetVROM_1K_Bank(4, reg[1] * 64 + reg[3] * 8 + 4); SetVROM_1K_Bank(4, reg[1] * 64 + reg[3] * 8 + 4);
SetVROM_1K_Bank(5, reg[1] * 64 + reg[3] * 8 + 5); SetVROM_1K_Bank(5, reg[1] * 64 + reg[3] * 8 + 5);
SetVROM_1K_Bank(6, reg[1] * 64 + reg[3] * 8 + 6); SetVROM_1K_Bank(6, reg[1] * 64 + reg[3] * 8 + 6);
SetVROM_1K_Bank(7, reg[1] * 64 + reg[3] * 8 + 7); SetVROM_1K_Bank(7, reg[1] * 64 + reg[3] * 8 + 7);
} }
//void Mapper046::SaveState(LPBYTE p) //void Mapper046::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = (byte)reg[0]; p[0] = (byte)reg[0];
p[1] = (byte)reg[1]; p[1] = (byte)reg[1];
p[2] = (byte)reg[2]; p[2] = (byte)reg[2];
p[3] = (byte)reg[3]; p[3] = (byte)reg[3];
} }
//void Mapper046::LoadState(LPBYTE p) //void Mapper046::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg[0] = p[0]; reg[0] = p[0];
reg[1] = p[1]; reg[1] = p[1];
reg[2] = p[2]; reg[2] = p[2];
reg[3] = p[3]; reg[3] = p[3];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

495
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper047.cs
View File

@ -1,275 +1,274 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper047 NES-QJ // // Mapper047 NES-QJ //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using INT = System.Int32;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper047 : Mapper public class Mapper047 : Mapper
{ {
BYTE[] reg = new byte[8]; BYTE[] reg = new byte[8];
BYTE patch; BYTE patch;
BYTE bank; BYTE bank;
BYTE prg0, prg1; BYTE prg0, prg1;
BYTE chr01, chr23, chr4, chr5, chr6, chr7; BYTE chr01, chr23, chr4, chr5, chr6, chr7;
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
public Mapper047(NES parent) : base(parent) public Mapper047(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
patch = 0; patch = 0;
if (nes.rom.GetPROM_CRC() == 0x7eef434c) if (nes.rom.GetPROM_CRC() == 0x7eef434c)
{ {
patch = 1; patch = 1;
} }
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
reg[i] = 0; reg[i] = 0;
} }
bank = 0; bank = 0;
prg0 = 0; prg0 = 0;
prg1 = 1; prg1 = 1;
// set VROM banks // set VROM banks
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
chr01 = 0; chr01 = 0;
chr23 = 2; chr23 = 2;
chr4 = 4; chr4 = 4;
chr5 = 5; chr5 = 5;
chr6 = 6; chr6 = 6;
chr7 = 7; chr7 = 7;
} }
else else
{ {
chr01 = chr23 = chr4 = chr5 = chr6 = chr7 = 0; chr01 = chr23 = chr4 = chr5 = chr6 = chr7 = 0;
} }
SetBank_CPU(); SetBank_CPU();
SetBank_PPU(); SetBank_PPU();
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
} }
//void Mapper047::WriteLow(WORD addr, BYTE data) //void Mapper047::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if (addr == 0x6000) if (addr == 0x6000)
{ {
if (patch != 0) if (patch != 0)
{ {
bank = (byte)((data & 0x06) >> 1); bank = (byte)((data & 0x06) >> 1);
} }
else else
{ {
bank = (byte)((data & 0x01) << 1); bank = (byte)((data & 0x01) << 1);
} }
SetBank_CPU(); SetBank_CPU();
SetBank_PPU(); SetBank_PPU();
} }
} }
//void Mapper047::Write(WORD addr, BYTE data) //void Mapper047::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xE001) switch (addr & 0xE001)
{ {
case 0x8000: case 0x8000:
reg[0] = data; reg[0] = data;
SetBank_CPU(); SetBank_CPU();
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x8001: case 0x8001:
reg[1] = data; reg[1] = data;
switch (reg[0] & 0x07) switch (reg[0] & 0x07)
{ {
case 0x00: case 0x00:
chr01 = (byte)(data & 0xFE); chr01 = (byte)(data & 0xFE);
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x01: case 0x01:
chr23 = (byte)(data & 0xFE); chr23 = (byte)(data & 0xFE);
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x02: case 0x02:
chr4 = data; chr4 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x03: case 0x03:
chr5 = data; chr5 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x04: case 0x04:
chr6 = data; chr6 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x05: case 0x05:
chr7 = data; chr7 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x06: case 0x06:
prg0 = data; prg0 = data;
SetBank_CPU(); SetBank_CPU();
break; break;
case 0x07: case 0x07:
prg1 = data; prg1 = data;
SetBank_CPU(); SetBank_CPU();
break; break;
} }
break; break;
case 0xA000: case 0xA000:
reg[2] = data; reg[2] = data;
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
case 0xA001: case 0xA001:
reg[3] = data; reg[3] = data;
break; break;
case 0xC000: case 0xC000:
reg[4] = data; reg[4] = data;
irq_counter = data; irq_counter = data;
break; break;
case 0xC001: case 0xC001:
reg[5] = data; reg[5] = data;
irq_latch = data; irq_latch = data;
break; break;
case 0xE000: case 0xE000:
reg[6] = data; reg[6] = data;
irq_enable = 0; irq_enable = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xE001: case 0xE001:
reg[7] = data; reg[7] = data;
irq_enable = 1; irq_enable = 1;
break; break;
} }
} }
//void Mapper047::HSync(INT scanline) //void Mapper047::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if ((scanline >= 0 && scanline <= 239)) if ((scanline >= 0 && scanline <= 239))
{ {
if (nes.ppu.IsDispON()) if (nes.ppu.IsDispON())
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if ((--irq_counter) == 0) if ((--irq_counter) == 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
// nes.cpu.IRQ(); // nes.cpu.IRQ();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
} }
} }
void SetBank_CPU() void SetBank_CPU()
{ {
if ((reg[0] & 0x40) != 0) if ((reg[0] & 0x40) != 0)
{ {
SetPROM_8K_Bank(4, bank * 8 + ((patch != 0 && bank != 2) ? 6 : 14)); SetPROM_8K_Bank(4, bank * 8 + ((patch != 0 && bank != 2) ? 6 : 14));
SetPROM_8K_Bank(5, bank * 8 + prg1); SetPROM_8K_Bank(5, bank * 8 + prg1);
SetPROM_8K_Bank(6, bank * 8 + prg0); SetPROM_8K_Bank(6, bank * 8 + prg0);
SetPROM_8K_Bank(7, bank * 8 + ((patch != 0 && bank != 2) ? 7 : 15)); SetPROM_8K_Bank(7, bank * 8 + ((patch != 0 && bank != 2) ? 7 : 15));
} }
else else
{ {
SetPROM_8K_Bank(4, bank * 8 + prg0); SetPROM_8K_Bank(4, bank * 8 + prg0);
SetPROM_8K_Bank(5, bank * 8 + prg1); SetPROM_8K_Bank(5, bank * 8 + prg1);
SetPROM_8K_Bank(6, bank * 8 + ((patch != 0 && bank != 2) ? 6 : 14)); SetPROM_8K_Bank(6, bank * 8 + ((patch != 0 && bank != 2) ? 6 : 14));
SetPROM_8K_Bank(7, bank * 8 + ((patch != 0 && bank != 2) ? 7 : 15)); SetPROM_8K_Bank(7, bank * 8 + ((patch != 0 && bank != 2) ? 7 : 15));
} }
} }
void SetBank_PPU() void SetBank_PPU()
{ {
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
if ((reg[0] & 0x80) != 0) if ((reg[0] & 0x80) != 0)
{ {
SetVROM_1K_Bank(0, (bank & 0x02) * 64 + chr4); SetVROM_1K_Bank(0, (bank & 0x02) * 64 + chr4);
SetVROM_1K_Bank(1, (bank & 0x02) * 64 + chr5); SetVROM_1K_Bank(1, (bank & 0x02) * 64 + chr5);
SetVROM_1K_Bank(2, (bank & 0x02) * 64 + chr6); SetVROM_1K_Bank(2, (bank & 0x02) * 64 + chr6);
SetVROM_1K_Bank(3, (bank & 0x02) * 64 + chr7); SetVROM_1K_Bank(3, (bank & 0x02) * 64 + chr7);
SetVROM_1K_Bank(4, (bank & 0x02) * 64 + chr01 + 0); SetVROM_1K_Bank(4, (bank & 0x02) * 64 + chr01 + 0);
SetVROM_1K_Bank(5, (bank & 0x02) * 64 + chr01 + 1); SetVROM_1K_Bank(5, (bank & 0x02) * 64 + chr01 + 1);
SetVROM_1K_Bank(6, (bank & 0x02) * 64 + chr23 + 0); SetVROM_1K_Bank(6, (bank & 0x02) * 64 + chr23 + 0);
SetVROM_1K_Bank(7, (bank & 0x02) * 64 + chr23 + 1); SetVROM_1K_Bank(7, (bank & 0x02) * 64 + chr23 + 1);
} }
else else
{ {
SetVROM_1K_Bank(0, (bank & 0x02) * 64 + chr01 + 0); SetVROM_1K_Bank(0, (bank & 0x02) * 64 + chr01 + 0);
SetVROM_1K_Bank(1, (bank & 0x02) * 64 + chr01 + 1); SetVROM_1K_Bank(1, (bank & 0x02) * 64 + chr01 + 1);
SetVROM_1K_Bank(2, (bank & 0x02) * 64 + chr23 + 0); SetVROM_1K_Bank(2, (bank & 0x02) * 64 + chr23 + 0);
SetVROM_1K_Bank(3, (bank & 0x02) * 64 + chr23 + 1); SetVROM_1K_Bank(3, (bank & 0x02) * 64 + chr23 + 1);
SetVROM_1K_Bank(4, (bank & 0x02) * 64 + chr4); SetVROM_1K_Bank(4, (bank & 0x02) * 64 + chr4);
SetVROM_1K_Bank(5, (bank & 0x02) * 64 + chr5); SetVROM_1K_Bank(5, (bank & 0x02) * 64 + chr5);
SetVROM_1K_Bank(6, (bank & 0x02) * 64 + chr6); SetVROM_1K_Bank(6, (bank & 0x02) * 64 + chr6);
SetVROM_1K_Bank(7, (bank & 0x02) * 64 + chr7); SetVROM_1K_Bank(7, (bank & 0x02) * 64 + chr7);
} }
} }
} }
//void Mapper047::SaveState(LPBYTE p) //void Mapper047::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
p[i] = reg[i]; p[i] = reg[i];
} }
p[8] = prg0; p[8] = prg0;
p[9] = prg1; p[9] = prg1;
p[10] = chr01; p[10] = chr01;
p[11] = chr23; p[11] = chr23;
p[12] = chr4; p[12] = chr4;
p[13] = chr5; p[13] = chr5;
p[14] = chr6; p[14] = chr6;
p[15] = chr7; p[15] = chr7;
p[16] = irq_enable; p[16] = irq_enable;
p[17] = irq_counter; p[17] = irq_counter;
p[18] = irq_latch; p[18] = irq_latch;
p[19] = bank; p[19] = bank;
} }
//void Mapper047::LoadState(LPBYTE p) //void Mapper047::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
reg[i] = p[i]; reg[i] = p[i];
} }
prg0 = p[8]; prg0 = p[8];
prg1 = p[9]; prg1 = p[9];
chr01 = p[10]; chr01 = p[10];
chr23 = p[11]; chr23 = p[11];
chr4 = p[12]; chr4 = p[12];
chr5 = p[13]; chr5 = p[13];
chr6 = p[14]; chr6 = p[14];
chr7 = p[15]; chr7 = p[15];
irq_enable = p[16]; irq_enable = p[16];
irq_counter = p[17]; irq_counter = p[17];
irq_latch = p[18]; irq_latch = p[18];
bank = p[19]; bank = p[19];
} }
} }
} }

236
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper048.cs
View File

@ -1,143 +1,141 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper048 Taito TC190V // // Mapper048 Taito TC190V //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper048 : Mapper public class Mapper048 : Mapper
{ {
BYTE reg; BYTE reg;
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
public Mapper048(NES parent) : base(parent) public Mapper048(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
reg = 0; reg = 0;
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
// if( crc == 0x547e6cc1 ) { // Flintstones - The Rescue of Dino & Hoppy(J) // if( crc == 0x547e6cc1 ) { // Flintstones - The Rescue of Dino & Hoppy(J)
// nes.SetRenderMethod( NES::POST_RENDER ); // nes.SetRenderMethod( NES::POST_RENDER );
// } // }
} }
//void Mapper048::Write(WORD addr, BYTE data) //void Mapper048::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
if (reg == 0) if (reg == 0)
{ {
if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
} }
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0x8001: case 0x8001:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0x8002: case 0x8002:
SetVROM_2K_Bank(0, data); SetVROM_2K_Bank(0, data);
break; break;
case 0x8003: case 0x8003:
SetVROM_2K_Bank(2, data); SetVROM_2K_Bank(2, data);
break; break;
case 0xA000: case 0xA000:
SetVROM_1K_Bank(4, data); SetVROM_1K_Bank(4, data);
break; break;
case 0xA001: case 0xA001:
SetVROM_1K_Bank(5, data); SetVROM_1K_Bank(5, data);
break; break;
case 0xA002: case 0xA002:
SetVROM_1K_Bank(6, data); SetVROM_1K_Bank(6, data);
break; break;
case 0xA003: case 0xA003:
SetVROM_1K_Bank(7, data); SetVROM_1K_Bank(7, data);
break; break;
case 0xC000: case 0xC000:
irq_counter = data; irq_counter = data;
irq_enable = 0; irq_enable = 0;
// nes.cpu.ClrIRQ( IRQ_MAPPER ); // nes.cpu.ClrIRQ( IRQ_MAPPER );
break; break;
case 0xC001: case 0xC001:
irq_counter = data; irq_counter = data;
irq_enable = 1; irq_enable = 1;
// irq_enable = data & 0x01; // irq_enable = data & 0x01;
// nes.cpu.ClrIRQ( IRQ_MAPPER ); // nes.cpu.ClrIRQ( IRQ_MAPPER );
break; break;
case 0xC002: case 0xC002:
break; break;
case 0xC003: case 0xC003:
break; break;
case 0xE000: case 0xE000:
if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
reg = 1; reg = 1;
break; break;
} }
} }
//void Mapper048::HSync(INT scanline) //void Mapper048::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if ((scanline >= 0 && scanline <= 239)) if ((scanline >= 0 && scanline <= 239))
{ {
if (nes.ppu.IsDispON()) if (nes.ppu.IsDispON())
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if (irq_counter == 0xFF) if (irq_counter == 0xFF)
{ {
// nes.cpu.IRQ_NotPending(); // nes.cpu.IRQ_NotPending();
// nes.cpu.SetIRQ( IRQ_MAPPER ); // nes.cpu.SetIRQ( IRQ_MAPPER );
nes.cpu.SetIRQ(IRQ_TRIGGER2); nes.cpu.SetIRQ(IRQ_TRIGGER2);
} }
irq_counter++; irq_counter++;
} }
} }
} }
} }
//void Mapper048::SaveState(LPBYTE p) //void Mapper048::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg; p[0] = reg;
p[1] = irq_enable; p[1] = irq_enable;
p[2] = irq_counter; p[2] = irq_counter;
} }
//void Mapper048::LoadState(LPBYTE p) //void Mapper048::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg = p[0]; reg = p[0];
irq_enable = p[1]; irq_enable = p[1];
irq_counter = p[2]; irq_counter = p[2];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

162
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper050.cs
View File

@ -1,100 +1,98 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper050 SMB2J // // Mapper050 SMB2J //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper050 : Mapper public class Mapper050 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
public Mapper050(NES parent) : base(parent) public Mapper050(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
irq_enable = 0; irq_enable = 0;
SetPROM_8K_Bank(3, 15); SetPROM_8K_Bank(3, 15);
SetPROM_8K_Bank(4, 8); SetPROM_8K_Bank(4, 8);
SetPROM_8K_Bank(5, 9); SetPROM_8K_Bank(5, 9);
SetPROM_8K_Bank(6, 0); SetPROM_8K_Bank(6, 0);
SetPROM_8K_Bank(7, 11); SetPROM_8K_Bank(7, 11);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper050::ExWrite(WORD addr, BYTE data) //void Mapper050::ExWrite(WORD addr, BYTE data)
public override void ExWrite(ushort addr, byte data) public override void ExWrite(ushort addr, byte data)
{ {
if ((addr & 0xE060) == 0x4020) if ((addr & 0xE060) == 0x4020)
{ {
if ((addr & 0x0100) != 0) if ((addr & 0x0100) != 0)
{ {
irq_enable = (byte)(data & 0x01); irq_enable = (byte)(data & 0x01);
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
} }
else else
{ {
SetPROM_8K_Bank(6, (data & 0x08) | ((data & 0x01) << 2) | ((data & 0x06) >> 1)); SetPROM_8K_Bank(6, (data & 0x08) | ((data & 0x01) << 2) | ((data & 0x06) >> 1));
} }
} }
} }
//void Mapper050::WriteLow(WORD addr, BYTE data) //void Mapper050::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if ((addr & 0xE060) == 0x4020) if ((addr & 0xE060) == 0x4020)
{ {
if ((addr & 0x0100) != 0) if ((addr & 0x0100) != 0)
{ {
irq_enable = (byte)(data & 0x01); irq_enable = (byte)(data & 0x01);
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
} }
else else
{ {
SetPROM_8K_Bank(6, (data & 0x08) | ((data & 0x01) << 2) | ((data & 0x06) >> 1)); SetPROM_8K_Bank(6, (data & 0x08) | ((data & 0x01) << 2) | ((data & 0x06) >> 1));
} }
} }
} }
//void Mapper050::HSync(INT scanline) //void Mapper050::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if (scanline == 21) if (scanline == 21)
{ {
// nes.cpu.IRQ(); // nes.cpu.IRQ();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
//void Mapper050::SaveState(LPBYTE p) //void Mapper050::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = irq_enable; p[0] = irq_enable;
} }
//void Mapper050::LoadState(LPBYTE p) //void Mapper050::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
irq_enable = p[0]; irq_enable = p[0];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

180
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper051.cs
View File

@ -2,108 +2,104 @@
// Mapper051 11-in-1 // // Mapper051 11-in-1 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper051 : Mapper public class Mapper051 : Mapper
{ {
int mode, bank; int mode, bank;
public Mapper051(NES parent) : base(parent) public Mapper051(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
bank = 0; bank = 0;
mode = 1; mode = 1;
SetBank_CPU(); SetBank_CPU();
SetCRAM_8K_Bank(0); SetCRAM_8K_Bank(0);
} }
//void Mapper051::WriteLow(WORD addr, BYTE data) //void Mapper051::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if (addr >= 0x6000) if (addr >= 0x6000)
{ {
mode = ((data & 0x10) >> 3) | ((data & 0x02) >> 1); mode = ((data & 0x10) >> 3) | ((data & 0x02) >> 1);
SetBank_CPU(); SetBank_CPU();
} }
} }
//void Mapper051::Write(WORD addr, BYTE data) //void Mapper051::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
bank = (data & 0x0f) << 2; bank = (data & 0x0f) << 2;
if (0xC000 <= addr && addr <= 0xDFFF) if (0xC000 <= addr && addr <= 0xDFFF)
{ {
mode = (mode & 0x01) | ((data & 0x10) >> 3); mode = (mode & 0x01) | ((data & 0x10) >> 3);
} }
SetBank_CPU(); SetBank_CPU();
} }
void SetBank_CPU() void SetBank_CPU()
{ {
switch (mode) switch (mode)
{ {
case 0: case 0:
SetVRAM_Mirror(VRAM_VMIRROR); SetVRAM_Mirror(VRAM_VMIRROR);
SetPROM_8K_Bank(3, (bank | 0x2c | 3)); SetPROM_8K_Bank(3, (bank | 0x2c | 3));
SetPROM_8K_Bank(4, (bank | 0x00 | 0)); SetPROM_8K_Bank(4, (bank | 0x00 | 0));
SetPROM_8K_Bank(5, (bank | 0x00 | 1)); SetPROM_8K_Bank(5, (bank | 0x00 | 1));
SetPROM_8K_Bank(6, (bank | 0x0c | 2)); SetPROM_8K_Bank(6, (bank | 0x0c | 2));
SetPROM_8K_Bank(7, (bank | 0x0c | 3)); SetPROM_8K_Bank(7, (bank | 0x0c | 3));
break; break;
case 1: case 1:
SetVRAM_Mirror(VRAM_VMIRROR); SetVRAM_Mirror(VRAM_VMIRROR);
SetPROM_8K_Bank(3, (bank | 0x20 | 3)); SetPROM_8K_Bank(3, (bank | 0x20 | 3));
SetPROM_8K_Bank(4, (bank | 0x00 | 0)); SetPROM_8K_Bank(4, (bank | 0x00 | 0));
SetPROM_8K_Bank(5, (bank | 0x00 | 1)); SetPROM_8K_Bank(5, (bank | 0x00 | 1));
SetPROM_8K_Bank(6, (bank | 0x00 | 2)); SetPROM_8K_Bank(6, (bank | 0x00 | 2));
SetPROM_8K_Bank(7, (bank | 0x00 | 3)); SetPROM_8K_Bank(7, (bank | 0x00 | 3));
break; break;
case 2: case 2:
SetVRAM_Mirror(VRAM_VMIRROR); SetVRAM_Mirror(VRAM_VMIRROR);
SetPROM_8K_Bank(3, (bank | 0x2e | 3)); SetPROM_8K_Bank(3, (bank | 0x2e | 3));
SetPROM_8K_Bank(4, (bank | 0x02 | 0)); SetPROM_8K_Bank(4, (bank | 0x02 | 0));
SetPROM_8K_Bank(5, (bank | 0x02 | 1)); SetPROM_8K_Bank(5, (bank | 0x02 | 1));
SetPROM_8K_Bank(6, (bank | 0x0e | 2)); SetPROM_8K_Bank(6, (bank | 0x0e | 2));
SetPROM_8K_Bank(7, (bank | 0x0e | 3)); SetPROM_8K_Bank(7, (bank | 0x0e | 3));
break; break;
case 3: case 3:
SetVRAM_Mirror(VRAM_HMIRROR); SetVRAM_Mirror(VRAM_HMIRROR);
SetPROM_8K_Bank(3, (bank | 0x20 | 3)); SetPROM_8K_Bank(3, (bank | 0x20 | 3));
SetPROM_8K_Bank(4, (bank | 0x00 | 0)); SetPROM_8K_Bank(4, (bank | 0x00 | 0));
SetPROM_8K_Bank(5, (bank | 0x00 | 1)); SetPROM_8K_Bank(5, (bank | 0x00 | 1));
SetPROM_8K_Bank(6, (bank | 0x00 | 2)); SetPROM_8K_Bank(6, (bank | 0x00 | 2));
SetPROM_8K_Bank(7, (bank | 0x00 | 3)); SetPROM_8K_Bank(7, (bank | 0x00 | 3));
break; break;
} }
} }
//void Mapper051::SaveState(LPBYTE p) //void Mapper051::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = (byte)mode; p[0] = (byte)mode;
p[1] = (byte)bank; p[1] = (byte)bank;
} }
//void Mapper051::LoadState(LPBYTE p) //void Mapper051::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
mode = p[0]; mode = p[0];
bank = p[1]; bank = p[1];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

131
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper057.cs
View File

@ -2,86 +2,83 @@
// Mapper057 // // Mapper057 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper057 : Mapper public class Mapper057 : Mapper
{ {
BYTE reg; BYTE reg;
public Mapper057(NES parent) : base(parent) public Mapper057(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, 0, 1); SetPROM_32K_Bank(0, 1, 0, 1);
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
reg = 0; reg = 0;
} }
//void Mapper057::Write(WORD addr, BYTE data) //void Mapper057::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
case 0x8001: case 0x8001:
case 0x8002: case 0x8002:
case 0x8003: case 0x8003:
if ((data & 0x40) != 0) if ((data & 0x40) != 0)
{ {
SetVROM_8K_Bank((data & 0x03) + ((reg & 0x10) >> 1) + (reg & 0x07)); SetVROM_8K_Bank((data & 0x03) + ((reg & 0x10) >> 1) + (reg & 0x07));
} }
break; break;
case 0x8800: case 0x8800:
reg = data; reg = data;
if ((data & 0x80) != 0) if ((data & 0x80) != 0)
{ {
SetPROM_8K_Bank(4, ((data & 0x40) >> 6) * 4 + 8 + 0); SetPROM_8K_Bank(4, ((data & 0x40) >> 6) * 4 + 8 + 0);
SetPROM_8K_Bank(5, ((data & 0x40) >> 6) * 4 + 8 + 1); SetPROM_8K_Bank(5, ((data & 0x40) >> 6) * 4 + 8 + 1);
SetPROM_8K_Bank(6, ((data & 0x40) >> 6) * 4 + 8 + 2); SetPROM_8K_Bank(6, ((data & 0x40) >> 6) * 4 + 8 + 2);
SetPROM_8K_Bank(7, ((data & 0x40) >> 6) * 4 + 8 + 3); SetPROM_8K_Bank(7, ((data & 0x40) >> 6) * 4 + 8 + 3);
} }
else else
{ {
SetPROM_8K_Bank(4, ((data & 0x60) >> 5) * 2 + 0); SetPROM_8K_Bank(4, ((data & 0x60) >> 5) * 2 + 0);
SetPROM_8K_Bank(5, ((data & 0x60) >> 5) * 2 + 1); SetPROM_8K_Bank(5, ((data & 0x60) >> 5) * 2 + 1);
SetPROM_8K_Bank(6, ((data & 0x60) >> 5) * 2 + 0); SetPROM_8K_Bank(6, ((data & 0x60) >> 5) * 2 + 0);
SetPROM_8K_Bank(7, ((data & 0x60) >> 5) * 2 + 1); SetPROM_8K_Bank(7, ((data & 0x60) >> 5) * 2 + 1);
} }
SetVROM_8K_Bank((data & 0x07) + ((data & 0x10) >> 1)); SetVROM_8K_Bank((data & 0x07) + ((data & 0x10) >> 1));
if ((data & 0x08) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x08) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
} }
} }
//void Mapper057::SaveState(LPBYTE p) //void Mapper057::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg; p[0] = reg;
} }
//void Mapper057::LoadState(LPBYTE p) //void Mapper057::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg = p[0]; reg = p[0];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

72
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper058.cs
View File

@ -2,52 +2,48 @@
// Mapper058 // // Mapper058 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper058 : Mapper public class Mapper058 : Mapper
{ {
public Mapper058(NES parent) : base(parent) public Mapper058(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, 0, 1); SetPROM_32K_Bank(0, 1, 0, 1);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper058::Write(WORD addr, BYTE data) //void Mapper058::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
if ((addr & 0x40) != 0) if ((addr & 0x40) != 0)
{ {
SetPROM_16K_Bank(4, addr & 0x07); SetPROM_16K_Bank(4, addr & 0x07);
SetPROM_16K_Bank(6, addr & 0x07); SetPROM_16K_Bank(6, addr & 0x07);
} }
else else
{ {
SetPROM_32K_Bank((addr & 0x06) >> 1); SetPROM_32K_Bank((addr & 0x06) >> 1);
} }
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank((addr & 0x38) >> 3); SetVROM_8K_Bank((addr & 0x38) >> 3);
} }
if ((data & 0x02) != 0) SetVRAM_Mirror(VRAM_VMIRROR); if ((data & 0x02) != 0) SetVRAM_Mirror(VRAM_VMIRROR);
else SetVRAM_Mirror(VRAM_HMIRROR); else SetVRAM_Mirror(VRAM_HMIRROR);
} }
} }
} }

97
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper060.cs
View File

@ -2,65 +2,62 @@
// Mapper060 // // Mapper060 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper060 : Mapper public class Mapper060 : Mapper
{ {
BYTE patch; BYTE patch;
BYTE game_sel; BYTE game_sel;
public Mapper060(NES parent) : base(parent) public Mapper060(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
patch = 0; patch = 0;
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0xf9c484a0) if (crc == 0xf9c484a0)
{ // Reset Based 4-in-1(Unl) { // Reset Based 4-in-1(Unl)
SetPROM_16K_Bank(4, game_sel); SetPROM_16K_Bank(4, game_sel);
SetPROM_16K_Bank(6, game_sel); SetPROM_16K_Bank(6, game_sel);
SetVROM_8K_Bank(game_sel); SetVROM_8K_Bank(game_sel);
game_sel++; game_sel++;
game_sel &= 3; game_sel &= 3;
} }
else else
{ {
patch = 1; patch = 1;
SetPROM_32K_Bank(0); SetPROM_32K_Bank(0);
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper060::Write(WORD addr, BYTE data) //void Mapper060::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
if (patch != 0) if (patch != 0)
{ {
if ((addr & 0x80) != 0) if ((addr & 0x80) != 0)
{ {
SetPROM_16K_Bank(4, (addr & 0x70) >> 4); SetPROM_16K_Bank(4, (addr & 0x70) >> 4);
SetPROM_16K_Bank(6, (addr & 0x70) >> 4); SetPROM_16K_Bank(6, (addr & 0x70) >> 4);
} }
else else
{ {
SetPROM_32K_Bank((addr & 0x70) >> 5); SetPROM_32K_Bank((addr & 0x70) >> 5);
} }
SetVROM_8K_Bank(addr & 0x07); SetVROM_8K_Bank(addr & 0x07);
if ((data & 0x08) != 0) SetVRAM_Mirror(VRAM_VMIRROR); if ((data & 0x08) != 0) SetVRAM_Mirror(VRAM_VMIRROR);
else SetVRAM_Mirror(VRAM_HMIRROR); else SetVRAM_Mirror(VRAM_HMIRROR);
} }
} }
} }
} }

62
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper061.cs
View File

@ -2,46 +2,42 @@
// Mapper061 // // Mapper061 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper061 : Mapper public class Mapper061 : Mapper
{ {
public Mapper061(NES parent) : base(parent) public Mapper061(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
} }
//void Mapper061::Write(WORD addr, BYTE data) //void Mapper061::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0x30) switch (addr & 0x30)
{ {
case 0x00: case 0x00:
case 0x30: case 0x30:
SetPROM_32K_Bank(addr & 0x0F); SetPROM_32K_Bank(addr & 0x0F);
break; break;
case 0x10: case 0x10:
case 0x20: case 0x20:
SetPROM_16K_Bank(4, ((addr & 0x0F) << 1) | ((addr & 0x20) >> 4)); SetPROM_16K_Bank(4, ((addr & 0x0F) << 1) | ((addr & 0x20) >> 4));
SetPROM_16K_Bank(6, ((addr & 0x0F) << 1) | ((addr & 0x20) >> 4)); SetPROM_16K_Bank(6, ((addr & 0x0F) << 1) | ((addr & 0x20) >> 4));
break; break;
} }
if ((addr & 0x80) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((addr & 0x80) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
} }
} }
} }

78
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper062.cs
View File

@ -2,52 +2,48 @@
// Mapper062 // // Mapper062 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper062 : Mapper public class Mapper062 : Mapper
{ {
public Mapper062(NES parent) : base(parent) public Mapper062(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0); SetPROM_32K_Bank(0);
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
//void Mapper062::Write(WORD addr, BYTE data) //void Mapper062::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xFF00) switch (addr & 0xFF00)
{ {
case 0x8100: case 0x8100:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
SetPROM_8K_Bank(5, data + 1); SetPROM_8K_Bank(5, data + 1);
break; break;
case 0x8500: case 0x8500:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0x8700: case 0x8700:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
SetVROM_1K_Bank(0, data + 0); SetVROM_1K_Bank(0, data + 0);
SetVROM_1K_Bank(1, data + 1); SetVROM_1K_Bank(1, data + 1);
SetVROM_1K_Bank(2, data + 2); SetVROM_1K_Bank(2, data + 2);
SetVROM_1K_Bank(3, data + 3); SetVROM_1K_Bank(3, data + 3);
SetVROM_1K_Bank(4, data + 4); SetVROM_1K_Bank(4, data + 4);
SetVROM_1K_Bank(5, data + 5); SetVROM_1K_Bank(5, data + 5);
SetVROM_1K_Bank(6, data + 6); SetVROM_1K_Bank(6, data + 6);
SetVROM_1K_Bank(7, data + 7); SetVROM_1K_Bank(7, data + 7);
} }
} }
} }
} }

515
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper064.cs
View File

@ -1,283 +1,282 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper064 Tengen Rambo-1 // // Mapper064 Tengen Rambo-1 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using INT = System.Int32;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper064 : Mapper public class Mapper064 : Mapper
{ {
BYTE[] reg = new byte[3]; BYTE[] reg = new byte[3];
BYTE irq_enable; BYTE irq_enable;
BYTE irq_mode; BYTE irq_mode;
INT irq_counter; INT irq_counter;
INT irq_counter2; INT irq_counter2;
BYTE irq_latch; BYTE irq_latch;
BYTE irq_reset; BYTE irq_reset;
public Mapper064(NES parent) : base(parent) public Mapper064(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(PROM_8K_SIZE - 1, PROM_8K_SIZE - 1, PROM_8K_SIZE - 1, PROM_8K_SIZE - 1); SetPROM_32K_Bank(PROM_8K_SIZE - 1, PROM_8K_SIZE - 1, PROM_8K_SIZE - 1, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
reg[0] = reg[1] = reg[2] = 0; reg[0] = reg[1] = reg[2] = 0;
irq_enable = 0; irq_enable = 0;
irq_mode = 0; irq_mode = 0;
irq_counter = 0; irq_counter = 0;
irq_counter2 = 0; irq_counter2 = 0;
irq_latch = 0; irq_latch = 0;
irq_reset = 0; irq_reset = 0;
} }
//void Mapper064::Write(WORD addr, BYTE data) //void Mapper064::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
//DEBUGOUT( "$%04X:$%02X\n", addr, data ); //DEBUGOUT( "$%04X:$%02X\n", addr, data );
switch (addr & 0xF003) switch (addr & 0xF003)
{ {
case 0x8000: case 0x8000:
reg[0] = (byte)(data & 0x0F); reg[0] = (byte)(data & 0x0F);
reg[1] = (byte)(data & 0x40); reg[1] = (byte)(data & 0x40);
reg[2] = (byte)(data & 0x80); reg[2] = (byte)(data & 0x80);
break; break;
case 0x8001: case 0x8001:
switch (reg[0]) switch (reg[0])
{ {
case 0x00: case 0x00:
if (reg[2] != 0) if (reg[2] != 0)
{ {
SetVROM_1K_Bank(4, data + 0); SetVROM_1K_Bank(4, data + 0);
SetVROM_1K_Bank(5, data + 1); SetVROM_1K_Bank(5, data + 1);
} }
else else
{ {
SetVROM_1K_Bank(0, data + 0); SetVROM_1K_Bank(0, data + 0);
SetVROM_1K_Bank(1, data + 1); SetVROM_1K_Bank(1, data + 1);
} }
break; break;
case 0x01: case 0x01:
if (reg[2] != 0) if (reg[2] != 0)
{ {
SetVROM_1K_Bank(6, data + 0); SetVROM_1K_Bank(6, data + 0);
SetVROM_1K_Bank(7, data + 1); SetVROM_1K_Bank(7, data + 1);
} }
else else
{ {
SetVROM_1K_Bank(2, data + 0); SetVROM_1K_Bank(2, data + 0);
SetVROM_1K_Bank(3, data + 1); SetVROM_1K_Bank(3, data + 1);
} }
break; break;
case 0x02: case 0x02:
if (reg[2] != 0) if (reg[2] != 0)
{ {
SetVROM_1K_Bank(0, data); SetVROM_1K_Bank(0, data);
} }
else else
{ {
SetVROM_1K_Bank(4, data); SetVROM_1K_Bank(4, data);
} }
break; break;
case 0x03: case 0x03:
if (reg[2] != 0) if (reg[2] != 0)
{ {
SetVROM_1K_Bank(1, data); SetVROM_1K_Bank(1, data);
} }
else else
{ {
SetVROM_1K_Bank(5, data); SetVROM_1K_Bank(5, data);
} }
break; break;
case 0x04: case 0x04:
if (reg[2] != 0) if (reg[2] != 0)
{ {
SetVROM_1K_Bank(2, data); SetVROM_1K_Bank(2, data);
} }
else else
{ {
SetVROM_1K_Bank(6, data); SetVROM_1K_Bank(6, data);
} }
break; break;
case 0x05: case 0x05:
if (reg[2] != 0) if (reg[2] != 0)
{ {
SetVROM_1K_Bank(3, data); SetVROM_1K_Bank(3, data);
} }
else else
{ {
SetVROM_1K_Bank(7, data); SetVROM_1K_Bank(7, data);
} }
break; break;
case 0x06: case 0x06:
if (reg[1] != 0) if (reg[1] != 0)
{ {
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
} }
else else
{ {
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
} }
break; break;
case 0x07: case 0x07:
if (reg[1] != 0) if (reg[1] != 0)
{ {
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
} }
else else
{ {
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
} }
break; break;
case 0x08: case 0x08:
SetVROM_1K_Bank(1, data); SetVROM_1K_Bank(1, data);
break; break;
case 0x09: case 0x09:
SetVROM_1K_Bank(3, data); SetVROM_1K_Bank(3, data);
break; break;
case 0x0F: case 0x0F:
if (reg[1] != 0) if (reg[1] != 0)
{ {
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
} }
else else
{ {
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
} }
break; break;
} }
break; break;
case 0xA000: case 0xA000:
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
case 0xC000: case 0xC000:
irq_latch = data; irq_latch = data;
if (irq_reset != 0) if (irq_reset != 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
} }
break; break;
case 0xC001: case 0xC001:
irq_reset = 0xFF; irq_reset = 0xFF;
irq_counter = irq_latch; irq_counter = irq_latch;
irq_mode = (byte)(data & 0x01); irq_mode = (byte)(data & 0x01);
break; break;
case 0xE000: case 0xE000:
irq_enable = 0; irq_enable = 0;
if (irq_reset != 0) if (irq_reset != 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
} }
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xE001: case 0xE001:
irq_enable = 0xFF; irq_enable = 0xFF;
if (irq_reset != 0) if (irq_reset != 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
} }
break; break;
} }
} }
//void Mapper064::Clock(INT cycles) //void Mapper064::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
if (irq_mode == 0) if (irq_mode == 0)
return; return;
irq_counter2 += cycles; irq_counter2 += cycles;
while (irq_counter2 >= 4) while (irq_counter2 >= 4)
{ {
irq_counter2 -= 4; irq_counter2 -= 4;
if (irq_counter >= 0) if (irq_counter >= 0)
{ {
irq_counter--; irq_counter--;
if (irq_counter < 0) if (irq_counter < 0)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
} }
} }
//void Mapper064::HSync(INT scanline) //void Mapper064::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if (irq_mode != 0) if (irq_mode != 0)
return; return;
irq_reset = 0; irq_reset = 0;
if ((scanline >= 0 && scanline <= 239)) if ((scanline >= 0 && scanline <= 239))
{ {
if (nes.ppu.IsDispON()) if (nes.ppu.IsDispON())
{ {
if (irq_counter >= 0) if (irq_counter >= 0)
{ {
irq_counter--; irq_counter--;
if (irq_counter < 0) if (irq_counter < 0)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
irq_reset = 1; irq_reset = 1;
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
} }
} }
} }
//void Mapper064::SaveState(LPBYTE p) //void Mapper064::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = reg[0]; //p[0] = reg[0];
//p[1] = reg[1]; //p[1] = reg[1];
//p[2] = reg[2]; //p[2] = reg[2];
//p[3] = irq_enable; //p[3] = irq_enable;
//p[4] = irq_mode; //p[4] = irq_mode;
//p[5] = irq_latch; //p[5] = irq_latch;
//p[6] = irq_reset; //p[6] = irq_reset;
//*((INT*)&p[8]) = irq_counter; //*((INT*)&p[8]) = irq_counter;
//*((INT*)&p[12]) = irq_counter2; //*((INT*)&p[12]) = irq_counter2;
} }
//void Mapper064::LoadState(LPBYTE p) //void Mapper064::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//reg[0] = p[0]; //reg[0] = p[0];
//reg[1] = p[1]; //reg[1] = p[1];
//reg[2] = p[2]; //reg[2] = p[2];
//irq_enable = p[3]; //irq_enable = p[3];
//irq_mode = p[4]; //irq_mode = p[4];
//irq_latch = p[5]; //irq_latch = p[5];
//irq_reset = p[6]; //irq_reset = p[6];
//irq_counter = *((INT*)&p[8]); //irq_counter = *((INT*)&p[8]);
//irq_counter2 = *((INT*)&p[12]); //irq_counter2 = *((INT*)&p[12]);
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

321
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper065.cs
View File

@ -1,189 +1,188 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper065 Irem H3001 // // Mapper065 Irem H3001 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using INT = System.Int32;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper065 : Mapper public class Mapper065 : Mapper
{ {
BYTE patch; BYTE patch;
BYTE irq_enable; BYTE irq_enable;
INT irq_counter; INT irq_counter;
INT irq_latch; INT irq_latch;
public Mapper065(NES parent) : base(parent) public Mapper065(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
patch = 0; patch = 0;
// Kaiketsu Yanchamaru 3(J) // Kaiketsu Yanchamaru 3(J)
if (nes.rom.GetPROM_CRC() == 0xe30b7f64) if (nes.rom.GetPROM_CRC() == 0xe30b7f64)
{ {
patch = 1; patch = 1;
} }
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_8K_SIZE != 0) if (VROM_8K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
} }
//void Mapper065::Write(WORD addr, BYTE data) //void Mapper065::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0x9000: case 0x9000:
if (patch == 0) if (patch == 0)
{ {
if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_VMIRROR); if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_VMIRROR);
else SetVRAM_Mirror(VRAM_HMIRROR); else SetVRAM_Mirror(VRAM_HMIRROR);
} }
break; break;
case 0x9001: case 0x9001:
if (patch != 0) if (patch != 0)
{ {
if ((data & 0x80) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x80) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
} }
break; break;
case 0x9003: case 0x9003:
if (patch == 0) if (patch == 0)
{ {
irq_enable = (byte)(data & 0x8); irq_enable = (byte)(data & 0x8);
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
} }
break; break;
case 0x9004: case 0x9004:
if (patch == 0) if (patch == 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
} }
break; break;
case 0x9005: case 0x9005:
if (patch != 0) if (patch != 0)
{ {
irq_counter = (BYTE)(data << 1); irq_counter = (BYTE)(data << 1);
irq_enable = data; irq_enable = data;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
} }
else else
{ {
irq_latch = (irq_latch & 0x00FF) | ((INT)data << 8); irq_latch = (irq_latch & 0x00FF) | ((INT)data << 8);
} }
break; break;
case 0x9006: case 0x9006:
if (patch != 0) if (patch != 0)
{ {
irq_enable = 1; irq_enable = 1;
} }
else else
{ {
irq_latch = (irq_latch & 0xFF00) | data; irq_latch = (irq_latch & 0xFF00) | data;
} }
break; break;
case 0xB000: case 0xB000:
case 0xB001: case 0xB001:
case 0xB002: case 0xB002:
case 0xB003: case 0xB003:
case 0xB004: case 0xB004:
case 0xB005: case 0xB005:
case 0xB006: case 0xB006:
case 0xB007: case 0xB007:
SetVROM_1K_Bank((byte)(addr & 0x0007), data); SetVROM_1K_Bank((byte)(addr & 0x0007), data);
break; break;
case 0xA000: case 0xA000:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0xC000: case 0xC000:
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
break; break;
} }
} }
//void Mapper065::HSync(INT scanline) //void Mapper065::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if (patch != 0) if (patch != 0)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if (irq_counter == 0) if (irq_counter == 0)
{ {
// nes.cpu.IRQ_NotPending(); // nes.cpu.IRQ_NotPending();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
else else
{ {
irq_counter--; irq_counter--;
} }
} }
} }
} }
//void Mapper065::Clock(INT cycles) //void Mapper065::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
if (patch == 0) if (patch == 0)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if (irq_counter <= 0) if (irq_counter <= 0)
{ {
// nes.cpu.IRQ_NotPending(); // nes.cpu.IRQ_NotPending();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
else else
{ {
irq_counter -= cycles; irq_counter -= cycles;
} }
} }
} }
} }
//void Mapper065::SaveState(LPBYTE p) //void Mapper065::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = irq_enable; //p[0] = irq_enable;
//*(INT*)&p[1] = irq_counter; //*(INT*)&p[1] = irq_counter;
//*(INT*)&p[5] = irq_latch; //*(INT*)&p[5] = irq_latch;
} }
//void Mapper065::LoadState(LPBYTE p) //void Mapper065::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//irq_enable = p[0]; //irq_enable = p[0];
//irq_counter = *(INT*)&p[1]; //irq_counter = *(INT*)&p[1];
//irq_latch = *(INT*)&p[5]; //irq_latch = *(INT*)&p[5];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

64
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper066.cs
View File

@ -2,47 +2,43 @@
// Mapper066 Bandai 74161 // // Mapper066 Bandai 74161 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper066 : Mapper public class Mapper066 : Mapper
{ {
public Mapper066(NES parent) : base(parent) public Mapper066(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
// if( nes->rom->GetPROM_CRC() == 0xe30552db ) { // Paris-Dakar Rally Special // if( nes->rom->GetPROM_CRC() == 0xe30552db ) { // Paris-Dakar Rally Special
// nes->SetFrameIRQmode( FALSE ); // nes->SetFrameIRQmode( FALSE );
// } // }
} }
//void Mapper066::WriteLow(WORD addr, BYTE data) //void Mapper066::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if (addr >= 0x6000) if (addr >= 0x6000)
{ {
SetPROM_32K_Bank((data & 0xF0) >> 4); SetPROM_32K_Bank((data & 0xF0) >> 4);
SetVROM_8K_Bank(data & 0x0F); SetVROM_8K_Bank(data & 0x0F);
} }
} }
//void Mapper066::Write(WORD addr, BYTE data) //void Mapper066::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
SetPROM_32K_Bank((data & 0xF0) >> 4); SetPROM_32K_Bank((data & 0xF0) >> 4);
SetVROM_8K_Bank(data & 0x0F); SetVROM_8K_Bank(data & 0x0F);
} }
} }
} }

227
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper067.cs
View File

@ -1,140 +1,139 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper067 SunSoft Mapper 3 // // Mapper067 SunSoft Mapper 3 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using INT = System.Int32;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper067 : Mapper public class Mapper067 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
BYTE irq_occur; BYTE irq_occur;
BYTE irq_toggle; BYTE irq_toggle;
INT irq_counter; INT irq_counter;
public Mapper067(NES parent) : base(parent) public Mapper067(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
irq_enable = 0; irq_enable = 0;
irq_toggle = 0; irq_toggle = 0;
irq_counter = 0; irq_counter = 0;
irq_occur = 0; irq_occur = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
SetVROM_4K_Bank(0, 0); SetVROM_4K_Bank(0, 0);
SetVROM_4K_Bank(4, VROM_4K_SIZE - 1); SetVROM_4K_Bank(4, VROM_4K_SIZE - 1);
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0x7f2a04bf) if (crc == 0x7f2a04bf)
{ // For Fantasy Zone 2(J) { // For Fantasy Zone 2(J)
nes.SetRenderMethod(EnumRenderMethod.PRE_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.PRE_ALL_RENDER);
} }
} }
//void Mapper067::Write(WORD addr, BYTE data) //void Mapper067::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF800) switch (addr & 0xF800)
{ {
case 0x8800: case 0x8800:
SetVROM_2K_Bank(0, data); SetVROM_2K_Bank(0, data);
break; break;
case 0x9800: case 0x9800:
SetVROM_2K_Bank(2, data); SetVROM_2K_Bank(2, data);
break; break;
case 0xA800: case 0xA800:
SetVROM_2K_Bank(4, data); SetVROM_2K_Bank(4, data);
break; break;
case 0xB800: case 0xB800:
SetVROM_2K_Bank(6, data); SetVROM_2K_Bank(6, data);
break; break;
case 0xC800: case 0xC800:
if (irq_toggle == 0) if (irq_toggle == 0)
{ {
irq_counter = (irq_counter & 0x00FF) | ((INT)data << 8); irq_counter = (irq_counter & 0x00FF) | ((INT)data << 8);
} }
else else
{ {
irq_counter = (irq_counter & 0xFF00) | ((INT)data & 0xFF); irq_counter = (irq_counter & 0xFF00) | ((INT)data & 0xFF);
} }
irq_toggle ^= 1; irq_toggle ^= 1;
irq_occur = 0; irq_occur = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xD800: case 0xD800:
irq_enable = (byte)(data & 0x10); irq_enable = (byte)(data & 0x10);
irq_toggle = 0; irq_toggle = 0;
irq_occur = 0; irq_occur = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xE800: case 0xE800:
data &= 0x03; data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR); if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L); else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L);
else SetVRAM_Mirror(VRAM_MIRROR4H); else SetVRAM_Mirror(VRAM_MIRROR4H);
break; break;
case 0xF800: case 0xF800:
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
break; break;
} }
} }
//void Mapper067::Clock(INT cycles) //void Mapper067::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if ((irq_counter -= cycles) <= 0) if ((irq_counter -= cycles) <= 0)
{ {
irq_enable = 0; irq_enable = 0;
irq_occur = 0xFF; irq_occur = 0xFF;
irq_counter = 0xFFFF; irq_counter = 0xFFFF;
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
// if( irq_occur ) { // if( irq_occur ) {
// nes.cpu.IRQ_NotPending(); // nes.cpu.IRQ_NotPending();
// } // }
} }
//void Mapper067::SaveState(LPBYTE p) //void Mapper067::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = irq_enable; //p[0] = irq_enable;
//p[1] = irq_occur; //p[1] = irq_occur;
//p[2] = irq_toggle; //p[2] = irq_toggle;
//*((INT*)&p[3]) = irq_counter; //*((INT*)&p[3]) = irq_counter;
} }
//void Mapper067::LoadState(LPBYTE p) //void Mapper067::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//irq_enable = p[0]; //irq_enable = p[0];
//irq_occur = p[1]; //irq_occur = p[1];
//irq_toggle = p[2]; //irq_toggle = p[2];
//irq_counter = *((INT*)&p[3]); //irq_counter = *((INT*)&p[3]);
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

246
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper068.cs
View File

@ -2,29 +2,27 @@
// Mapper068 SunSoft Mapper 4 (After Burner II) // // Mapper068 SunSoft Mapper 4 (After Burner II) //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using INT = System.Int32;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper068 : Mapper public class Mapper068 : Mapper
{ {
BYTE[] reg = new byte[4]; BYTE[] reg = new byte[4];
BYTE coin; BYTE coin;
public Mapper068(NES parent) : base(parent) public Mapper068(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
reg[0] = reg[1] = reg[2] = reg[3] = 0; reg[0] = reg[1] = reg[2] = reg[3] = 0;
coin = 0; coin = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
} }
#if FALSE //0 #if FALSE //0
@ -47,118 +45,118 @@ DEBUGOUT( "WR $4020:%02X\n", data );
} }
#endif #endif
//void Mapper068::Write(WORD addr, BYTE data) //void Mapper068::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF000) switch (addr & 0xF000)
{ {
case 0x8000: case 0x8000:
SetVROM_2K_Bank(0, data); SetVROM_2K_Bank(0, data);
break; break;
case 0x9000: case 0x9000:
SetVROM_2K_Bank(2, data); SetVROM_2K_Bank(2, data);
break; break;
case 0xA000: case 0xA000:
SetVROM_2K_Bank(4, data); SetVROM_2K_Bank(4, data);
break; break;
case 0xB000: case 0xB000:
SetVROM_2K_Bank(6, data); SetVROM_2K_Bank(6, data);
break; break;
case 0xC000: case 0xC000:
reg[2] = data; reg[2] = data;
SetBank(); SetBank();
break; break;
case 0xD000: case 0xD000:
reg[3] = data; reg[3] = data;
SetBank(); SetBank();
break; break;
case 0xE000: case 0xE000:
reg[0] = (byte)((data & 0x10) >> 4); reg[0] = (byte)((data & 0x10) >> 4);
reg[1] = (byte)(data & 0x03); reg[1] = (byte)(data & 0x03);
SetBank(); SetBank();
break; break;
case 0xF000: case 0xF000:
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
break; break;
} }
} }
void SetBank() void SetBank()
{ {
if (reg[0] != 0) if (reg[0] != 0)
{ {
switch (reg[1]) switch (reg[1])
{ {
case 0: case 0:
SetVROM_1K_Bank(8, (INT)reg[2] + 0x80); SetVROM_1K_Bank(8, (INT)reg[2] + 0x80);
SetVROM_1K_Bank(9, (INT)reg[3] + 0x80); SetVROM_1K_Bank(9, (INT)reg[3] + 0x80);
SetVROM_1K_Bank(10, (INT)reg[2] + 0x80); SetVROM_1K_Bank(10, (INT)reg[2] + 0x80);
SetVROM_1K_Bank(11, (INT)reg[3] + 0x80); SetVROM_1K_Bank(11, (INT)reg[3] + 0x80);
break; break;
case 1: case 1:
SetVROM_1K_Bank(8, (INT)reg[2] + 0x80); SetVROM_1K_Bank(8, (INT)reg[2] + 0x80);
SetVROM_1K_Bank(9, (INT)reg[2] + 0x80); SetVROM_1K_Bank(9, (INT)reg[2] + 0x80);
SetVROM_1K_Bank(10, (INT)reg[3] + 0x80); SetVROM_1K_Bank(10, (INT)reg[3] + 0x80);
SetVROM_1K_Bank(11, (INT)reg[3] + 0x80); SetVROM_1K_Bank(11, (INT)reg[3] + 0x80);
break; break;
case 2: case 2:
SetVROM_1K_Bank(8, (INT)reg[2] + 0x80); SetVROM_1K_Bank(8, (INT)reg[2] + 0x80);
SetVROM_1K_Bank(9, (INT)reg[2] + 0x80); SetVROM_1K_Bank(9, (INT)reg[2] + 0x80);
SetVROM_1K_Bank(10, (INT)reg[2] + 0x80); SetVROM_1K_Bank(10, (INT)reg[2] + 0x80);
SetVROM_1K_Bank(11, (INT)reg[2] + 0x80); SetVROM_1K_Bank(11, (INT)reg[2] + 0x80);
break; break;
case 3: case 3:
SetVROM_1K_Bank(8, (INT)reg[3] + 0x80); SetVROM_1K_Bank(8, (INT)reg[3] + 0x80);
SetVROM_1K_Bank(9, (INT)reg[3] + 0x80); SetVROM_1K_Bank(9, (INT)reg[3] + 0x80);
SetVROM_1K_Bank(10, (INT)reg[3] + 0x80); SetVROM_1K_Bank(10, (INT)reg[3] + 0x80);
SetVROM_1K_Bank(11, (INT)reg[3] + 0x80); SetVROM_1K_Bank(11, (INT)reg[3] + 0x80);
break; break;
} }
} }
else else
{ {
switch (reg[1]) switch (reg[1])
{ {
case 0: case 0:
SetVRAM_Mirror(VRAM_VMIRROR); SetVRAM_Mirror(VRAM_VMIRROR);
break; break;
case 1: case 1:
SetVRAM_Mirror(VRAM_HMIRROR); SetVRAM_Mirror(VRAM_HMIRROR);
break; break;
case 2: case 2:
SetVRAM_Mirror(VRAM_MIRROR4L); SetVRAM_Mirror(VRAM_MIRROR4L);
break; break;
case 3: case 3:
SetVRAM_Mirror(VRAM_MIRROR4H); SetVRAM_Mirror(VRAM_MIRROR4H);
break; break;
} }
} }
} }
//void Mapper068::SaveState(LPBYTE p) //void Mapper068::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg[0]; p[0] = reg[0];
p[1] = reg[1]; p[1] = reg[1];
p[2] = reg[2]; p[2] = reg[2];
p[3] = reg[3]; p[3] = reg[3];
} }
//void Mapper068::LoadState(LPBYTE p) //void Mapper068::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg[0] = p[0]; reg[0] = p[0];
reg[1] = p[1]; reg[1] = p[1];
reg[2] = p[2]; reg[2] = p[2];
reg[3] = p[3]; reg[3] = p[3];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

295
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper069.cs
View File

@ -1,177 +1,176 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper069 SunSoft FME-7 // // Mapper069 SunSoft FME-7 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using INT = System.Int32;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper069 : Mapper public class Mapper069 : Mapper
{ {
BYTE patch; BYTE patch;
BYTE reg; BYTE reg;
BYTE irq_enable; BYTE irq_enable;
INT irq_counter; INT irq_counter;
public Mapper069(NES parent) : base(parent) public Mapper069(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
reg = 0; reg = 0;
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
nes.apu.SelectExSound(32); nes.apu.SelectExSound(32);
nes.SetIrqType(NES.IRQMETHOD.IRQ_CLOCK); nes.SetIrqType(NES.IRQMETHOD.IRQ_CLOCK);
patch = 0; patch = 0;
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0xfeac6916) if (crc == 0xfeac6916)
{ // Honoo no Toukyuuji - Dodge Danpei 2(J) { // Honoo no Toukyuuji - Dodge Danpei 2(J)
// nes.SetIrqType( NES::IRQ_HSYNC ); // nes.SetIrqType( NES::IRQ_HSYNC );
nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER); nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER);
} }
if (crc == 0xad28aef6) if (crc == 0xad28aef6)
{ // Dynamite Batman(J) / Dynamite Batman - Return of the Joker(U) { // Dynamite Batman(J) / Dynamite Batman - Return of the Joker(U)
patch = 1; patch = 1;
} }
} }
//void Mapper069::Write(WORD addr, BYTE data) //void Mapper069::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xE000) switch (addr & 0xE000)
{ {
case 0x8000: case 0x8000:
reg = data; reg = data;
break; break;
case 0xA000: case 0xA000:
switch (reg & 0x0F) switch (reg & 0x0F)
{ {
case 0x00: case 0x00:
case 0x01: case 0x01:
case 0x02: case 0x02:
case 0x03: case 0x03:
case 0x04: case 0x04:
case 0x05: case 0x05:
case 0x06: case 0x06:
case 0x07: case 0x07:
SetVROM_1K_Bank((byte)(reg & 0x07), data); SetVROM_1K_Bank((byte)(reg & 0x07), data);
break; break;
case 0x08: case 0x08:
if (patch == 0 && (data & 0x40) == 0) if (patch == 0 && (data & 0x40) == 0)
{ {
SetPROM_8K_Bank(3, data); SetPROM_8K_Bank(3, data);
} }
break; break;
case 0x09: case 0x09:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0x0A: case 0x0A:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0x0B: case 0x0B:
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
break; break;
case 0x0C: case 0x0C:
data &= 0x03; data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR); if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L); else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L);
else SetVRAM_Mirror(VRAM_MIRROR4H); else SetVRAM_Mirror(VRAM_MIRROR4H);
break; break;
case 0x0D: case 0x0D:
irq_enable = data; irq_enable = data;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0x0E: case 0x0E:
irq_counter = (irq_counter & 0xFF00) | data; irq_counter = (irq_counter & 0xFF00) | data;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0x0F: case 0x0F:
irq_counter = (irq_counter & 0x00FF) | (data << 8); irq_counter = (irq_counter & 0x00FF) | (data << 8);
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
} }
break; break;
case 0xC000: case 0xC000:
case 0xE000: case 0xE000:
nes.apu.ExWrite(addr, data); nes.apu.ExWrite(addr, data);
break; break;
} }
} }
//void Mapper069::Clock(INT cycles) //void Mapper069::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
//if (irq_enable && (nes.GetIrqType() == NES::IRQ_CLOCK)) //if (irq_enable && (nes.GetIrqType() == NES::IRQ_CLOCK))
if (irq_enable != 0 && (nes.GetIrqType() == (int)NES.IRQMETHOD.IRQ_HSYNC)) if (irq_enable != 0 && (nes.GetIrqType() == (int)NES.IRQMETHOD.IRQ_HSYNC))
{ {
irq_counter -= cycles; irq_counter -= cycles;
if (irq_counter <= 0) if (irq_counter <= 0)
{ {
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
irq_enable = 0; irq_enable = 0;
irq_counter = 0xFFFF; irq_counter = 0xFFFF;
} }
} }
} }
//void Mapper069::HSync(INT scanline) //void Mapper069::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if (irq_enable != 0 && (nes.GetIrqType() == (int)NES.IRQMETHOD.IRQ_HSYNC)) if (irq_enable != 0 && (nes.GetIrqType() == (int)NES.IRQMETHOD.IRQ_HSYNC))
{ {
irq_counter -= 114; irq_counter -= 114;
if (irq_counter <= 0) if (irq_counter <= 0)
{ {
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
irq_enable = 0; irq_enable = 0;
irq_counter = 0xFFFF; irq_counter = 0xFFFF;
} }
} }
} }
//void Mapper069::SaveState(LPBYTE p) //void Mapper069::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = reg; //p[0] = reg;
//p[1] = irq_enable; //p[1] = irq_enable;
//*(INT*)&p[2] = irq_counter; //*(INT*)&p[2] = irq_counter;
} }
//void Mapper069::LoadState(LPBYTE p) //void Mapper069::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//reg = p[0]; //reg = p[0];
//irq_enable = p[1]; //irq_enable = p[1];
//irq_counter = *(INT*)&p[2]; //irq_counter = *(INT*)&p[2];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

91
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper070.cs
View File

@ -2,63 +2,60 @@
// Mapper070 Bandai 74161 // // Mapper070 Bandai 74161 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper070 : Mapper public class Mapper070 : Mapper
{ {
BYTE patch; BYTE patch;
public Mapper070(NES parent) : base(parent) public Mapper070(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
patch = 0; patch = 0;
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0xa59ca2ef) if (crc == 0xa59ca2ef)
{ // Kamen Rider Club(J) { // Kamen Rider Club(J)
patch = 1; patch = 1;
nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER);
} }
if (crc == 0x10bb8f9a) if (crc == 0x10bb8f9a)
{ // Family Trainer - Manhattan Police(J) { // Family Trainer - Manhattan Police(J)
patch = 1; patch = 1;
} }
if (crc == 0x0cd00488) if (crc == 0x0cd00488)
{ // Space Shadow(J) { // Space Shadow(J)
patch = 1; patch = 1;
} }
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
//void Mapper070::Write(WORD addr, BYTE data) //void Mapper070::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
SetPROM_16K_Bank(4, (data & 0x70) >> 4); SetPROM_16K_Bank(4, (data & 0x70) >> 4);
SetVROM_8K_Bank(data & 0x0F); SetVROM_8K_Bank(data & 0x0F);
if (patch != 0) if (patch != 0)
{ {
if ((data & 0x80) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x80) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
} }
else else
{ {
if ((data & 0x80) != 0) SetVRAM_Mirror(VRAM_MIRROR4H); if ((data & 0x80) != 0) SetVRAM_Mirror(VRAM_MIRROR4H);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
} }
} }
} }
} }

76
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper071.cs
View File

@ -2,53 +2,49 @@
// Mapper071 Camerica // // Mapper071 Camerica //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper071 : Mapper public class Mapper071 : Mapper
{ {
public Mapper071(NES parent) : base(parent) public Mapper071(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
} }
//void Mapper071::WriteLow(WORD addr, BYTE data) //void Mapper071::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if ((addr & 0xE000) == 0x6000) if ((addr & 0xE000) == 0x6000)
{ {
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
} }
} }
//void Mapper071::Write(WORD addr, BYTE data) //void Mapper071::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF000) switch (addr & 0xF000)
{ {
case 0x9000: case 0x9000:
if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_MIRROR4H); if ((data & 0x10) != 0) SetVRAM_Mirror(VRAM_MIRROR4H);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
break; break;
case 0xC000: case 0xC000:
case 0xD000: case 0xD000:
case 0xE000: case 0xE000:
case 0xF000: case 0xF000:
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
break; break;
} }
} }
} }
} }

7
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper072.cs
View File

@ -1,13 +1,8 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper072 Jaleco/Type1 lower bank switch // // Mapper072 Jaleco/Type1 lower bank switch //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
using VirtualNes.Core.Debug; using VirtualNes.Core.Debug;
using static VirtualNes.MMU;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

151
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper073.cs
View File

@ -1,94 +1,93 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper073 Konami VRC3 // // Mapper073 Konami VRC3 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using INT = System.Int32;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper073 : Mapper public class Mapper073 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
INT irq_counter; INT irq_counter;
public Mapper073(NES parent) : base(parent) public Mapper073(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
} }
//void Mapper073::Write(WORD addr, BYTE data) //void Mapper073::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0xF000: case 0xF000:
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
break; break;
case 0x8000: case 0x8000:
irq_counter = (irq_counter & 0xFFF0) | (data & 0x0F); irq_counter = (irq_counter & 0xFFF0) | (data & 0x0F);
break; break;
case 0x9000: case 0x9000:
irq_counter = (irq_counter & 0xFF0F) | ((data & 0x0F) << 4); irq_counter = (irq_counter & 0xFF0F) | ((data & 0x0F) << 4);
break; break;
case 0xA000: case 0xA000:
irq_counter = (irq_counter & 0xF0FF) | ((data & 0x0F) << 8); irq_counter = (irq_counter & 0xF0FF) | ((data & 0x0F) << 8);
break; break;
case 0xB000: case 0xB000:
irq_counter = (irq_counter & 0x0FFF) | ((data & 0x0F) << 12); irq_counter = (irq_counter & 0x0FFF) | ((data & 0x0F) << 12);
break; break;
case 0xC000: case 0xC000:
irq_enable = (byte)(data & 0x02); irq_enable = (byte)(data & 0x02);
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xD000: case 0xD000:
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
} }
} }
//void Mapper073::Clock(INT cycles) //void Mapper073::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if ((irq_counter += cycles) >= 0xFFFF) if ((irq_counter += cycles) >= 0xFFFF)
{ {
irq_enable = 0; irq_enable = 0;
irq_counter &= 0xFFFF; irq_counter &= 0xFFFF;
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
//void Mapper073::SaveState(LPBYTE p) //void Mapper073::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = irq_enable; //p[0] = irq_enable;
//*(INT*)&p[1] = irq_counter; //*(INT*)&p[1] = irq_counter;
} }
//void Mapper073::LoadState(LPBYTE p) //void Mapper073::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//irq_enable = p[0]; //irq_enable = p[0];
//irq_counter = *(INT*)&p[1]; //irq_counter = *(INT*)&p[1];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

569
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper074.cs
View File

@ -1,312 +1,311 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper074 // // Mapper074 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using INT = System.Int32;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper074 : Mapper public class Mapper074 : Mapper
{ {
BYTE[] reg = new byte[8]; BYTE[] reg = new byte[8];
BYTE prg0, prg1; BYTE prg0, prg1;
BYTE chr01, chr23, chr4, chr5, chr6, chr7; BYTE chr01, chr23, chr4, chr5, chr6, chr7;
BYTE we_sram; BYTE we_sram;
BYTE irq_type; BYTE irq_type;
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
BYTE irq_request; BYTE irq_request;
BYTE patch; BYTE patch;
public Mapper074(NES parent) : base(parent) public Mapper074(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
reg[i] = 0x00; reg[i] = 0x00;
} }
prg0 = 0; prg0 = 0;
prg1 = 1; prg1 = 1;
SetBank_CPU(); SetBank_CPU();
chr01 = 0; chr01 = 0;
chr23 = 2; chr23 = 2;
chr4 = 4; chr4 = 4;
chr5 = 5; chr5 = 5;
chr6 = 6; chr6 = 6;
chr7 = 7; chr7 = 7;
SetBank_PPU(); SetBank_PPU();
we_sram = 0; // Disable we_sram = 0; // Disable
irq_enable = 0; // Disable irq_enable = 0; // Disable
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
irq_request = 0; irq_request = 0;
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
patch = 0; patch = 0;
if (crc == 0x37ae04a8) if (crc == 0x37ae04a8)
{ {
patch = 1; patch = 1;
nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER); nes.SetRenderMethod(EnumRenderMethod.TILE_RENDER);
} }
} }
//void Mapper074::Write(WORD addr, BYTE data) //void Mapper074::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() ); //DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() );
switch (addr & 0xE001) switch (addr & 0xE001)
{ {
case 0x8000: case 0x8000:
reg[0] = data; reg[0] = data;
SetBank_CPU(); SetBank_CPU();
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x8001: case 0x8001:
reg[1] = data; reg[1] = data;
switch (reg[0] & 0x07) switch (reg[0] & 0x07)
{ {
case 0x00: case 0x00:
chr01 = (byte)(data & 0xFE); chr01 = (byte)(data & 0xFE);
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x01: case 0x01:
chr23 = (byte)(data & 0xFE); chr23 = (byte)(data & 0xFE);
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x02: case 0x02:
chr4 = data; chr4 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x03: case 0x03:
chr5 = data; chr5 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x04: case 0x04:
chr6 = data; chr6 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x05: case 0x05:
chr7 = data; chr7 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x06: case 0x06:
prg0 = data; prg0 = data;
SetBank_CPU(); SetBank_CPU();
break; break;
case 0x07: case 0x07:
prg1 = data; prg1 = data;
SetBank_CPU(); SetBank_CPU();
break; break;
} }
break; break;
case 0xA000: case 0xA000:
reg[2] = data; reg[2] = data;
if (!nes.rom.Is4SCREEN()) if (!nes.rom.Is4SCREEN())
{ {
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
} }
break; break;
case 0xA001: case 0xA001:
reg[3] = data; reg[3] = data;
break; break;
case 0xC000: case 0xC000:
reg[4] = data; reg[4] = data;
irq_counter = data; irq_counter = data;
irq_request = 0; irq_request = 0;
break; break;
case 0xC001: case 0xC001:
reg[5] = data; reg[5] = data;
irq_latch = data; irq_latch = data;
irq_request = 0; irq_request = 0;
break; break;
case 0xE000: case 0xE000:
reg[6] = data; reg[6] = data;
irq_enable = 0; irq_enable = 0;
irq_request = 0; irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xE001: case 0xE001:
reg[7] = data; reg[7] = data;
irq_enable = 1; irq_enable = 1;
irq_request = 0; irq_request = 0;
break; break;
} }
} }
//void Mapper074::HSync(INT scanline) //void Mapper074::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if ((scanline >= 0 && scanline <= 239)) if ((scanline >= 0 && scanline <= 239))
{ {
if (nes.ppu.IsDispON()) if (nes.ppu.IsDispON())
{ {
if (irq_enable != 0 && irq_request == 0) if (irq_enable != 0 && irq_request == 0)
{ {
if (scanline == 0) if (scanline == 0)
{ {
if (irq_counter != 0) if (irq_counter != 0)
{ {
irq_counter--; irq_counter--;
} }
} }
if ((irq_counter--) == 0) if ((irq_counter--) == 0)
{ {
irq_request = 0xFF; irq_request = 0xFF;
irq_counter = irq_latch; irq_counter = irq_latch;
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
} }
} }
void SetBank_CPU() void SetBank_CPU()
{ {
if ((reg[0] & 0x40) != 0) if ((reg[0] & 0x40) != 0)
{ {
SetPROM_32K_Bank(PROM_8K_SIZE - 2, prg1, prg0, PROM_8K_SIZE - 1); SetPROM_32K_Bank(PROM_8K_SIZE - 2, prg1, prg0, PROM_8K_SIZE - 1);
} }
else else
{ {
SetPROM_32K_Bank(prg0, prg1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(prg0, prg1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
} }
} }
void SetBank_PPU() void SetBank_PPU()
{ {
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
if ((reg[0] & 0x80) != 0) if ((reg[0] & 0x80) != 0)
{ {
// SetVROM_8K_Bank( chr4, chr5, chr6, chr7, // SetVROM_8K_Bank( chr4, chr5, chr6, chr7,
// chr01, chr01+1, chr23, chr23+1 ); // chr01, chr01+1, chr23, chr23+1 );
SetBank_PPUSUB(4, chr01 + 0); SetBank_PPUSUB(4, chr01 + 0);
SetBank_PPUSUB(5, chr01 + 1); SetBank_PPUSUB(5, chr01 + 1);
SetBank_PPUSUB(6, chr23 + 0); SetBank_PPUSUB(6, chr23 + 0);
SetBank_PPUSUB(7, chr23 + 1); SetBank_PPUSUB(7, chr23 + 1);
SetBank_PPUSUB(0, chr4); SetBank_PPUSUB(0, chr4);
SetBank_PPUSUB(1, chr5); SetBank_PPUSUB(1, chr5);
SetBank_PPUSUB(2, chr6); SetBank_PPUSUB(2, chr6);
SetBank_PPUSUB(3, chr7); SetBank_PPUSUB(3, chr7);
} }
else else
{ {
// SetVROM_8K_Bank( chr01, chr01+1, chr23, chr23+1, // SetVROM_8K_Bank( chr01, chr01+1, chr23, chr23+1,
// chr4, chr5, chr6, chr7 ); // chr4, chr5, chr6, chr7 );
SetBank_PPUSUB(0, chr01 + 0); SetBank_PPUSUB(0, chr01 + 0);
SetBank_PPUSUB(1, chr01 + 1); SetBank_PPUSUB(1, chr01 + 1);
SetBank_PPUSUB(2, chr23 + 0); SetBank_PPUSUB(2, chr23 + 0);
SetBank_PPUSUB(3, chr23 + 1); SetBank_PPUSUB(3, chr23 + 1);
SetBank_PPUSUB(4, chr4); SetBank_PPUSUB(4, chr4);
SetBank_PPUSUB(5, chr5); SetBank_PPUSUB(5, chr5);
SetBank_PPUSUB(6, chr6); SetBank_PPUSUB(6, chr6);
SetBank_PPUSUB(7, chr7); SetBank_PPUSUB(7, chr7);
} }
} }
else else
{ {
if ((reg[0] & 0x80) != 0) if ((reg[0] & 0x80) != 0)
{ {
SetCRAM_1K_Bank(4, (chr01 + 0) & 0x07); SetCRAM_1K_Bank(4, (chr01 + 0) & 0x07);
SetCRAM_1K_Bank(5, (chr01 + 1) & 0x07); SetCRAM_1K_Bank(5, (chr01 + 1) & 0x07);
SetCRAM_1K_Bank(6, (chr23 + 0) & 0x07); SetCRAM_1K_Bank(6, (chr23 + 0) & 0x07);
SetCRAM_1K_Bank(7, (chr23 + 1) & 0x07); SetCRAM_1K_Bank(7, (chr23 + 1) & 0x07);
SetCRAM_1K_Bank(0, chr4 & 0x07); SetCRAM_1K_Bank(0, chr4 & 0x07);
SetCRAM_1K_Bank(1, chr5 & 0x07); SetCRAM_1K_Bank(1, chr5 & 0x07);
SetCRAM_1K_Bank(2, chr6 & 0x07); SetCRAM_1K_Bank(2, chr6 & 0x07);
SetCRAM_1K_Bank(3, chr7 & 0x07); SetCRAM_1K_Bank(3, chr7 & 0x07);
} }
else else
{ {
SetCRAM_1K_Bank(0, (chr01 + 0) & 0x07); SetCRAM_1K_Bank(0, (chr01 + 0) & 0x07);
SetCRAM_1K_Bank(1, (chr01 + 1) & 0x07); SetCRAM_1K_Bank(1, (chr01 + 1) & 0x07);
SetCRAM_1K_Bank(2, (chr23 + 0) & 0x07); SetCRAM_1K_Bank(2, (chr23 + 0) & 0x07);
SetCRAM_1K_Bank(3, (chr23 + 1) & 0x07); SetCRAM_1K_Bank(3, (chr23 + 1) & 0x07);
SetCRAM_1K_Bank(4, chr4 & 0x07); SetCRAM_1K_Bank(4, chr4 & 0x07);
SetCRAM_1K_Bank(5, chr5 & 0x07); SetCRAM_1K_Bank(5, chr5 & 0x07);
SetCRAM_1K_Bank(6, chr6 & 0x07); SetCRAM_1K_Bank(6, chr6 & 0x07);
SetCRAM_1K_Bank(7, chr7 & 0x07); SetCRAM_1K_Bank(7, chr7 & 0x07);
} }
} }
} }
void SetBank_PPUSUB(int bank, int page) void SetBank_PPUSUB(int bank, int page)
{ {
if (patch == 0 && (page == 8 || page == 9)) if (patch == 0 && (page == 8 || page == 9))
{ {
SetCRAM_1K_Bank((byte)bank, page & 7); SetCRAM_1K_Bank((byte)bank, page & 7);
} }
else if (patch == 1 && page >= 128) else if (patch == 1 && page >= 128)
{ {
SetCRAM_1K_Bank((byte)bank, page & 7); SetCRAM_1K_Bank((byte)bank, page & 7);
} }
else else
{ {
SetVROM_1K_Bank((byte)bank, page); SetVROM_1K_Bank((byte)bank, page);
} }
} }
//void Mapper074::SaveState(LPBYTE p) //void Mapper074::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
p[i] = reg[i]; p[i] = reg[i];
} }
p[8] = prg0; p[8] = prg0;
p[9] = prg1; p[9] = prg1;
p[10] = chr01; p[10] = chr01;
p[11] = chr23; p[11] = chr23;
p[12] = chr4; p[12] = chr4;
p[13] = chr5; p[13] = chr5;
p[14] = chr6; p[14] = chr6;
p[15] = chr7; p[15] = chr7;
p[16] = irq_enable; p[16] = irq_enable;
p[17] = irq_counter; p[17] = irq_counter;
p[18] = irq_latch; p[18] = irq_latch;
p[19] = irq_request; p[19] = irq_request;
} }
//void Mapper074::LoadState(LPBYTE p) //void Mapper074::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
for (INT i = 0; i < 8; i++) for (INT i = 0; i < 8; i++)
{ {
reg[i] = p[i]; reg[i] = p[i];
} }
prg0 = p[8]; prg0 = p[8];
prg1 = p[9]; prg1 = p[9];
chr01 = p[10]; chr01 = p[10];
chr23 = p[11]; chr23 = p[11];
chr4 = p[12]; chr4 = p[12];
chr5 = p[13]; chr5 = p[13];
chr6 = p[14]; chr6 = p[14];
chr7 = p[15]; chr7 = p[15];
irq_enable = p[16]; irq_enable = p[16];
irq_counter = p[17]; irq_counter = p[17];
irq_latch = p[18]; irq_latch = p[18];
irq_request = p[19]; irq_request = p[19];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

135
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper075.cs
View File

@ -2,89 +2,86 @@
// Mapper075 Konami VRC1/Jaleco D65005 // // Mapper075 Konami VRC1/Jaleco D65005 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper075 : Mapper public class Mapper075 : Mapper
{ {
BYTE[] reg = new byte[2]; BYTE[] reg = new byte[2];
public Mapper075(NES parent) : base(parent) public Mapper075(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_8K_SIZE != 0) if (VROM_8K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
reg[0] = 0; reg[0] = 0;
reg[1] = 1; reg[1] = 1;
} }
//void Mapper075::Write(WORD addr, BYTE data) //void Mapper075::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF000) switch (addr & 0xF000)
{ {
case 0x8000: case 0x8000:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0x9000: case 0x9000:
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
reg[0] = (byte)((reg[0] & 0x0F) | ((data & 0x02) << 3)); reg[0] = (byte)((reg[0] & 0x0F) | ((data & 0x02) << 3));
reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x04) << 2)); reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x04) << 2));
SetVROM_4K_Bank(0, reg[0]); SetVROM_4K_Bank(0, reg[0]);
SetVROM_4K_Bank(4, reg[1]); SetVROM_4K_Bank(4, reg[1]);
break; break;
case 0xA000: case 0xA000:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0xC000: case 0xC000:
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
break; break;
case 0xE000: case 0xE000:
reg[0] = (byte)((reg[0] & 0x10) | (data & 0x0F)); reg[0] = (byte)((reg[0] & 0x10) | (data & 0x0F));
SetVROM_4K_Bank(0, reg[0]); SetVROM_4K_Bank(0, reg[0]);
break; break;
case 0xF000: case 0xF000:
reg[1] = (byte)((reg[1] & 0x10) | (data & 0x0F)); reg[1] = (byte)((reg[1] & 0x10) | (data & 0x0F));
SetVROM_4K_Bank(4, reg[1]); SetVROM_4K_Bank(4, reg[1]);
break; break;
} }
} }
//void Mapper075::SaveState(LPBYTE p) //void Mapper075::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg[0]; p[0] = reg[0];
p[1] = reg[1]; p[1] = reg[1];
} }
//void Mapper075::LoadState(LPBYTE p) //void Mapper075::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg[0] = p[0]; reg[0] = p[0];
reg[1] = p[1]; reg[1] = p[1];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

129
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper076.cs
View File

@ -2,81 +2,78 @@
// Mapper076 Namcot 109 (女神転生) // // Mapper076 Namcot 109 (女神転生) //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper076 : Mapper public class Mapper076 : Mapper
{ {
BYTE reg; BYTE reg;
public Mapper076(NES parent) : base(parent) public Mapper076(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE >= 8) if (VROM_1K_SIZE >= 8)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper076::Write(WORD addr, BYTE data) //void Mapper076::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
reg = data; reg = data;
break; break;
case 0x8001: case 0x8001:
switch (reg & 0x07) switch (reg & 0x07)
{ {
case 2: case 2:
SetVROM_2K_Bank(0, data); SetVROM_2K_Bank(0, data);
break; break;
case 3: case 3:
SetVROM_2K_Bank(2, data); SetVROM_2K_Bank(2, data);
break; break;
case 4: case 4:
SetVROM_2K_Bank(4, data); SetVROM_2K_Bank(4, data);
break; break;
case 5: case 5:
SetVROM_2K_Bank(6, data); SetVROM_2K_Bank(6, data);
break; break;
case 6: case 6:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 7: case 7:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
} }
break; break;
} }
} }
//void Mapper076::SaveState(LPBYTE p) //void Mapper076::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg; p[0] = reg;
} }
//void Mapper076::LoadState(LPBYTE p) //void Mapper076::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg = p[0]; reg = p[0];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

46
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper077.cs
View File

@ -2,38 +2,34 @@
// Mapper077 Irem Early Mapper #0 // // Mapper077 Irem Early Mapper #0 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper077 : Mapper public class Mapper077 : Mapper
{ {
public Mapper077(NES parent) : base(parent) public Mapper077(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0); SetPROM_32K_Bank(0);
SetVROM_2K_Bank(0, 0); SetVROM_2K_Bank(0, 0);
SetCRAM_2K_Bank(2, 1); SetCRAM_2K_Bank(2, 1);
SetCRAM_2K_Bank(4, 2); SetCRAM_2K_Bank(4, 2);
SetCRAM_2K_Bank(6, 3); SetCRAM_2K_Bank(6, 3);
} }
//void Mapper077::Write(WORD addr, BYTE data) //void Mapper077::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
SetPROM_32K_Bank(data & 0x07); SetPROM_32K_Bank(data & 0x07);
SetVROM_2K_Bank(0, (data & 0xF0) >> 4); SetVROM_2K_Bank(0, (data & 0xF0) >> 4);
} }
} }
} }

58
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper078.cs
View File

@ -2,44 +2,40 @@
// Mapper078 Jaleco(Cosmo Carrier) // // Mapper078 Jaleco(Cosmo Carrier) //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper078 : Mapper public class Mapper078 : Mapper
{ {
public Mapper078(NES parent) : base(parent) public Mapper078(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_8K_SIZE != 0) if (VROM_8K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper078::Write(WORD addr, BYTE data) //void Mapper078::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
//DEBUGOUT( "MAP78 WR $%04X=$%02X L=%d\n", addr, data, nes->GetScanline() ); //DEBUGOUT( "MAP78 WR $%04X=$%02X L=%d\n", addr, data, nes->GetScanline() );
SetPROM_16K_Bank(4, data & 0x0F); SetPROM_16K_Bank(4, data & 0x0F);
SetVROM_8K_Bank((data & 0xF0) >> 4); SetVROM_8K_Bank((data & 0xF0) >> 4);
if ((addr & 0xFE00) != 0xFE00) if ((addr & 0xFE00) != 0xFE00)
{ {
if ((data & 0x08) != 0) SetVRAM_Mirror(VRAM_MIRROR4H); if ((data & 0x08) != 0) SetVRAM_Mirror(VRAM_MIRROR4H);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
} }
} }
} }
} }

52
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper079.cs
View File

@ -2,40 +2,36 @@
// Mapper079 Nina-3 // // Mapper079 Nina-3 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper079 : Mapper public class Mapper079 : Mapper
{ {
public Mapper079(NES parent) : base(parent) public Mapper079(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0); SetPROM_32K_Bank(0);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper079::WriteLow(WORD addr, BYTE data) //void Mapper079::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if ((addr & 0x0100) != 0) if ((addr & 0x0100) != 0)
{ {
SetPROM_32K_Bank((data >> 3) & 0x01); SetPROM_32K_Bank((data >> 3) & 0x01);
SetVROM_8K_Bank(data & 0x07); SetVROM_8K_Bank(data & 0x07);
} }
} }
} }
} }

174
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper080.cs
View File

@ -2,105 +2,101 @@
// Mapper080 Taito X1-005 // // Mapper080 Taito X1-005 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper080 : Mapper public class Mapper080 : Mapper
{ {
public Mapper080(NES parent) : base(parent) public Mapper080(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_8K_SIZE != 0) if (VROM_8K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper080::WriteLow(WORD addr, BYTE data) //void Mapper080::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x7EF0: case 0x7EF0:
SetVROM_2K_Bank(0, (data >> 1) & 0x3F); SetVROM_2K_Bank(0, (data >> 1) & 0x3F);
if (PROM_8K_SIZE == 32) if (PROM_8K_SIZE == 32)
{ {
if ((data & 0x80) != 0) if ((data & 0x80) != 0)
{ {
SetVRAM_1K_Bank(8, 1); SetVRAM_1K_Bank(8, 1);
SetVRAM_1K_Bank(9, 1); SetVRAM_1K_Bank(9, 1);
} }
else else
{ {
SetVRAM_1K_Bank(8, 0); SetVRAM_1K_Bank(8, 0);
SetVRAM_1K_Bank(9, 0); SetVRAM_1K_Bank(9, 0);
} }
} }
break; break;
case 0x7EF1: case 0x7EF1:
SetVROM_2K_Bank(2, (data >> 1) & 0x3F); SetVROM_2K_Bank(2, (data >> 1) & 0x3F);
if (PROM_8K_SIZE == 32) if (PROM_8K_SIZE == 32)
{ {
if ((data & 0x80) != 0) if ((data & 0x80) != 0)
{ {
SetVRAM_1K_Bank(10, 1); SetVRAM_1K_Bank(10, 1);
SetVRAM_1K_Bank(11, 1); SetVRAM_1K_Bank(11, 1);
} }
else else
{ {
SetVRAM_1K_Bank(10, 0); SetVRAM_1K_Bank(10, 0);
SetVRAM_1K_Bank(11, 0); SetVRAM_1K_Bank(11, 0);
} }
} }
break; break;
case 0x7EF2: case 0x7EF2:
SetVROM_1K_Bank(4, data); SetVROM_1K_Bank(4, data);
break; break;
case 0x7EF3: case 0x7EF3:
SetVROM_1K_Bank(5, data); SetVROM_1K_Bank(5, data);
break; break;
case 0x7EF4: case 0x7EF4:
SetVROM_1K_Bank(6, data); SetVROM_1K_Bank(6, data);
break; break;
case 0x7EF5: case 0x7EF5:
SetVROM_1K_Bank(7, data); SetVROM_1K_Bank(7, data);
break; break;
case 0x7EF6: case 0x7EF6:
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_VMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_VMIRROR);
else SetVRAM_Mirror(VRAM_HMIRROR); else SetVRAM_Mirror(VRAM_HMIRROR);
break; break;
case 0x7EFA: case 0x7EFA:
case 0x7EFB: case 0x7EFB:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0x7EFC: case 0x7EFC:
case 0x7EFD: case 0x7EFD:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0x7EFE: case 0x7EFE:
case 0x7EFF: case 0x7EFF:
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
break; break;
default: default:
base.WriteLow(addr, data); base.WriteLow(addr, data);
break; break;
} }
} }
} }
} }

179
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper082.cs
View File

@ -2,118 +2,115 @@
// Mapper082 Taito C075 // // Mapper082 Taito C075 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper082 : Mapper public class Mapper082 : Mapper
{ {
BYTE reg; BYTE reg;
public Mapper082(NES parent) : base(parent) public Mapper082(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
reg = 0; reg = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_8K_SIZE!=0) if (VROM_8K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
SetVRAM_Mirror(VRAM_VMIRROR); SetVRAM_Mirror(VRAM_VMIRROR);
} }
//void Mapper082::WriteLow(WORD addr, BYTE data) //void Mapper082::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x7EF0: case 0x7EF0:
if (reg!=0) if (reg != 0)
{ {
SetVROM_2K_Bank(4, data >> 1); SetVROM_2K_Bank(4, data >> 1);
} }
else else
{ {
SetVROM_2K_Bank(0, data >> 1); SetVROM_2K_Bank(0, data >> 1);
} }
break; break;
case 0x7EF1: case 0x7EF1:
if (reg!=0) if (reg != 0)
{ {
SetVROM_2K_Bank(6, data >> 1); SetVROM_2K_Bank(6, data >> 1);
} }
else else
{ {
SetVROM_2K_Bank(2, data >> 1); SetVROM_2K_Bank(2, data >> 1);
} }
break; break;
case 0x7EF2: case 0x7EF2:
if (reg!=0) SetVROM_1K_Bank(0, data); if (reg != 0) SetVROM_1K_Bank(0, data);
else SetVROM_1K_Bank(4, data); else SetVROM_1K_Bank(4, data);
break; break;
case 0x7EF3: case 0x7EF3:
if (reg!=0) SetVROM_1K_Bank(1, data); if (reg != 0) SetVROM_1K_Bank(1, data);
else SetVROM_1K_Bank(5, data); else SetVROM_1K_Bank(5, data);
break; break;
case 0x7EF4: case 0x7EF4:
if (reg!=0) SetVROM_1K_Bank(2, data); if (reg != 0) SetVROM_1K_Bank(2, data);
else SetVROM_1K_Bank(6, data); else SetVROM_1K_Bank(6, data);
break; break;
case 0x7EF5: case 0x7EF5:
if (reg!=0) SetVROM_1K_Bank(3, data); if (reg != 0) SetVROM_1K_Bank(3, data);
else SetVROM_1K_Bank(7, data); else SetVROM_1K_Bank(7, data);
break; break;
case 0x7EF6: case 0x7EF6:
reg = (byte)(data & 0x02); reg = (byte)(data & 0x02);
if ((data & 0x01)!=0) SetVRAM_Mirror(VRAM_VMIRROR); if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_VMIRROR);
else SetVRAM_Mirror(VRAM_HMIRROR); else SetVRAM_Mirror(VRAM_HMIRROR);
break; break;
case 0x7EFA: case 0x7EFA:
SetPROM_8K_Bank(4, data >> 2); SetPROM_8K_Bank(4, data >> 2);
break; break;
case 0x7EFB: case 0x7EFB:
SetPROM_8K_Bank(5, data >> 2); SetPROM_8K_Bank(5, data >> 2);
break; break;
case 0x7EFC: case 0x7EFC:
SetPROM_8K_Bank(6, data >> 2); SetPROM_8K_Bank(6, data >> 2);
break; break;
default: default:
base.WriteLow(addr, data); base.WriteLow(addr, data);
break; break;
} }
} }
//void Mapper082::SaveState(LPBYTE p) //void Mapper082::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg; p[0] = reg;
} }
//void Mapper082::LoadState(LPBYTE p) //void Mapper082::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg = p[0]; reg = p[0];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

425
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper083.cs
View File

@ -1,243 +1,242 @@
///////////////////////////// /////////////////////////////
// Mapper083 Cony // // Mapper083 Cony //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using INT = System.Int32;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper083 : Mapper public class Mapper083 : Mapper
{ {
BYTE[] reg = new byte[3]; BYTE[] reg = new byte[3];
INT chr_bank; INT chr_bank;
BYTE irq_enable; BYTE irq_enable;
INT irq_counter; INT irq_counter;
BYTE patch; BYTE patch;
public Mapper083(NES parent) : base(parent) public Mapper083(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
for (INT i = 0; i < 3; i++) for (INT i = 0; i < 3; i++)
{ {
reg[i] = 0x00; reg[i] = 0x00;
} }
if (PROM_8K_SIZE >= 32) if (PROM_8K_SIZE >= 32)
{ {
SetPROM_32K_Bank(0, 1, 30, 31); SetPROM_32K_Bank(0, 1, 30, 31);
reg[1] = 0x30; reg[1] = 0x30;
} }
else else
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
} }
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
chr_bank = 0; chr_bank = 0;
irq_enable = 0; // Disable irq_enable = 0; // Disable
irq_counter = 0; irq_counter = 0;
patch = 0; patch = 0;
if (nes.rom.GetPROM_CRC() == 0x1461D1F8) if (nes.rom.GetPROM_CRC() == 0x1461D1F8)
{ {
patch = 1; patch = 1;
} }
} }
//BYTE Mapper083::ReadLow(WORD addr) //BYTE Mapper083::ReadLow(WORD addr)
public override byte ReadLow(ushort addr) public override byte ReadLow(ushort addr)
{ {
if ((addr & 0x5100) == 0x5100) if ((addr & 0x5100) == 0x5100)
{ {
return reg[2]; return reg[2];
} }
else if (addr >= 0x6000) else if (addr >= 0x6000)
{ {
return base.ReadLow(addr); return base.ReadLow(addr);
} }
return (BYTE)(addr >> 8); return (BYTE)(addr >> 8);
} }
//void Mapper083::WriteLow(WORD addr, BYTE data) //void Mapper083::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() ); //DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() );
switch (addr) switch (addr)
{ {
case 0x5101: case 0x5101:
case 0x5102: case 0x5102:
case 0x5103: case 0x5103:
reg[2] = data; reg[2] = data;
break; break;
} }
if (addr >= 0x6000) if (addr >= 0x6000)
{ {
base.WriteLow(addr, data); base.WriteLow(addr, data);
} }
} }
//void Mapper083::Write(WORD addr, BYTE data) //void Mapper083::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() ); //DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() );
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
case 0xB000: case 0xB000:
case 0xB0FF: case 0xB0FF:
case 0xB1FF: case 0xB1FF:
reg[0] = data; reg[0] = data;
chr_bank = (data & 0x30) << 4; chr_bank = (data & 0x30) << 4;
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
SetPROM_16K_Bank(6, (data & 0x30) | 0x0F); SetPROM_16K_Bank(6, (data & 0x30) | 0x0F);
break; break;
case 0x8100: case 0x8100:
reg[1] = (byte)(data & 0x80); reg[1] = (byte)(data & 0x80);
data &= 0x03; data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR); if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L); else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L);
else SetVRAM_Mirror(VRAM_MIRROR4H); else SetVRAM_Mirror(VRAM_MIRROR4H);
break; break;
case 0x8200: case 0x8200:
irq_counter = (irq_counter & 0xFF00) | (INT)data; irq_counter = (irq_counter & 0xFF00) | (INT)data;
// nes.cpu.ClrIRQ( IRQ_MAPPER ); // nes.cpu.ClrIRQ( IRQ_MAPPER );
break; break;
case 0x8201: case 0x8201:
irq_counter = (irq_counter & 0x00FF) | ((INT)data << 8); irq_counter = (irq_counter & 0x00FF) | ((INT)data << 8);
irq_enable = reg[1]; irq_enable = reg[1];
// nes.cpu.ClrIRQ( IRQ_MAPPER ); // nes.cpu.ClrIRQ( IRQ_MAPPER );
break; break;
case 0x8300: case 0x8300:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0x8301: case 0x8301:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0x8302: case 0x8302:
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
break; break;
case 0x8310: case 0x8310:
if (patch != 0) if (patch != 0)
{ {
SetVROM_2K_Bank(0, chr_bank | data); SetVROM_2K_Bank(0, chr_bank | data);
} }
else else
{ {
SetVROM_1K_Bank(0, chr_bank | data); SetVROM_1K_Bank(0, chr_bank | data);
} }
break; break;
case 0x8311: case 0x8311:
if (patch != 0) if (patch != 0)
{ {
SetVROM_2K_Bank(2, chr_bank | data); SetVROM_2K_Bank(2, chr_bank | data);
} }
else else
{ {
SetVROM_1K_Bank(1, chr_bank | data); SetVROM_1K_Bank(1, chr_bank | data);
} }
break; break;
case 0x8312: case 0x8312:
SetVROM_1K_Bank(2, chr_bank | data); SetVROM_1K_Bank(2, chr_bank | data);
break; break;
case 0x8313: case 0x8313:
SetVROM_1K_Bank(3, chr_bank | data); SetVROM_1K_Bank(3, chr_bank | data);
break; break;
case 0x8314: case 0x8314:
SetVROM_1K_Bank(4, chr_bank | data); SetVROM_1K_Bank(4, chr_bank | data);
break; break;
case 0x8315: case 0x8315:
SetVROM_1K_Bank(5, chr_bank | data); SetVROM_1K_Bank(5, chr_bank | data);
break; break;
case 0x8316: case 0x8316:
if (patch != 0) if (patch != 0)
{ {
SetVROM_2K_Bank(4, chr_bank | data); SetVROM_2K_Bank(4, chr_bank | data);
} }
else else
{ {
SetVROM_1K_Bank(6, chr_bank | data); SetVROM_1K_Bank(6, chr_bank | data);
} }
break; break;
case 0x8317: case 0x8317:
if (patch != 0) if (patch != 0)
{ {
SetVROM_2K_Bank(6, chr_bank | data); SetVROM_2K_Bank(6, chr_bank | data);
} }
else else
{ {
SetVROM_1K_Bank(7, chr_bank | data); SetVROM_1K_Bank(7, chr_bank | data);
} }
break; break;
case 0x8318: case 0x8318:
SetPROM_16K_Bank(4, (reg[0] & 0x30) | data); SetPROM_16K_Bank(4, (reg[0] & 0x30) | data);
break; break;
} }
} }
//void Mapper083::HSync(INT scanline) //void Mapper083::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
if (irq_counter <= 113) if (irq_counter <= 113)
{ {
// nes.cpu.IRQ(); // nes.cpu.IRQ();
irq_enable = 0; irq_enable = 0;
// nes.cpu.SetIRQ( IRQ_MAPPER ); // nes.cpu.SetIRQ( IRQ_MAPPER );
nes.cpu.SetIRQ(IRQ_TRIGGER); nes.cpu.SetIRQ(IRQ_TRIGGER);
} }
else else
{ {
irq_counter -= 113; irq_counter -= 113;
} }
} }
} }
//void Mapper083::SaveState(LPBYTE p) //void Mapper083::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = reg[0]; //p[0] = reg[0];
//p[1] = reg[1]; //p[1] = reg[1];
//p[2] = reg[2]; //p[2] = reg[2];
//*(INT*)&p[3] = chr_bank; //*(INT*)&p[3] = chr_bank;
//p[7] = irq_enable; //p[7] = irq_enable;
//*(INT*)&p[8] = irq_counter; //*(INT*)&p[8] = irq_counter;
} }
//void Mapper083::LoadState(LPBYTE p) //void Mapper083::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//reg[0] = p[0]; //reg[0] = p[0];
//reg[1] = p[1]; //reg[1] = p[1];
//reg[2] = p[2]; //reg[2] = p[2];
//chr_bank = *(INT*)&p[3]; //chr_bank = *(INT*)&p[3];
//irq_enable = p[7]; //irq_enable = p[7];
//irq_counter = *(INT*)&p[8]; //irq_counter = *(INT*)&p[8];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

391
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper085.cs
View File

@ -1,43 +1,42 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper085 Konami VRC7 // // Mapper085 Konami VRC7 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using INT = System.Int32;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper085 : Mapper public class Mapper085 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
INT irq_clock; INT irq_clock;
public Mapper085(NES parent) : base(parent) public Mapper085(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
irq_clock = 0; irq_clock = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
else else
{ {
SetCRAM_8K_Bank(0); SetCRAM_8K_Bank(0);
} }
#if FALSE//0 #if FALSE//0
// DWORD crc = nes.rom.GetPROM_CRC(); // DWORD crc = nes.rom.GetPROM_CRC();
@ -48,191 +47,191 @@ namespace VirtualNes.Core
// nes.SetRenderMethod( NES::TILE_RENDER ); // nes.SetRenderMethod( NES::TILE_RENDER );
// } // }
#endif #endif
nes.apu.SelectExSound(2); nes.apu.SelectExSound(2);
} }
//void Mapper085::Write(WORD addr, BYTE data) //void Mapper085::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr & 0xF038) switch (addr & 0xF038)
{ {
case 0x8000: case 0x8000:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0x8008: case 0x8008:
case 0x8010: case 0x8010:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0x9000: case 0x9000:
SetPROM_8K_Bank(6, data); SetPROM_8K_Bank(6, data);
break; break;
case 0x9010: case 0x9010:
case 0x9030: case 0x9030:
nes.apu.ExWrite(addr, data); nes.apu.ExWrite(addr, data);
break; break;
case 0xA000: case 0xA000:
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_1K_Bank(0, data); SetVROM_1K_Bank(0, data);
} }
else else
{ {
SetCRAM_1K_Bank(0, data); SetCRAM_1K_Bank(0, data);
} }
break; break;
case 0xA008: case 0xA008:
case 0xA010: case 0xA010:
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_1K_Bank(1, data); SetVROM_1K_Bank(1, data);
} }
else else
{ {
SetCRAM_1K_Bank(1, data); SetCRAM_1K_Bank(1, data);
} }
break; break;
case 0xB000: case 0xB000:
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_1K_Bank(2, data); SetVROM_1K_Bank(2, data);
} }
else else
{ {
SetCRAM_1K_Bank(2, data); SetCRAM_1K_Bank(2, data);
} }
break; break;
case 0xB008: case 0xB008:
case 0xB010: case 0xB010:
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_1K_Bank(3, data); SetVROM_1K_Bank(3, data);
} }
else else
{ {
SetCRAM_1K_Bank(3, data); SetCRAM_1K_Bank(3, data);
} }
break; break;
case 0xC000: case 0xC000:
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_1K_Bank(4, data); SetVROM_1K_Bank(4, data);
} }
else else
{ {
SetCRAM_1K_Bank(4, data); SetCRAM_1K_Bank(4, data);
} }
break; break;
case 0xC008: case 0xC008:
case 0xC010: case 0xC010:
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_1K_Bank(5, data); SetVROM_1K_Bank(5, data);
} }
else else
{ {
SetCRAM_1K_Bank(5, data); SetCRAM_1K_Bank(5, data);
} }
break; break;
case 0xD000: case 0xD000:
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_1K_Bank(6, data); SetVROM_1K_Bank(6, data);
} }
else else
{ {
SetCRAM_1K_Bank(6, data); SetCRAM_1K_Bank(6, data);
} }
break; break;
case 0xD008: case 0xD008:
case 0xD010: case 0xD010:
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_1K_Bank(7, data); SetVROM_1K_Bank(7, data);
} }
else else
{ {
SetCRAM_1K_Bank(7, data); SetCRAM_1K_Bank(7, data);
} }
break; break;
case 0xE000: case 0xE000:
data &= 0x03; data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR); if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR); else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L); else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L);
else SetVRAM_Mirror(VRAM_MIRROR4H); else SetVRAM_Mirror(VRAM_MIRROR4H);
break; break;
case 0xE008: case 0xE008:
case 0xE010: case 0xE010:
irq_latch = data; irq_latch = data;
break; break;
case 0xF000: case 0xF000:
irq_enable = (byte)(data & 0x03); irq_enable = (byte)(data & 0x03);
irq_counter = irq_latch; irq_counter = irq_latch;
irq_clock = 0; irq_clock = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xF008: case 0xF008:
case 0xF010: case 0xF010:
irq_enable = (byte)((irq_enable & 0x01) * 3); irq_enable = (byte)((irq_enable & 0x01) * 3);
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
} }
} }
//void Mapper085::Clock(INT cycles) //void Mapper085::Clock(INT cycles)
public override void Clock(int cycles) public override void Clock(int cycles)
{ {
if ((irq_enable & 0x02) != 0) if ((irq_enable & 0x02) != 0)
{ {
irq_clock += cycles * 4; irq_clock += cycles * 4;
while (irq_clock >= 455) while (irq_clock >= 455)
{ {
irq_clock -= 455; irq_clock -= 455;
irq_counter++; irq_counter++;
if (irq_counter == 0) if (irq_counter == 0)
{ {
irq_counter = irq_latch; irq_counter = irq_latch;
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
} }
//void Mapper085::SaveState(LPBYTE p) //void Mapper085::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
//p[0] = irq_enable; //p[0] = irq_enable;
//p[1] = irq_counter; //p[1] = irq_counter;
//p[2] = irq_latch; //p[2] = irq_latch;
//*((INT*)&p[4]) = irq_clock; //*((INT*)&p[4]) = irq_clock;
} }
//void Mapper085::LoadState(LPBYTE p) //void Mapper085::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
//irq_enable = p[0]; //irq_enable = p[0];
//irq_counter = p[1]; //irq_counter = p[1];
//irq_latch = p[2]; //irq_latch = p[2];
//irq_clock = *((INT*)&p[4]); //irq_clock = *((INT*)&p[4]);
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

5
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper086.cs
View File

@ -2,11 +2,8 @@
// Mapper086 Jaleco Early Mapper #2 // // Mapper086 Jaleco Early Mapper #2 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

34
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper087.cs
View File

@ -2,35 +2,31 @@
// Mapper087 Konami 74161/32 // // Mapper087 Konami 74161/32 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper087 : Mapper public class Mapper087 : Mapper
{ {
public Mapper087(NES parent) : base(parent) public Mapper087(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, 2, 3); SetPROM_32K_Bank(0, 1, 2, 3);
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
//void Mapper087::WriteLow(WORD addr, BYTE data) //void Mapper087::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if (addr == 0x6000) if (addr == 0x6000)
{ {
SetVROM_8K_Bank((data & 0x02) >> 1); SetVROM_8K_Bank((data & 0x02) >> 1);
} }
} }
} }
} }

183
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper088.cs
View File

@ -1,107 +1,104 @@
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper088 : Mapper public class Mapper088 : Mapper
{ {
BYTE reg; BYTE reg;
BYTE patch; BYTE patch;
public Mapper088(NES parent) : base(parent) public Mapper088(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE >= 8) if (VROM_1K_SIZE >= 8)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
patch = 0; patch = 0;
uint crc = nes.rom.GetPROM_CRC(); uint crc = nes.rom.GetPROM_CRC();
if (crc == 0xc1b6b2a6) if (crc == 0xc1b6b2a6)
{ // Devil Man(J) { // Devil Man(J)
patch = 1; patch = 1;
nes.SetRenderMethod(EnumRenderMethod.POST_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_RENDER);
} }
if (crc == 0xd9803a35) if (crc == 0xd9803a35)
{ // Quinty(J) { // Quinty(J)
nes.SetRenderMethod(EnumRenderMethod.POST_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_RENDER);
} }
} }
//void Mapper088::Write(WORD addr, BYTE data) //void Mapper088::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
reg = data; reg = data;
if (patch != 0) if (patch != 0)
{ {
if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_MIRROR4H); if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_MIRROR4H);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
} }
break; break;
case 0x8001: case 0x8001:
switch (reg & 0x07) switch (reg & 0x07)
{ {
case 0: case 0:
SetVROM_2K_Bank(0, data >> 1); SetVROM_2K_Bank(0, data >> 1);
break; break;
case 1: case 1:
SetVROM_2K_Bank(2, data >> 1); SetVROM_2K_Bank(2, data >> 1);
break; break;
case 2: case 2:
SetVROM_1K_Bank(4, data + 0x40); SetVROM_1K_Bank(4, data + 0x40);
break; break;
case 3: case 3:
SetVROM_1K_Bank(5, data + 0x40); SetVROM_1K_Bank(5, data + 0x40);
break; break;
case 4: case 4:
SetVROM_1K_Bank(6, data + 0x40); SetVROM_1K_Bank(6, data + 0x40);
break; break;
case 5: case 5:
SetVROM_1K_Bank(7, data + 0x40); SetVROM_1K_Bank(7, data + 0x40);
break; break;
case 6: case 6:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 7: case 7:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
} }
break; break;
case 0xC000: case 0xC000:
if (data != 0) SetVRAM_Mirror(VRAM_MIRROR4H); if (data != 0) SetVRAM_Mirror(VRAM_MIRROR4H);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
break; break;
} }
} }
//void Mapper088::SaveState(LPBYTE p) //void Mapper088::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = reg; p[0] = reg;
} }
//void Mapper088::LoadState(LPBYTE p) //void Mapper088::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
reg = p[0]; reg = p[0];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

50
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper089.cs
View File

@ -2,40 +2,36 @@
// Mapper089 SunSoft (水戸黄門) // // Mapper089 SunSoft (水戸黄門) //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper089 : Mapper public class Mapper089 : Mapper
{ {
public Mapper089(NES parent) : base(parent) public Mapper089(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
//void Mapper089::Write(WORD addr, BYTE data) //void Mapper089::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
if ((addr & 0xFF00) == 0xC000) if ((addr & 0xFF00) == 0xC000)
{ {
SetPROM_16K_Bank(4, (data & 0x70) >> 4); SetPROM_16K_Bank(4, (data & 0x70) >> 4);
SetVROM_8K_Bank(((data & 0x80) >> 4) | (data & 0x07)); SetVROM_8K_Bank(((data & 0x80) >> 4) | (data & 0x07));
if ((data & 0x08) != 0) SetVRAM_Mirror(VRAM_MIRROR4H); if ((data & 0x08) != 0) SetVRAM_Mirror(VRAM_MIRROR4H);
else SetVRAM_Mirror(VRAM_MIRROR4L); else SetVRAM_Mirror(VRAM_MIRROR4L);
} }
} }
} }
} }

10
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper090.cs
View File

@ -1,13 +1,11 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper090 PC-JY-?? // // Mapper090 PC-JY-?? //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
using VirtualNes.Core.Debug; using VirtualNes.Core.Debug;
using static VirtualNes.Core.CPU;
using static VirtualNes.MMU;
using BYTE = System.Byte;
using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

164
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper091.cs
View File

@ -1,104 +1,102 @@
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
// Mapper091 PC-HK-SF3 // // Mapper091 PC-HK-SF3 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using static VirtualNes.MMU;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper091 : Mapper public class Mapper091 : Mapper
{ {
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
public Mapper091(NES parent) : base(parent) public Mapper091(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(PROM_8K_SIZE - 2, PROM_8K_SIZE - 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(PROM_8K_SIZE - 2, PROM_8K_SIZE - 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_8K_SIZE != 0) if (VROM_8K_SIZE != 0)
{ {
SetVROM_8K_Bank(0, 0, 0, 0, 0, 0, 0, 0); SetVROM_8K_Bank(0, 0, 0, 0, 0, 0, 0, 0);
} }
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER); nes.SetRenderMethod(EnumRenderMethod.POST_ALL_RENDER);
} }
//void Mapper091::WriteLow(WORD addr, BYTE data) //void Mapper091::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
//DEBUGOUT( "$%04X:$%02X(%3d) L=%3d\n", addr, data, data, nes.GetScanline() ); //DEBUGOUT( "$%04X:$%02X(%3d) L=%3d\n", addr, data, data, nes.GetScanline() );
switch (addr & 0xF003) switch (addr & 0xF003)
{ {
case 0x6000: case 0x6000:
case 0x6001: case 0x6001:
case 0x6002: case 0x6002:
case 0x6003: case 0x6003:
SetVROM_2K_Bank((byte)((addr & 0x03) * 2), data); SetVROM_2K_Bank((byte)((addr & 0x03) * 2), data);
break; break;
case 0x7000: case 0x7000:
SetPROM_8K_Bank(4, data); SetPROM_8K_Bank(4, data);
break; break;
case 0x7001: case 0x7001:
SetPROM_8K_Bank(5, data); SetPROM_8K_Bank(5, data);
break; break;
case 0x7002: case 0x7002:
irq_enable = 0; irq_enable = 0;
irq_counter = 0; irq_counter = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0x7003: case 0x7003:
irq_enable = 1; irq_enable = 1;
break; break;
} }
} }
//void Mapper091::HSync(INT scanline) //void Mapper091::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if ((scanline >= 0 && scanline < 240) && nes.ppu.IsDispON()) if ((scanline >= 0 && scanline < 240) && nes.ppu.IsDispON())
{ {
if (irq_enable != 0) if (irq_enable != 0)
{ {
irq_counter++; irq_counter++;
} }
if (irq_counter >= 8) if (irq_counter >= 8)
{ {
// nes.cpu.IRQ_NotPending(); // nes.cpu.IRQ_NotPending();
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
//void Mapper091::SaveState(LPBYTE p) //void Mapper091::SaveState(LPBYTE p)
public override void SaveState(byte[] p) public override void SaveState(byte[] p)
{ {
p[0] = irq_enable; p[0] = irq_enable;
p[1] = irq_counter; p[1] = irq_counter;
} }
//void Mapper091::LoadState(LPBYTE p) //void Mapper091::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
irq_enable = p[0]; irq_enable = p[0];
irq_counter = p[1]; irq_counter = p[1];
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }
} }
} }

8
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper092.cs
View File

@ -1,13 +1,9 @@
///////////////////////////////// /////////////////////////////////
// Mapper092 Jaleco/Type1 Higher bank switch // // Mapper092 Jaleco/Type1 Higher bank switch //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
using VirtualNes.Core.Debug; using VirtualNes.Core.Debug;
using static VirtualNes.MMU;
using INT = System.Int32;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {

50
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper093.cs
View File

@ -2,37 +2,33 @@
// Mapper093 SunSoft (Fantasy Zone) // // Mapper093 SunSoft (Fantasy Zone) //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper093 : Mapper public class Mapper093 : Mapper
{ {
public Mapper093(NES parent) : base(parent) public Mapper093(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_8K_SIZE != 0) if (VROM_8K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper093::WriteLow(WORD addr, BYTE data) //void Mapper093::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
if (addr == 0x6000) if (addr == 0x6000)
{ {
SetPROM_16K_Bank(4, data); SetPROM_16K_Bank(4, data);
} }
} }
} }
} }

42
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper094.cs
View File

@ -2,34 +2,30 @@
// Mapper094 Capcom 74161/32 // // Mapper094 Capcom 74161/32 //
////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU; using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper094 : Mapper public class Mapper094 : Mapper
{ {
public Mapper094(NES parent) : base(parent) public Mapper094(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1); SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
} }
//void Mapper094::Write(WORD addr, BYTE data) //void Mapper094::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
if ((addr & 0xFFF0) == 0xFF00) if ((addr & 0xFFF0) == 0xFF00)
{ {
SetPROM_16K_Bank(4, (data >> 2) & 0x7); SetPROM_16K_Bank(4, (data >> 2) & 0x7);
} }
} }
} }
} }

Some files were not shown because too many files have changed in this diff Show More