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sin365 2024-08-06 17:49:14 +08:00
parent ba1ac5d5c2
commit 44311f075b
5 changed files with 655 additions and 470 deletions
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448
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper163.cs
View File

@ -11,229 +11,229 @@ using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper163 : Mapper public class Mapper163 : Mapper
{ {
//BYTE strobe; //BYTE strobe;
//BYTE security; //BYTE security;
//BYTE trigger; //BYTE trigger;
//BYTE rom_type; //BYTE rom_type;
//BYTE reg[2];
BYTE laststrobe, trigger;
BYTE[] reg = new byte[8];
public Mapper163(NES parent) : base(parent)
{
/*
reg[1] = 0xFF;
strobe = 1;
security = trigger = reg[0] = 0x00;
rom_type = 0;
SetPROM_32K_Bank(15);
DWORD crc = nes.rom.GetPROM_CRC();
if( crc == 0xb6a10d5d ) { // Hu Lu Jin Gang (NJ039) (Ch) [dump]
SetPROM_32K_Bank(0);
}
if( crc == 0xf52468e7 ) { // San Guo Wu Shuang - Meng Jiang Zhuan (NJ047) (Ch) [dump]
rom_type = 1;
}
*/
MemoryUtility.ZEROMEMORY(reg, reg.Length); //BYTE reg[2];
laststrobe = 1; BYTE[] reg = new byte[3];
SetPROM_32K_Bank((reg[0] << 4) | (reg[1] & 0xF)); BYTE strobe, trigger;
//SetPROM_32K_Bank(0); ushort security;
SetCRAM_8K_Bank(0); BYTE rom_type;
}
INT www, index;
//BYTE Mapper163::ReadLow(WORD A) public Mapper163(NES parent) : base(parent)
public override byte ReadLow(ushort A) {
{ }
/*
if((addr>=0x5000 && addr<0x6000)) static Int32[] index_adjust = new Int32[]{ -1, -1, -1, -1, 2, 4, 6, 8 };
{ static Int16[] step_table = new Int16[] {
switch (addr & 0x7700) 7,8,9,10,11,12,13,14,16,17,19,21,23,25,28,31,34,37,41,45,50,55,
{ 60,66,73,80,88,97,107,118,130,143,157,173,190,209,230,253,279,
case 0x5100: 307,337,371,408,449,494,544,598,658,724,796,876,963,1060,
return security; 1166,1282,1411,1552,1707,1878,2066,2272,2499,2749,3024,3327,
break; 3660,4026,4428,4871,5358,5894,6484,7132,7845,8630,9493,10442,
case 0x5500: 11487,12635,13899,15289,16818,18500,20350,22385,24623,27086,29794,32767
if(trigger) };
return security;
else BYTE adpcm_decoder(BYTE data)
return 0; {
break; int sb, delta;
} int cur_sample = 0;
return 4; if ((data & 8) != 0) sb = 1; else sb = 0;
} data &= 7;
else if( addr>=0x6000 ) { delta = (step_table[index] * data) / 4 + step_table[index] / 8;
return CPU_MEM_BANK[addr>>13][addr&0x1FFF]; if (sb == 1) delta = -delta;
} cur_sample += delta;
return Mapper::ReadLow( addr ); if (cur_sample > 32767) cur_sample = 32767;
*/ else if (cur_sample < -32768) cur_sample = -32768;
if ((A < 0x6000) && (A >= 0x5000)) else cur_sample = cur_sample;
{ index += index_adjust[data];
switch (A & 0x7700) if (index < 0) index = 0;
{ if (index > 88) index = 88;
case 0x5100: return (byte)(reg[2] | reg[0] | reg[1] | reg[3] ^ 0xff); break; return (byte)(cur_sample & 0xff);
case 0x5500: }
if (trigger != 0)
return (byte)(reg[2] | reg[1]); // Lei Dian Huang Bi Ka Qiu Chuan Shuo (NJ046) may broke other games //void Mapper163::Reset()
else public override void Reset()
return 0; {
}
return 4; index = 0;
}
else reg[1] = 0xFF;
return base.ReadLow(A); strobe = 1;
} security = trigger = reg[0] = 0x00;
rom_type = 0;
//void Mapper163::WriteLow(WORD A, BYTE V) SetPROM_32K_Bank(15);
public override void WriteLow(ushort A, byte V)
{ // jedi_table_init();
/*
if((addr>=0x4020 && addr<0x6000)) uint crc = nes.rom.GetPROM_CRC();
{ if (crc == 0xb6a10d5d)
DEBUGOUT("W %.4X %.2X\n",addr,data); { // Hu Lu Jin Gang (NJ039) (Ch) [dump]
if(addr==0x5101){ SetPROM_32K_Bank(0);
if(strobe && !data){ }
trigger ^= 1; if (crc == 0xf52468e7 // San Guo Wu Shuang - Meng Jiang Zhuan (NJ047) (Ch) [dump]
// trigger ^= 0xFF; || crc == 0x696D98E3)
} { // San Guo Zhi Lv Bu Zhuan (NJ040) (Ch) [dump]
strobe = data; rom_type = 1;
}else if(addr==0x5100 && data==6){ }
SetPROM_32K_Bank(3); if (crc == 0xEFF96E8A)
} { // Mo Shou Shi Jie E Mo Lie Ren (NJ097) (Ch) [dump]
else{ rom_type = 2;
switch (addr & 0x7300) }
{
case 0x5000: www = 0;
reg[1]=data; }
SetPROM_32K_Bank( (reg[1] & 0xF) | (reg[0] << 4) );
if(!(reg[1]&0x80)&&(nes.ppu.GetScanlineNo()<128)) ///BYTE Mapper163::ReadLow(WORD addr)
SetCRAM_8K_Bank(0); public override byte ReadLow(ushort addr)
if(rom_type==1) SetCRAM_8K_Bank(0); {
break; // DEBUGOUT( "ReadLow - addr= %04x\n", addr );
case 0x5200:
reg[0]=data; if ((addr >= 0x5000 && addr < 0x6000))
SetPROM_32K_Bank( (reg[1] & 0xF) | (reg[0] << 4) ); {
break; switch (addr & 0x7700)
case 0x5300: {
security=data; case 0x5100:
break; return (byte)security;
} break;
} case 0x5500:
} if (trigger!=0)
else if( addr>=0x6000 ) { return (byte)security;
CPU_MEM_BANK[addr>>13][addr&0x1FFF] = data; else
} return 0;
*/ break;
if ((A < 0x6000) && (A >= 0x5000)) }
{ return 4;
if (A == 0x5300) }
{ else if (addr >= 0x6000)
A = (ushort)(A + 1 - 1); {
} return CPU_MEM_BANK[addr >> 13][addr & 0x1FFF];
}
if (A == 0x5101) return base.ReadLow(addr);
{ }
if (laststrobe != 0 && V == 0)
{ //void Mapper163::WriteLow(WORD addr, BYTE data)
trigger ^= 1; public override void WriteLow(ushort addr, byte data)
} {
laststrobe = V; // if(addr==0x5200) DEBUGOUT( "WriteLow - addr= %04x ; dat= %03x\n", addr, data );
}
else if (A == 0x5100 && V == 6) //damn thoose protected games if ((addr >= 0x4020 && addr < 0x6000))
SetPROM_32K_Bank(3); {
else if (addr == 0x5101)
{ {
switch (A & 0x7300) if (strobe !=0 && data == 0)
{ {
case 0x5200: reg[0] = V; SetPROM_32K_Bank((reg[0] << 4) | reg[1] & 0xF); SetCRAM_8K_Bank(0); break; trigger ^= 1;
case 0x5000: reg[1] = V; SetPROM_32K_Bank((reg[0] << 4) | reg[1] & 0xF); SetCRAM_8K_Bank(0); if ((reg[1] & 0x80) == 0 && (nes.GetScanline() < 128)) SetCRAM_8K_Bank(0); break; // trigger ^= 0xFF;
case 0x5300: reg[2] = V; break; }
case 0x5100: reg[3] = V; SetPROM_32K_Bank((reg[0] << 4) | reg[1] & 0xF); SetCRAM_8K_Bank(0); break; strobe = data;
} }
} else if (addr == 0x5100 && data == 6)
} {
//071 SetPROM_32K_Bank(3);
else if ((A & 0xFF00) == 0x4800) }
{ else
//512KרÓà {
if (PROM_8K_SIZE == 64) switch (addr & 0x7300)
{ {
reg[A & 3] = V; case 0x5000:
if (A == 0x4802) reg[1] = data;
SetPROM_32K_Bank(((reg[1] >> 1) & 3) | (reg[2] << 2)); SetPROM_32K_Bank((reg[1] & 0xF) | (reg[0] << 4));
} if ((reg[1] & 0x80) == 0 && (nes.ppu.GetScanlineNo() < 128))
} SetCRAM_8K_Bank(0);
else if (rom_type == 1) SetCRAM_8K_Bank(0);
base.WriteLow(A, V); break;
} case 0x5100:
reg[2] = data;
//void Mapper163::HSync(int scanline) // nes.apu.Write(0x4011,(decode(reg[0]&0xf)<<3));
public override void HSync(int scanline) break;
{ case 0x5200:
//sline = scanline; reg[0] = data;
/* SetPROM_32K_Bank((reg[1] & 0xF) | (reg[0] << 4));
if( (reg[1]&0x80) && nes.ppu.IsDispON() ) { break;
if(scanline==127){ case 0x5300:
SetCRAM_4K_Bank(0, 1); security = data;
SetCRAM_4K_Bank(4, 1); break;
} }
if (rom_type==1){ }
if(scanline<127){ }
SetCRAM_4K_Bank(0, 0); else if (addr >= 0x6000)
SetCRAM_4K_Bank(4, 0); {
} CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
}else{ if ((addr >= 0x7900 && addr <= 0x79FF))
if(scanline==239){ {
SetCRAM_4K_Bank(0, 0); // WAVRAM[addr&0xFF] = data;
SetCRAM_4K_Bank(4, 0); // if(addr==0x79FF){
} // memcpy( YWRAM+(www*256), WAVRAM, 256);
} // www++;
} // }
*/ // nes.apu.Write(0x4011,(adpcm_decoder(data)));
if ((reg[1] & 0x80) != 0) nes.apu.Write(0x4011, data);
{ }
if (scanline == 239) }
{ }
SetCRAM_4K_Bank(0, 0);
SetCRAM_4K_Bank(4, 0); //void Mapper163::Write(WORD addr, BYTE data)
} public override void Write(ushort addr, byte data)
else if (scanline == 127) {
{ // DEBUGOUT( "Write - addr= %04x ; dat= %03x\n", addr, data );
SetCRAM_4K_Bank(0, 1); }
SetCRAM_4K_Bank(4, 1);
} //void Mapper163::HSync(int scanline)
} public override void HSync(int scanline)
} {
if ((reg[1] & 0x80) !=0 && nes.ppu.IsDispON())
//void Mapper163::SaveState(LPBYTE p) {
public override void SaveState(byte[] p) if (scanline == 127)
{ {
//p[0] = reg[0]; SetCRAM_4K_Bank(0, 1);
//p[1] = reg[1]; SetCRAM_4K_Bank(4, 1);
for (byte i = 0; i < 8; i++) }
p[i] = reg[i]; if (rom_type == 1)
p[8] = laststrobe; {
p[9] = trigger; if (scanline < 127)
} {
SetCRAM_4K_Bank(0, 0);
//void Mapper163::LoadState(LPBYTE p) SetCRAM_4K_Bank(4, 0);
public override void LoadState(byte[] p) }
{ }
else
//reg[0] = p[0]; {
//reg[1] = p[1]; if (scanline == 239)
for (byte i = 0; i < 8; i++) {
reg[i] = p[i]; SetCRAM_4K_Bank(0, 0);
laststrobe = p[8]; SetCRAM_4K_Bank(4, 0);
trigger = p[9]; if (rom_type == 2) SetCRAM_4K_Bank(4, 1);
} }
}
public override void Reset() }
{ }
}
///void Mapper163::PPU_Latch(WORD addr)
} //{
// if (DirectInput.m_Sw[DIK_PAUSE])
// {
// nes.Dump_YWRAM();
// }
//}
//void Mapper163::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
p[0] = reg[0];
p[1] = reg[1];
}
//void Mapper163::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
reg[0] = p[0];
reg[1] = p[1];
}
}
} }

82
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper175.cs
View File

@ -18,51 +18,51 @@ namespace VirtualNes.Core
} }
public override void Reset() public override void Reset()
{ {
SetPROM_16K_Bank(4, 0); SetPROM_16K_Bank(4, 0);
SetPROM_16K_Bank(6, 0); SetPROM_16K_Bank(6, 0);
reg_dat = 0; reg_dat = 0;
if (VROM_1K_SIZE != 0) if (VROM_1K_SIZE != 0)
{ {
SetVROM_8K_Bank(0); SetVROM_8K_Bank(0);
} }
} }
//void Mapper175::Read(WORD addr, BYTE data) //BYTE Mapper175::Read(WORD addr)
public override void Read(ushort addr, byte data) public override void Read(ushort addr, byte data)
{ {
if (addr == 0xFFFC) if (addr == 0xFFFC)
{ {
SetPROM_16K_Bank(4, reg_dat & 0x0F); SetPROM_16K_Bank(4, reg_dat & 0x0F);
SetPROM_8K_Bank(6, (reg_dat & 0x0F) * 2); SetPROM_8K_Bank(6, (reg_dat & 0x0F) * 2);
} }
} }
//void Mapper175::Write(WORD addr, BYTE data) //void Mapper175::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
switch (addr) switch (addr)
{ {
case 0x8000: case 0x8000:
if ((data & 0x04) != 0) if ((data & 0x04)!=0)
{ {
SetVRAM_Mirror(VRAM_HMIRROR); SetVRAM_Mirror(VRAM_HMIRROR);
} }
else else
{ {
SetVRAM_Mirror(VRAM_VMIRROR); SetVRAM_Mirror(VRAM_VMIRROR);
} }
break; break;
case 0xA000: case 0xA000:
reg_dat = data; reg_dat = data;
SetPROM_8K_Bank(7, (reg_dat & 0x0F) * 2 + 1); SetPROM_8K_Bank(7, (reg_dat & 0x0F) * 2 + 1);
SetVROM_8K_Bank(reg_dat & 0x0F); SetVROM_8K_Bank(reg_dat & 0x0F);
break; break;
} }
} }
public override bool IsStateSave() public override bool IsStateSave()
{ {
return true; return true;
} }

216
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper176.cs
View File

@ -1,53 +1,233 @@
using static VirtualNes.MMU; //////////////////////////////////////////////////////////////////////////
// Mapper176 ShuQiYu / HengGe / WaiXing //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System; using System;
using Codice.CM.Client.Differences;
using System.Runtime.ConstrainedExecution;
namespace VirtualNes.Core namespace VirtualNes.Core
{ {
public class Mapper176 : Mapper public class Mapper176 : Mapper
{ {
BYTE prg, chr; BYTE reg5000;
BYTE reg5001;
BYTE reg5010;
BYTE reg5011;
BYTE reg5013;
BYTE reg5FF1;
BYTE reg5FF2;
BYTE we_sram;
BYTE SBW, sp_rom;
public Mapper176(NES parent) : base(parent) public Mapper176(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
//prg = ~0; if (PROM_16K_SIZE > 32)
prg = unchecked((byte)(~0)); {
chr = 0; SetPROM_32K_Bank(0, 1, (PROM_8K_SIZE / 2) - 2, (PROM_8K_SIZE / 2) - 1); //For 1M byte Cartridge
Sync(); }
else
{
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
}
// SetPROM_32K_Bank( PROM_8K_SIZE-4, PROM_8K_SIZE-3, PROM_8K_SIZE-2, PROM_8K_SIZE-1 );
if (VROM_1K_SIZE!=0) SetVROM_8K_Bank(0);
reg5000 = 0;
reg5001 = 0;
reg5010 = 0;
reg5011 = 0;
reg5013 = 0;
reg5FF1 = 0;
reg5FF2 = 0;
we_sram = 0;
SBW = 0;
sp_rom = 0;
uint crc = nes.rom.GetPROM_CRC();
if (crc == 0x095D8678 //[ES-0122] Shuang Yue Zhuan (C)
|| crc == 0xD5F7AAEF)
{ //[ES-XXXX] Shen Feng Jian (C)
sp_rom = 1;
nes.SetSAVERAM_SIZE(32 * 1024);
}
/*
crc == 0x416C07A1 //[ES-1006] Meng Huan Zhi Xing IV (C) & WXN-梦幻之星 √
crc == 0x94782FBD //[ES-1057] San Guo Zhi - Xiong Ba Tian Xia (C)
crc == 0xF9863ADF //[ES-1066] Xi Chu Ba Wang (C)
crc == 0xB511C04B //[ES-1071] San Xia Wu Yi (C)
crc == 0x1923A8C5 //[ES-1087] Shui Hu Shen Shou (C) & WXN-水浒神兽(fix) √
crc == 0x095D8678 //[ES-0122] Shuang Yue Zhuan (C)
crc == 0x8f6ab5ac //WXN-三国忠烈传 √
crc == 0x99051cb5 //WXN-雄霸天下 √
crc == 0xf29c8186 //WXN-大富翁2-上海大亨 √
crc == 0xc768098b //WXN-三侠五义 √
crc == 0x49f22159 //WXN-超级大富翁 √
crc == 0xf354d847 //WXN-格兰帝亚 √
crc == 0x5ee2ef97 //WXN-帝国时代(fix) √
crc == 0x977d22c3 //WXN-破釜沉舟(fix) √
crc == 0xf1d803f3 //WXN-西楚霸王(fix) √
crc == 0x85dd49b6 //WXN-口袋金(fix) √
crc == 0x97b82f53 //WXN-爆笑三国(fix) √
crc == 0xce2ea530 //WXN-宠物翡翠(fix) √
*/
} }
void Sync() //BYTE Mapper176::ReadLow(WORD addr)
public override byte ReadLow(ushort addr)
{ {
//setprg8r(0x10,0x6000,0); if (sp_rom == 1)
SetPROM_32K_Bank(prg >> 1); {
SetVROM_8K_Bank(chr); if (addr >= 0x6000)
{
switch (we_sram)
{
case 0xE4:
case 0xEC: return WRAM[(addr & 0x1FFF) + 0x0000];
case 0xE5:
case 0xED: return WRAM[(addr & 0x1FFF) + 0x2000];
case 0xE6:
case 0xEE: return WRAM[(addr & 0x1FFF) + 0x4000];
case 0xE7:
case 0xEF: return WRAM[(addr & 0x1FFF) + 0x6000];
default: return CPU_MEM_BANK[addr >> 13][addr & 0x1FFF];
}
}
}
return base.ReadLow(addr);
} }
//void Mapper176::WriteLow(WORD addr, BYTE data) //void Mapper176::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
// DEBUGOUT("Address=%04X Data=%02X\n", addr&0xFFFF, data&0xFF );
switch (addr) switch (addr)
{ {
case 0x5000:
reg5000 = data;
break;
case 0x5001: //[ES-1006] Meng Huan Zhi Xing IV (C)
reg5001 = data;
if (SBW!=0) SetPROM_32K_Bank(reg5001);
break;
case 0x5010:
reg5010 = data;
if (reg5010 == 0x24) SBW = 1;
break;
case 0x5011:
reg5011 = (byte)(data >> 1);
if (SBW!=0) SetPROM_32K_Bank(reg5011);
break;
case 0x5013:
reg5013 = data;
break;
case 0x5ff1: case 0x5ff1:
prg = data; Sync(); reg5FF1 = (byte)(data >> 1);
SetPROM_32K_Bank(reg5FF1);
break; break;
case 0x5ff2: case 0x5ff2:
chr = data; Sync(); reg5FF2 = data;
break; SetVROM_8K_Bank(reg5FF2);
default:
break; break;
} }
if (addr >= 0x6000)
if (sp_rom == 1)
{ {
CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data; if (addr >= 0x6000)
{
switch (we_sram)
{
case 0xE4: //CPU_MEM_BANK
case 0xEC: //CPU_MEM_BANK
WRAM[(addr & 0x1FFF) + 0x0000] = data;
CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
break;
case 0xE5: //SRAM
case 0xED: //SRAM
WRAM[(addr & 0x1FFF) + 0x2000] = data;
break;
case 0xE6:
case 0xEE:
WRAM[(addr & 0x1FFF) + 0x4000] = data;
break;
case 0xE7:
case 0xEF:
WRAM[(addr & 0x1FFF) + 0x6000] = data;
break;
default:
CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
break;
}
}
} }
else
{
if (addr >= 0x6000)
{
// if ( we_sram == 0 ){
CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
// }
}
}
}
//void Mapper176::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
// DEBUGOUT("Address=%04X Data=%02X\n", addr&0xFFFF, data&0xFF );
if (addr == 0xa000)
{
data &= 0x03;
if (data == 0) SetVRAM_Mirror(VRAM_VMIRROR);
else if (data == 1) SetVRAM_Mirror(VRAM_HMIRROR);
else if (data == 2) SetVRAM_Mirror(VRAM_MIRROR4L);
else SetVRAM_Mirror(VRAM_MIRROR4H);
}
if (addr == 0xa001)
{
// we_sram = data & 0x03;
we_sram = data;
}
}
//void Mapper176::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
p[0] = reg5000;
p[1] = reg5001;
p[2] = reg5010;
p[3] = reg5011;
p[4] = reg5013;
p[5] = reg5FF1;
p[6] = reg5FF2;
p[7] = we_sram;
p[8] = SBW;
p[9] = sp_rom;
}
//void Mapper176::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
reg5000 = p[0];
reg5001 = p[1];
reg5010 = p[2];
reg5011 = p[3];
reg5013 = p[4];
reg5FF1 = p[5];
reg5FF2 = p[6];
we_sram = p[7];
SBW = p[8];
sp_rom = p[9];
} }
public override bool IsStateSave() public override bool IsStateSave()

113
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper178.cs
View File

@ -1,8 +1,10 @@
using static VirtualNes.MMU; //////////////////////////////////////////////////////////////////////////
// Mapper178 Education / WaiXing_FS305 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU; using static VirtualNes.Core.CPU;
using INT = System.Int32; using INT = System.Int32;
using BYTE = System.Byte; using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences; using Codice.CM.Client.Differences;
namespace VirtualNes.Core namespace VirtualNes.Core
@ -10,63 +12,66 @@ namespace VirtualNes.Core
public class Mapper178 : Mapper public class Mapper178 : Mapper
{ {
BYTE[] reg = new byte[3]; BYTE[] reg = new byte[3];
BYTE banknum; BYTE banknum;
public Mapper178(NES parent) : base(parent) BYTE OP_rom;
public Mapper178(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
reg[0] = 0; reg[0] = 0;
reg[1] = 0; reg[1] = 0;
reg[2] = 0; reg[2] = 0;
banknum = 0; banknum = 0;
SetBank_CPU(); SetBank_CPU();
} OP_rom = 0;
//void Mapper178::WriteLow(WORD addr, BYTE data) uint crc = nes.rom.GetPROM_CRC();
public override void WriteLow(ushort addr, byte data) if (crc == 0x925926BC //[ES-XXXX] Kou Dai Zuan Shi Zhi Chong Wu Xiao Jing Ling 2 (C)
{ || crc == 0xB0B13DBD) //[ES-XXXX] Chong Wu Fei Cui Zhi Chong Wu Xiao Jing Ling IV (C)
if (addr == 0x4800) {
{ OP_rom = 1;
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR); }
else SetVRAM_Mirror(VRAM_VMIRROR); }
}
else if (addr == 0x4801)
{
reg[0] = (byte)((data >> 1) & 0x0f);
SetBank_CPU();
}
else if (addr == 0x4802)
{
reg[1] = (byte)((data << 2) & 0x0f);
// SetBank_CPU();
}
else if (addr == 0x4803)
{
//unknown
}
else if (addr >= 0x6000)
{
CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
}
}
//void Write(WORD addr, BYTE data) //void Mapper178::WriteLow(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void WriteLow(ushort addr, byte data)
{ {
// SetPROM_32K_Bank( data ); // if( addr >= 0x4000 && addr <= 0x5FFF ) DEBUGOUT("Address=%04X Data=%02X\n", addr&0xFFFF, data&0xFF );
} if (addr == 0x4800)
{
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR);
}
else if (addr == 0x4801)
{
reg[0] = (byte)((data >> 1) & 0x0F);
if (OP_rom!=0) reg[0] = (byte)(data << 2);
SetBank_CPU();
}
else if (addr == 0x4802)
{
reg[1] = (byte)(data << 2);
if (OP_rom!=0) reg[1] = data;
SetBank_CPU();
}
else if (addr == 0x4803)
{
//unknown
reg[2] = data;
}
else if (addr >= 0x6000)
{
CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
}
}
void SetBank_CPU() void SetBank_CPU()
{ {
banknum = (byte)((reg[0] + reg[1]) & 0x0f); banknum = (byte)(reg[0] | reg[1]);
SetPROM_32K_Bank(banknum); // DEBUGOUT("Bank=%02X\n", banknum&0xFF );
} SetPROM_32K_Bank(banknum);
}
public override bool IsStateSave() }
{
return true;
}
}
} }

266
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper192.cs
View File

@ -13,43 +13,43 @@ namespace VirtualNes.Core
public class Mapper192 : Mapper public class Mapper192 : Mapper
{ {
BYTE[] reg = new byte[8]; BYTE[] reg = new byte[8];
BYTE prg0, prg1; BYTE prg0, prg1;
BYTE chr01, chr23, chr4, chr5, chr6, chr7; BYTE chr01, chr23, chr4, chr5, chr6, chr7;
BYTE we_sram; BYTE we_sram;
BYTE irq_type; BYTE irq_type;
BYTE irq_enable; BYTE irq_enable;
BYTE irq_counter; BYTE irq_counter;
BYTE irq_latch; BYTE irq_latch;
BYTE irq_request; BYTE irq_request;
public Mapper192(NES parent) : base(parent) public Mapper192(NES parent) : base(parent)
{ {
} }
public override void Reset() public override void Reset()
{ {
for (INT i = 0; i < 8; i++) for (byte i = 0; i < 8; i++)
{ {
reg[i] = 0x00; reg[i] = 0x00;
} }
prg0 = 0; prg0 = 0;
prg1 = 1; prg1 = 1;
SetBank_CPU(); SetBank_CPU();
chr01 = 0; chr01 = 0;
chr23 = 2; chr23 = 2;
chr4 = 4; chr4 = 4;
chr5 = 5; chr5 = 5;
chr6 = 6; chr6 = 6;
chr7 = 7; chr7 = 7;
SetBank_PPU(); SetBank_PPU();
we_sram = 0; // Disable we_sram = 0; // Disable
irq_enable = 0; // Disable irq_enable = 0; // Disable
irq_counter = 0; irq_counter = 0;
irq_latch = 0; irq_latch = 0;
irq_request = 0; irq_request = 0;
} }
//BYTE Mapper192::ReadLow(WORD addr) //BYTE Mapper192::ReadLow(WORD addr)
@ -81,116 +81,116 @@ namespace VirtualNes.Core
//void Mapper192::Write(WORD addr, BYTE data) //void Mapper192::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data) public override void Write(ushort addr, byte data)
{ {
//DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() ); //DEBUGOUT( "MPRWR A=%04X D=%02X L=%3d CYC=%d\n", addr&0xFFFF, data&0xFF, nes.GetScanline(), nes.cpu.GetTotalCycles() );
switch (addr & 0xE001) switch (addr & 0xE001)
{ {
case 0x8000: case 0x8000:
reg[0] = data; reg[0] = data;
SetBank_CPU(); SetBank_CPU();
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x8001: case 0x8001:
reg[1] = data; reg[1] = data;
switch (reg[0] & 0x07) switch (reg[0] & 0x07)
{ {
case 0x00: case 0x00:
chr01 = data; chr01 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x01: case 0x01:
chr23 = data; chr23 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x02: case 0x02:
chr4 = data; chr4 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x03: case 0x03:
chr5 = data; chr5 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x04: case 0x04:
chr6 = data; chr6 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x05: case 0x05:
chr7 = data; chr7 = data;
SetBank_PPU(); SetBank_PPU();
break; break;
case 0x06: case 0x06:
prg0 = data; prg0 = data;
SetBank_CPU(); SetBank_CPU();
break; break;
case 0x07: case 0x07:
prg1 = data; prg1 = data;
SetBank_CPU(); SetBank_CPU();
break; break;
} }
break; break;
case 0xA000: case 0xA000:
reg[2] = data; reg[2] = data;
if (!nes.rom.Is4SCREEN()) if (!nes.rom.Is4SCREEN())
{ {
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR); if ((data & 0x01)!=0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR); else SetVRAM_Mirror(VRAM_VMIRROR);
} }
break; break;
case 0xA001: case 0xA001:
reg[3] = data; reg[3] = data;
break; break;
case 0xC000: case 0xC000:
reg[4] = data; reg[4] = data;
irq_counter = data; irq_counter = data;
irq_request = 0; irq_request = 0;
break; break;
case 0xC001: case 0xC001:
reg[5] = data; reg[5] = data;
irq_latch = data; irq_latch = data;
irq_request = 0; irq_request = 0;
break; break;
case 0xE000: case 0xE000:
reg[6] = data; reg[6] = data;
irq_enable = 0; irq_enable = 0;
irq_request = 0; irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER); nes.cpu.ClrIRQ(IRQ_MAPPER);
break; break;
case 0xE001: case 0xE001:
reg[7] = data; reg[7] = data;
irq_enable = 1; irq_enable = 1;
irq_request = 0; irq_request = 0;
break; break;
} }
} }
//void Mapper192::HSync(INT scanline) //void Mapper192::HSync(INT scanline)
public override void HSync(int scanline) public override void HSync(int scanline)
{ {
if ((scanline >= 0 && scanline <= 239)) if ((scanline >= 0 && scanline <= 239))
{ {
if (nes.ppu.IsDispON()) if (nes.ppu.IsDispON())
{ {
if (irq_enable != 0 && irq_request == 0) if (irq_enable!=0 && irq_request == 0)
{ {
if (scanline == 0) if (scanline == 0)
{ {
if (irq_counter != 0) if (irq_counter!=0)
{ {
irq_counter--; irq_counter--;
} }
} }
if ((irq_counter--) == 0) if ((irq_counter--)==0)
{ {
irq_request = 0xFF; irq_request = 0xFF;
irq_counter = irq_latch; irq_counter = irq_latch;
nes.cpu.SetIRQ(IRQ_MAPPER); nes.cpu.SetIRQ(IRQ_MAPPER);
} }
} }
} }
} }
} }
void SetBank_CPU() void SetBank_CPU()
{ {
@ -298,7 +298,7 @@ namespace VirtualNes.Core
//void Mapper192::LoadState(LPBYTE p) //void Mapper192::LoadState(LPBYTE p)
public override void LoadState(byte[] p) public override void LoadState(byte[] p)
{ {
for (INT i = 0; i < 8; i++) for (byte i = 0; i < 8; i++)
{ {
reg[i] = p[i]; reg[i] = p[i];
} }