2024-08-05 23:16:39 +08:00
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//////////////////////////////////////////////////////////////////////////
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// Mapper015 100-in-1 chip //
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//////////////////////////////////////////////////////////////////////////
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using static VirtualNes.MMU;
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2024-08-16 10:20:00 +08:00
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2024-08-05 23:16:39 +08:00
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namespace VirtualNes.Core
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{
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2024-08-16 10:20:00 +08:00
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public class Mapper015 : Mapper
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{
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2024-08-05 23:16:39 +08:00
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2024-08-16 10:20:00 +08:00
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public Mapper015(NES parent) : base(parent) { }
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2024-08-05 23:16:39 +08:00
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2024-08-16 10:20:00 +08:00
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public override void Reset()
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{
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SetPROM_32K_Bank(0, 1, 2, 3);
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}
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2024-08-05 23:16:39 +08:00
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2024-08-16 10:20:00 +08:00
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//void Mapper015::Write(WORD addr, BYTE data)
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public override void Write(ushort addr, byte data)
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{
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switch (addr)
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{
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case 0x8000:
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if ((data & 0x80) != 0)
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{
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SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 1);
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SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 0);
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SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 3);
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SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 2);
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}
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else
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{
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SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 0);
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SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 1);
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SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 2);
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SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 3);
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}
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if ((data & 0x40) != 0)
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SetVRAM_Mirror(VRAM_HMIRROR);
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else SetVRAM_Mirror(VRAM_VMIRROR);
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break;
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case 0x8001:
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if ((data & 0x80) != 0)
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{
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SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 1);
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SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 0);
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}
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else
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{
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SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 0);
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SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 1);
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}
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break;
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case 0x8002:
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if ((data & 0x80) != 0)
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{
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SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 1);
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SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 1);
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SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 1);
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SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 1);
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}
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else
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{
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SetPROM_8K_Bank(4, (data & 0x3F) * 2 + 0);
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SetPROM_8K_Bank(5, (data & 0x3F) * 2 + 0);
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SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 0);
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SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 0);
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}
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break;
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case 0x8003:
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if ((data & 0x80) != 0)
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{
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SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 1);
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SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 0);
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}
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else
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{
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SetPROM_8K_Bank(6, (data & 0x3F) * 2 + 0);
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SetPROM_8K_Bank(7, (data & 0x3F) * 2 + 1);
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}
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if ((data & 0x40) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
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else SetVRAM_Mirror(VRAM_VMIRROR);
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break;
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}
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}
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2024-08-05 23:16:39 +08:00
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2024-08-16 10:20:00 +08:00
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}
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2024-08-05 23:16:39 +08:00
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}
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