592 lines
14 KiB
C++
592 lines
14 KiB
C++
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static const Mapper172::FDC_CMD_DESC FdcCmdTableJ[32] =
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{
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/* 0x00 */ { 1, 1, Mapper172::FdcNop },
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/* 0x01 */ { 1, 1, Mapper172::FdcNop },
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/* 0x02 */ { 9, 7, Mapper172::FdcReadTrack },
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/* 0x03 */ { 3, 0, Mapper172::FdcSpecify },
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/* 0x04 */ { 2, 1, Mapper172::FdcSenseDriveStatus },
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/* 0x05 */ { 9, 7, Mapper172::FdcWriteData },
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/* 0x06 */ { 9, 7, Mapper172::FdcReadData },
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/* 0x07 */ { 2, 0, Mapper172::FdcRecalibrate },
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/* 0x08 */ { 1, 2, Mapper172::FdcSenseIntStatus },
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/* 0x09 */ { 9, 7, Mapper172::FdcWriteDeletedData },
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/* 0x0A */ { 2, 7, Mapper172::FdcReadID },
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/* 0x0B */ { 1, 1, Mapper172::FdcNop },
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/* 0x0C */ { 9, 7, Mapper172::FdcReadDeletedData },
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/* 0x0D */ { 6, 7, Mapper172::FdcFormatTrack },
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/* 0x0E */ { 1, 1, Mapper172::FdcNop },
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/* 0x0F */ { 3, 0, Mapper172::FdcSeek },
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/* 0x10 */ { 1, 1, Mapper172::FdcNop },
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/* 0x11 */ { 9, 7, Mapper172::FdcScanEqual },
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/* 0x12 */ { 1, 1, Mapper172::FdcNop },
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/* 0x13 */ { 1, 1, Mapper172::FdcNop },
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/* 0x14 */ { 1, 1, Mapper172::FdcNop },
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/* 0x15 */ { 1, 1, Mapper172::FdcNop },
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/* 0x16 */ { 1, 1, Mapper172::FdcNop },
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/* 0x17 */ { 1, 1, Mapper172::FdcNop },
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/* 0x18 */ { 1, 1, Mapper172::FdcNop },
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/* 0x19 */ { 9, 7, Mapper172::FdcScanLowOrEqual },
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/* 0x1A */ { 1, 1, Mapper172::FdcNop },
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/* 0x1B */ { 1, 1, Mapper172::FdcNop },
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/* 0x1C */ { 1, 1, Mapper172::FdcNop },
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/* 0x1D */ { 9, 7, Mapper172::FdcScanHighOrEqual },
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/* 0x1E */ { 1, 1, Mapper172::FdcNop },
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/* 0x1F */ { 1, 1, Mapper172::FdcNop },
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};
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void Mapper172::Reset()
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{
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memcpy( YSRAM, PROM, 0x8000);
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ZEROMEMORY( JDRAM, sizeof(JDRAM) );
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ZEROMEMORY( JSRAM, sizeof(JSRAM) );
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ZEROMEMORY( JCRAM, sizeof(JCRAM) );
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SetPROM_32K_Bank( 0 );
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irq_enable = 0;
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irq_counter = 0;
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WE_SRAM = 0;
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WE_DRAM = 0;
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RE_DRAM = 1;
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reg[0] = 0;
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reg[1] = 0;
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reg[2] = 0;
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reg[3] = 0;
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read_mode = 0;
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read_mode1 = 0;
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write_mode = 0;
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write_mode1 = 0;
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//for FDC code by fanoble
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lpDisk = NULL;
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DISK = NULL;
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if(Load_DiskIMG() != NULL) DISK = Load_DiskIMG();
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pFdcDataPtr = DISK;
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bFdcIrq = FALSE;
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bFdcHwReset = FALSE;
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bFdcSoftReset = FALSE;
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bFdcDmaInt = FALSE;
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nFdcDrvSel = 0;
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nFdcMotor = 0;
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nFdcMainStatus = FDC_MS_RQM;
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nFDCStatus[0] = 0;
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nFDCStatus[1] = 0;
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nFDCStatus[2] = 0;
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nFDCStatus[3] = 0;
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bFdcCycle = 0;
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bFdcPhase = FDC_PH_IDLE;
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nFdcCylinder = 0;
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nFdcHeadAddres = 0;
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nFdcRecord = 0;
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nFdcNumber = 0;
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}
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BYTE Mapper172::ReadLow( WORD addr )
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{
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// if((addr<0x6000)&&(addr!=0x418E)) DEBUGOUT( "ReadLow - addr= %04x ; dat= %03x\n", addr, Mapper::ReadLow( addr ) );
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switch (addr)
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{
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case 0x4188://FDC<44><43>״̬<D7B4>Ĵ<EFBFBD><C4B4><EFBFBD>(STATUS)
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// DEBUGOUT( "Read 0x4188 = %04X\n", nFdcMainStatus );
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return nFdcMainStatus;
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break;
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case 0x4189:
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if(read_mode){
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read_mode1++;
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if(read_mode1==512) read_mode=0;
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reg[2] = *(pFdcDataPtr++);
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return reg[2];
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}
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// DEBUGOUT( "Read 0x4189 = %04X\n", bFdcResults[bFdcCycle] );
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read_mode1 = 0;
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write_mode = 0;
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reg[2] = bFdcResults[bFdcCycle];
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bFdcCycle++;
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if (bFdcCycle == pFdcCmd->bRLength)
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{
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bFdcCycle = 0;
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bFdcPhase = FDC_PH_IDLE;
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nFdcMainStatus &= ~FDC_MS_DATA_IN;
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nFdcMainStatus |= FDC_MS_RQM;
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}
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return reg[2];
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break;
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case 0x418E:
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if (bFdcIrq)
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return 0xC0;
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else
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return 0x00;
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break;
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case 0x41AC:
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//
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break;
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}
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if((addr>=0x6000)&&(WE_SRAM==1)){
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return JSRAM[addr-0x6000];
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}
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if((addr>=0x6000)&&(RE_DRAM==1)){
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// if((addr>=0x6000)){
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return JDRAM[addr-0x6000+(reg[0]*0x8000)];
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}
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if(addr>=0x6000) return CPU_MEM_BANK[addr>>13][addr&0x1FFF];
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return Mapper::ReadLow( addr );
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}
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void Mapper172::WriteLow( WORD addr, BYTE data )
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{
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if((addr>=0x6000)&&(WE_SRAM==1)){
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JSRAM[addr-0x6000] = data;
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}
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if((addr>=0x6000)&&(WE_DRAM==1)){
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// if((addr>=0x6000)){
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JDRAM[addr-0x6000+(reg[1]*0x8000)] = data;
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}
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if(addr>=0x6000) CPU_MEM_BANK[addr>>13][addr&0x1FFF] = data;
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// if((addr<0x6000)&&(addr!=0x418E)) DEBUGOUT( "WriteLow - addr= %04x ; dat= %03x\n", addr, data );
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switch (addr)
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{
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case 0x4180:
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DEBUGOUT( "Write 0x4180 = %04X\n", data );
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//s????xxx: BIOS ROM bankswitch register.
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//Load page xxx (4K) of the BIOS ROM to the page frame at $e000.
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//Also, s might be an enable for SRAM at $6000-$7fff.
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//
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WE_SRAM = data & 0x80;
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SetPROM_4K_Bank(0xE000, data&7);
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// SetPROM_8K_Bank(7, data&7);
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break;
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case 0x4181:
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//P?mmppcc: Game Mode Control.
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//P=1 enables MMC2 CHR-ROM switch
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//values of mm select game mode (00=old game, 01=new game, 10=MMC1, 11=MMC3)
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//values of pp select PRG page size (00=8k, 01=16k, 10=32k, 11=invalid)
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//values of cc select CHR page size (1 << cc KBytes). (same as Bung's doc)
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//
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DEBUGOUT( "Write 0x4181 = %04X\n", data );
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break;
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case 0x4182:
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//Rfffvvii: New game mode PPU Config. (same as Bung's doc)
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//
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DEBUGOUT( "Write 0x4181 = %04X\n", data );
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break;
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case 0x4183:
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//PPPPCCCC: PRG and CHR high address line masks (same as Bung's doc)
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//
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DEBUGOUT( "Write 0x4181 = %04X\n", data );
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break;
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case 0x4185:
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//
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break;
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case 0x4186:
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//Send Parallel data.
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break;
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case 0x4189:
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// DEBUGOUT( "Write 0x4189 = %04X\n", data );
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if(write_mode){
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write_mode1++;
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if(write_mode1==512) write_mode=0;
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*pFdcDataPtr = data;
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pFdcDataPtr++;
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}
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write_mode1 = 0;
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read_mode = 0;
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switch (bFdcPhase)
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{
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case FDC_PH_EXECUTION:
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case FDC_PH_RESULT:
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// ERROR
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break;
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case FDC_PH_IDLE:
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default:
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bFdcCycle = 0;
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bFdcPhase = FDC_PH_COMMAND;
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pFdcCmd = &FdcCmdTableJ[data & FDC_CC_MASK];
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// fall through
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case FDC_PH_COMMAND:
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bFdcCommands[bFdcCycle] = data;
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bFdcCycle++;
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if (bFdcCycle == pFdcCmd->bWLength)
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{
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bFdcPhase = FDC_PH_EXECUTION;
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pFdcCmd->pFun(this);
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if (pFdcCmd->bRLength)
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{
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nFdcMainStatus |= FDC_MS_DATA_IN;
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nFdcMainStatus |= FDC_MS_RQM;
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bFdcPhase = FDC_PH_RESULT;
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if((bFdcCommands[0]&0x0F)==0x06) read_mode = 1;
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if((bFdcCommands[0]&0x0F)==0x05) write_mode = 1;
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}
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else
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{
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bFdcPhase = FDC_PH_IDLE;
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}
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bFdcCycle = 0;
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}
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break;
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}
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break;
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case 0x418A://DCR
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// DEBUGOUT( "Write 0x418A = %04X\n", data );
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data = data;
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break;
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case 0x418B://FDC<44><43><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĵ<EFBFBD><C4B4><EFBFBD>(DOR)(<28><><EFBFBD>ֿ<EFBFBD><D6BF>ƼĴ<C6BC><C4B4><EFBFBD>)
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// DEBUGOUT( "Write 0x418B = %04X\n", data );
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bFdcDmaInt = (data & 8) ? TRUE : FALSE;
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nFdcDrvSel = data & 3;
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nFdcMotor = data >> 4;
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if (data & 4)
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{
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if (bFdcSoftReset)
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{
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FdcSoftReset();
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bFdcSoftReset = FALSE;
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// irq after soft reset
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if (0 == nFdcDrvSel)
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bFdcIrq = TRUE; // Drv A Only
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else
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bFdcIrq = FALSE;
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}
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}
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else
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{
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if (!bFdcSoftReset)
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{
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bFdcSoftReset = TRUE;
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bFdcIrq = FALSE;
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}
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}
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break;
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case 0x418C:
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//
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break;
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case 0x418D:
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data = data&0x03;
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if(data==0) SetVRAM_Mirror( VRAM_VMIRROR );
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else if(data==1) SetVRAM_Mirror( VRAM_HMIRROR );
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else if(data==2) SetVRAM_Mirror( VRAM_MIRROR4L );
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else SetVRAM_Mirror( VRAM_MIRROR4H );
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break;
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case 0x418E:
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//
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break;
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case 0x418F:
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reg[3] = data;
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break;
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case 0x4190:
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//????xxxx: Map 32k DRAM bank (of a possible 512k) to $6000-$DFFF for reading.
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//Reading and writing function independently of each other.
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WE_DRAM = 0;
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RE_DRAM = 1;
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reg[0] = data & 0x0F;
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SetJDRAM_32K_Bank( reg[0] );
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break;
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case 0x4191:
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//????xxxx: Map 32k DRAM bank to $6000-$DFFF for writing.
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WE_DRAM = 1;
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RE_DRAM = 0;
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reg[1] = data & 0x0F;
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SetJDRAM_32K_Bank( reg[1] );
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break;
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case 0x4194:
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//
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break;
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case 0x4198:
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//??xxxxxx: Map 8k DRAM bank to PPU 0x0000.
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SetJCRAM_8K_Bank( data & 0x3F );
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break;
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case 0x42FF:
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//
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break;
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}
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}
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BOOL Mapper172::ReadHigh(WORD addr, LPBYTE pdata)
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{
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if( addr>=0xE000 ) return FALSE;
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if( RE_DRAM == 0 ) return FALSE;
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*pdata = JDRAM[addr-0x6000+(reg[0]*0x8000)];
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return TRUE;
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}
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void Mapper172::Write( WORD addr, BYTE data )
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{
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// if(addr>=0xE000) DEBUGOUT( "Write - addr= %04x ; dat= %03x\n", addr, data );
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if( (addr<0xE000)&&(WE_DRAM==1) ) {
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// if( (addr<0xE000) ) {
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|
|
JDRAM[addr-0x6000+(reg[1]*0x8000)] = data;
|
|||
|
|
}else{
|
|||
|
|
CPU_MEM_BANK[addr>>13][addr&0x1FFF] = data;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void Mapper172::Clock( INT cycles )
|
|||
|
|
{
|
|||
|
|
/* if( irq_enable ) {
|
|||
|
|
if( (irq_counter+=cycles) >= 0x7FFF ) {
|
|||
|
|
// irq_counter = 0x7FFF;
|
|||
|
|
// nes->cpu->IRQ_NotPending();
|
|||
|
|
|
|||
|
|
irq_enable = 0;
|
|||
|
|
// irq_counter &= 0x7FFF;
|
|||
|
|
irq_counter = 0x7FFF;
|
|||
|
|
nes->cpu->SetIRQ( IRQ_MAPPER );
|
|||
|
|
}
|
|||
|
|
}*/
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
void Mapper172::PPU_Latch( WORD addr )
|
|||
|
|
{
|
|||
|
|
if(DirectInput.m_Sw[DIK_PAUSE]){
|
|||
|
|
// nes->Dump_JDRAM();
|
|||
|
|
// nes->Dump_CPULMEM();
|
|||
|
|
// nes->Dump_CPUHMEM();
|
|||
|
|
// nes->Dump_YWRAM();
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
LPBYTE Mapper172::Load_DiskIMG()
|
|||
|
|
{
|
|||
|
|
FILE *fp = NULL;
|
|||
|
|
if( !(lpDisk = (LPBYTE)malloc( 0x168000 )) ) {
|
|||
|
|
throw CApp::GetErrorString( IDS_ERROR_OUTOFMEMORY );
|
|||
|
|
}
|
|||
|
|
if( !(fp = ::fopen( "DrPCJr.img", "rb" )) ) {
|
|||
|
|
LPCSTR szErrStr = CApp::GetErrorString( IDS_ERROR_OPEN );
|
|||
|
|
::wsprintf( szErrorString, szErrStr, "DrPCJr.img" );
|
|||
|
|
throw szErrorString;
|
|||
|
|
}
|
|||
|
|
::fread(lpDisk, 0x168000, 1, fp);
|
|||
|
|
FCLOSE(fp);
|
|||
|
|
return lpDisk;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
//for FDC code by fanoble
|
|||
|
|
void Mapper172::FdcHardReset(void)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcHardReset!!!\n" );
|
|||
|
|
bFdcDmaInt = FALSE;
|
|||
|
|
FdcSoftReset();
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcSoftReset(void)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcSoftReset!!!\n" );
|
|||
|
|
nFdcDrvSel = 0;
|
|||
|
|
nFdcMotor = 0;
|
|||
|
|
nFdcMainStatus = FDC_MS_RQM;
|
|||
|
|
nFDCStatus[0] = 0;
|
|||
|
|
nFDCStatus[1] = 0;
|
|||
|
|
nFDCStatus[2] = 0;
|
|||
|
|
nFDCStatus[3] = 0;
|
|||
|
|
bFdcCycle = 0;
|
|||
|
|
bFdcPhase = FDC_PH_IDLE;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(READ DATA)
|
|||
|
|
void Mapper172::FdcReadData(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcReadData!!!\n" );
|
|||
|
|
BYTE C = thiz->bFdcCommands[2]; //<2F>ŵ<EFBFBD><C5B5><EFBFBD>
|
|||
|
|
BYTE H = thiz->bFdcCommands[3]; //<2F><>ͷ<EFBFBD><CDB7>
|
|||
|
|
BYTE R = thiz->bFdcCommands[4]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
BYTE N = thiz->bFdcCommands[5];
|
|||
|
|
INT LBA = H * 18 + C * 36 + (R - 1);
|
|||
|
|
DEBUGOUT( "C = %04X\n", C );
|
|||
|
|
DEBUGOUT( "H = %04X\n", H );
|
|||
|
|
DEBUGOUT( "R = %04X\n", R );
|
|||
|
|
DEBUGOUT( "N = %04X\n", N );
|
|||
|
|
thiz->pFdcDataPtr = thiz->DISK + LBA * 512;
|
|||
|
|
R++;
|
|||
|
|
if (19 == R)
|
|||
|
|
{
|
|||
|
|
R = 1;
|
|||
|
|
H++;
|
|||
|
|
if (2 == H)
|
|||
|
|
{
|
|||
|
|
C++;
|
|||
|
|
if (80 == C)
|
|||
|
|
C = 0;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
thiz->nFDCStatus[0] = 0;
|
|||
|
|
thiz->bFdcResults[0] = thiz->nFDCStatus[0]; // ST0
|
|||
|
|
thiz->bFdcResults[1] = thiz->nFDCStatus[1]; // ST1
|
|||
|
|
thiz->bFdcResults[2] = thiz->nFDCStatus[2]; // ST2
|
|||
|
|
thiz->bFdcResults[3] = C;
|
|||
|
|
thiz->bFdcResults[4] = H;
|
|||
|
|
thiz->bFdcResults[5] = R;
|
|||
|
|
thiz->bFdcResults[6] = N;
|
|||
|
|
thiz->nFdcCylinder = C;
|
|||
|
|
thiz->nFdcHeadAddres = H;
|
|||
|
|
thiz->nFdcRecord = R;
|
|||
|
|
thiz->nFdcNumber = N;
|
|||
|
|
}
|
|||
|
|
//д<><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(WRITE DATA)
|
|||
|
|
void Mapper172::FdcWriteData(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcWriteData!!!\n" );
|
|||
|
|
BYTE C = thiz->bFdcCommands[2]; //<2F>ŵ<EFBFBD><C5B5><EFBFBD>
|
|||
|
|
BYTE H = thiz->bFdcCommands[3]; //<2F><>ͷ<EFBFBD><CDB7>
|
|||
|
|
BYTE R = thiz->bFdcCommands[4]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
BYTE N = thiz->bFdcCommands[5];
|
|||
|
|
INT LBA = H * 18 + C * 36 + (R - 1);
|
|||
|
|
DEBUGOUT( "C = %04X\n", C );
|
|||
|
|
DEBUGOUT( "H = %04X\n", H );
|
|||
|
|
DEBUGOUT( "R = %04X\n", R );
|
|||
|
|
DEBUGOUT( "N = %04X\n", N );
|
|||
|
|
thiz->pFdcDataPtr = thiz->DISK + LBA * 512;
|
|||
|
|
R++;
|
|||
|
|
if (19 == R)
|
|||
|
|
{
|
|||
|
|
R = 1;
|
|||
|
|
H++;
|
|||
|
|
if (2 == H)
|
|||
|
|
{
|
|||
|
|
C++;
|
|||
|
|
if (80 == C)
|
|||
|
|
C = 0;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
thiz->nFDCStatus[0] = 0;
|
|||
|
|
thiz->bFdcResults[0] = thiz->nFDCStatus[0]; // ST0
|
|||
|
|
thiz->bFdcResults[1] = thiz->nFDCStatus[1]; // ST1
|
|||
|
|
thiz->bFdcResults[2] = thiz->nFDCStatus[2]; // ST2
|
|||
|
|
thiz->bFdcResults[3] = C;
|
|||
|
|
thiz->bFdcResults[4] = H;
|
|||
|
|
thiz->bFdcResults[5] = R;
|
|||
|
|
thiz->bFdcResults[6] = N;
|
|||
|
|
thiz->nFdcCylinder = C;
|
|||
|
|
thiz->nFdcHeadAddres = H;
|
|||
|
|
thiz->nFdcRecord = R;
|
|||
|
|
thiz->nFdcNumber = N;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcNop(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcNop!!!\n" );
|
|||
|
|
thiz->nFDCStatus[0] = FDC_S0_IC1;
|
|||
|
|
thiz->bFdcResults[0] = thiz->nFDCStatus[0];
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcReadTrack(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcReadTrack!!!\n" );
|
|||
|
|
thiz = thiz;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcSpecify(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcSpecify!!!\n" );
|
|||
|
|
thiz = thiz;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcSenseDriveStatus(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcSenseDriveStatus!!!\n" );
|
|||
|
|
thiz->bFdcResults[0] = thiz->nFDCStatus[3];
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcRecalibrate(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcRecalibrate!!!\n" );
|
|||
|
|
thiz->nFdcCylinder = 0; //<2F><>ͷ<EFBFBD>ص<EFBFBD>0<EFBFBD>ŵ<EFBFBD>
|
|||
|
|
thiz->nFDCStatus[0] |= FDC_S0_SE;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcSenseIntStatus(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcSenseIntStatus!!!\n" );
|
|||
|
|
thiz->bFdcResults[0] = thiz->nFDCStatus[0];
|
|||
|
|
thiz->bFdcResults[1] = thiz->nFdcCylinder;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcWriteDeletedData(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcWriteDeletedData!!!\n" );
|
|||
|
|
thiz = thiz;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcReadID(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcReadID!!!\n" );
|
|||
|
|
thiz->nFDCStatus[0] = 0;
|
|||
|
|
thiz->bFdcResults[0] = thiz->nFDCStatus[0];
|
|||
|
|
thiz->bFdcResults[1] = thiz->nFDCStatus[1];
|
|||
|
|
thiz->bFdcResults[2] = thiz->nFDCStatus[2];
|
|||
|
|
thiz->bFdcResults[3] = thiz->nFdcCylinder;
|
|||
|
|
thiz->bFdcResults[4] = thiz->nFdcHeadAddres;
|
|||
|
|
thiz->bFdcResults[5] = thiz->nFdcRecord;
|
|||
|
|
thiz->bFdcResults[6] = thiz->nFdcNumber;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcReadDeletedData(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcReadDeletedData!!!\n" );
|
|||
|
|
thiz = thiz;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcFormatTrack(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcFormatTrack!!!\n" );
|
|||
|
|
BYTE C = thiz->bFdcCommands[2]; //<2F>ŵ<EFBFBD><C5B5><EFBFBD>
|
|||
|
|
BYTE H = thiz->bFdcCommands[3]; //<2F><>ͷ<EFBFBD><CDB7>
|
|||
|
|
BYTE R = thiz->bFdcCommands[4]; //<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
BYTE N = thiz->bFdcCommands[5];
|
|||
|
|
|
|||
|
|
R++;
|
|||
|
|
if (19 == R)
|
|||
|
|
{
|
|||
|
|
R = 1;
|
|||
|
|
H++;
|
|||
|
|
if (2 == H)
|
|||
|
|
{
|
|||
|
|
C++;
|
|||
|
|
if (80 == C)
|
|||
|
|
C = 0;
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
thiz->nFDCStatus[0] = 0;
|
|||
|
|
thiz->bFdcResults[0] = thiz->nFDCStatus[0]; // ST0
|
|||
|
|
thiz->bFdcResults[1] = thiz->nFDCStatus[1]; // ST1
|
|||
|
|
thiz->bFdcResults[2] = thiz->nFDCStatus[2]; // ST2
|
|||
|
|
thiz->bFdcResults[3] = C;
|
|||
|
|
thiz->bFdcResults[4] = H;
|
|||
|
|
thiz->bFdcResults[5] = R;
|
|||
|
|
thiz->bFdcResults[6] = N;
|
|||
|
|
thiz->nFdcCylinder = C;
|
|||
|
|
thiz->nFdcHeadAddres = H;
|
|||
|
|
thiz->nFdcRecord = R;
|
|||
|
|
thiz->nFdcNumber = N;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcSeek(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcSeek!!!\n" );
|
|||
|
|
BYTE US;
|
|||
|
|
US = thiz->bFdcCommands[1] & 3;
|
|||
|
|
thiz->nFdcHeadAddres = ( thiz->bFdcCommands[1] & 7 ) >> 2;
|
|||
|
|
thiz->nFdcCylinder = thiz->bFdcCommands[2];
|
|||
|
|
thiz->nFDCStatus[0] = FDC_S0_SE;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcScanEqual(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcScanEqual!!!\n" );
|
|||
|
|
thiz = thiz;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcScanLowOrEqual(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcScanLowOrEqual!!!\n" );
|
|||
|
|
thiz = thiz;
|
|||
|
|
}
|
|||
|
|
void Mapper172::FdcScanHighOrEqual(Mapper172* thiz)
|
|||
|
|
{
|
|||
|
|
DEBUGOUT( "FdcScanHighOrEqual!!!\n" );
|
|||
|
|
thiz = thiz;
|
|||
|
|
}
|