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AxibugEmuOnline/References/VirtuaNESex_src_191105/NES/MMU.h

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readme + references
2024-08-05 17:58:53 +08:00
//////////////////////////////////////////////////////////////////////////
// //
// NES Memory Management Unit //
// Norix //
// written 2001/02/21 //
// last modify ----/--/-- //
//////////////////////////////////////////////////////////////////////////
#ifndef __MMU_INCLUDED__
#define __MMU_INCLUDED__
#include "typedef.h"
#include "macro.h"
extern BYTE nnn;
// CPU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD>N
extern LPBYTE CPU_MEM_BANK[8]; // 8K<38>P<EFBFBD><50>
extern BYTE CPU_MEM_TYPE[8];
extern INT CPU_MEM_PAGE[8]; // <20>X<EFBFBD>e<EFBFBD>[<5B>g<EFBFBD>Z<EFBFBD>[<5B>u<EFBFBD>p
// PPU <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>o<EFBFBD><6F><EFBFBD>N
extern LPBYTE PPU_MEM_BANK[12]; // 1K<31>P<EFBFBD><50>
extern BYTE PPU_MEM_TYPE[12];
extern INT PPU_MEM_PAGE[12]; // <20>X<EFBFBD>e<EFBFBD>[<5B>g<EFBFBD>Z<EFBFBD>[<5B>u<EFBFBD>p
extern BYTE CRAM_USED[16]; // <20>X<EFBFBD>e<EFBFBD>[<5B>g<EFBFBD>Z<EFBFBD>[<5B>u<EFBFBD>p
extern PBYTE VROM_WRITED; // for mapper 74
// NES<45><53><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
extern BYTE RAM [ 8*1024]; // NES<45><53><EFBFBD><EFBFBD>RAM
extern BYTE WRAM[128*1024]; // <20><><EFBFBD>[<5B>N/<2F>o<EFBFBD>b<EFBFBD>N<EFBFBD>A<EFBFBD>b<EFBFBD>vRAM
extern BYTE DRAM[ 40*1024]; // <20>f<EFBFBD>B<EFBFBD>X<EFBFBD>N<EFBFBD>V<EFBFBD>X<EFBFBD>e<EFBFBD><65>RAM
extern BYTE XRAM[ 8*1024]; // <20>_<EFBFBD>~<7E>[<5B>o<EFBFBD><6F><EFBFBD>N
extern BYTE ERAM[ 32*1024]; // <20>g<EFBFBD><67><EFBFBD>@<40><><EFBFBD>pRAM
extern BYTE VRAM[ 4*1024]; // <20>l<EFBFBD>[<5B><><EFBFBD>e<EFBFBD>[<5B>u<EFBFBD><75>/<2F>A<EFBFBD>g<EFBFBD><67><EFBFBD>r<EFBFBD><72><EFBFBD>[<5B>gRAM
extern BYTE CRAM[ 32*1024]; // <20>L<EFBFBD><4C><EFBFBD><EFBFBD><EFBFBD>N<EFBFBD>^<5E>p<EFBFBD>^<5E>[<5B><>RAM
extern BYTE YWRAM[1024*1024]; // for YuXing 98/F 1024K PRam
extern BYTE YSRAM[ 32*1024]; // for YuXing 98/F 32K SRam
extern BYTE YCRAM[ 128*1024]; // for YuXing 98/F 128K CRam
extern BYTE BDRAM[ 512*1024]; // for BBK 512K PRam
extern BYTE BSRAM[ 32*1024]; // for BBK 32K SRam
extern BYTE BCRAM[ 512*1024]; // for BBK 512K CRam
extern BYTE JDRAM[ 512*1024]; // for DrPCJr 512K PRam
extern BYTE JSRAM[ 8*1024]; // for DrPCJr 8K SRam
extern BYTE JCRAM[ 512*1024]; // for DrPCJr 512K CRam
extern BYTE tempRAM[ 4*1024];
extern BYTE WAVRAM[256];
extern BYTE SPRAM[0x100]; // <20>X<EFBFBD>v<EFBFBD><76><EFBFBD>C<EFBFBD>gRAM
extern BYTE BGPAL[0x10]; // BG<42>p<EFBFBD><70><EFBFBD>b<EFBFBD>g
extern BYTE SPPAL[0x10]; // SP<53>p<EFBFBD><70><EFBFBD>b<EFBFBD>g
// <20><><EFBFBD>W<EFBFBD>X<EFBFBD>^
extern BYTE CPUREG[0x18]; // Nes $4000-$4017
extern BYTE PPUREG[0x04]; // Nes $2000-$2003
// Frame-IRQ<52><51><EFBFBD>W<EFBFBD>X<EFBFBD>^($4017)
extern BYTE FrameIRQ;
// PPU<50><55><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>W<EFBFBD>X<EFBFBD>^
extern BYTE PPU56Toggle; // $2005-$2006 Toggle
extern BYTE PPU7_Temp; // $2007 read buffer
extern WORD loopy_t; // same as $2005/$2006
extern WORD loopy_v; // same as $2005/$2006
extern WORD loopy_x; // tile x offset
// ROM<4F>f<EFBFBD>[<5B>^<5E>|<7C>C<EFBFBD><43><EFBFBD>^
extern LPBYTE PROM; // PROM ptr
extern LPBYTE VROM; // VROM ptr
#ifdef _DATATRACE
// For dis...
extern LPBYTE PROM_ACCESS;
#endif
// ROM <20>o<EFBFBD><6F><EFBFBD>N<EFBFBD>T<EFBFBD>C<EFBFBD>Y
extern INT PROM_8K_SIZE, PROM_16K_SIZE, PROM_32K_SIZE;
extern INT VROM_1K_SIZE, VROM_2K_SIZE, VROM_4K_SIZE, VROM_8K_SIZE;
// <20>֐<EFBFBD>
extern void NesSub_MemoryInitial();
extern void SetPROM_Bank( BYTE page, LPBYTE ptr, BYTE type );
extern void SetPROM_8K_Bank ( BYTE page, INT bank );
extern void SetPROM_16K_Bank( BYTE page, INT bank );
extern void SetPROM_32K_Bank( INT bank );
extern void SetPROM_32K_Bank( INT bank0, INT bank1, INT bank2, INT bank3 );
extern void SetVROM_Bank( BYTE page, LPBYTE ptr, BYTE type );
extern void SetVROM_1K_Bank( BYTE page, INT bank );
extern void SetVROM_2K_Bank( BYTE page, INT bank );
extern void SetVROM_4K_Bank( BYTE page, INT bank );
extern void SetVROM_8K_Bank( INT bank );
extern void SetVROM_8K_Bank( INT bank0, INT bank1, INT bank2, INT bank3,
INT bank4, INT bank5, INT bank6, INT bank7 );
extern void SetCRAM_1K_Bank( BYTE page, INT bank );
extern void SetCRAM_2K_Bank( BYTE page, INT bank );
extern void SetCRAM_4K_Bank( BYTE page, INT bank );
extern void SetCRAM_8K_Bank( INT bank );
extern void SetVRAM_1K_Bank( BYTE page, INT bank );
extern void SetVRAM_Bank( INT bank0, INT bank1, INT bank2, INT bank3 );
extern void SetVRAM_Mirror( INT type );
extern void SetVRAM_Mirror( INT bank0, INT bank1, INT bank2, INT bank3 );
// for YuXing 98/F 1024K PRam
extern void SetYWRAM_8K_Bank ( BYTE page, INT bank );
extern void SetYWRAM_16K_Bank( BYTE page, INT bank );
extern void SetYWRAM_32K_Bank( INT bank );
extern void SetYWRAM_32K_Bank( INT bank0, INT bank1, INT bank2, INT bank3 );
// for YuXing 98/F 128K CRam
extern void SetYCRAM_1K_Bank( BYTE page, INT bank );
extern void SetYCRAM_2K_Bank( BYTE page, INT bank );
extern void SetYCRAM_4K_Bank( BYTE page, INT bank );
extern void SetYCRAM_8K_Bank( INT bank );
extern void SetBDRAM_8K_Bank( BYTE page, INT bank );
extern void SetBDRAM_16K_Bank( BYTE page, INT bank );
extern void SetBDRAM_32K_Bank( INT bank );
extern void SetPROM_4K_Bank( WORD addr, INT bank );
extern void SetJCRAM_1K_Bank( BYTE page, INT bank );
extern void SetJCRAM_2K_Bank( BYTE page, INT bank );
extern void SetJCRAM_4K_Bank( BYTE page, INT bank );
extern void SetJCRAM_8K_Bank( INT bank );
extern void SetJCRAM_8K_Bank( INT bank0, INT bank1, INT bank2, INT bank3,
INT bank4, INT bank5, INT bank6, INT bank7 );
extern void SetJDRAM_8K_Bank ( BYTE page, INT bank );
extern void SetJDRAM_32K_Bank( INT bank );
extern void SetOBCRAM_1K_Bank( BYTE page, INT bank );
// <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>^<5E>C<EFBFBD>v
// For PROM (CPU)
#define BANKTYPE_ROM 0x00
#define BANKTYPE_RAM 0xFF
#define BANKTYPE_DRAM 0x01
#define BANKTYPE_MAPPER 0x80
// For VROM/VRAM/CRAM (PPU)
#define BANKTYPE_VROM 0x00
#define BANKTYPE_CRAM 0x01
#define BANKTYPE_YCRAM 0x02
#define BANKTYPE_JCRAM 0x03
#define BANKTYPE_VRAM 0x80
// <20>~<7E><><EFBFBD>[<5B>^<5E>C<EFBFBD>v
#define VRAM_HMIRROR 0x00 // Horizontal
#define VRAM_VMIRROR 0x01 // Virtical
#define VRAM_MIRROR4 0x02 // All screen
#define VRAM_MIRROR4L 0x03 // PA10 L<>Œ<EFBFBD> $2000-$23FF<46>̃~<7E><><EFBFBD>[
#define VRAM_MIRROR4H 0x04 // PA10 H<>Œ<EFBFBD> $2400-$27FF<46>̃~<7E><><EFBFBD>[
#define VRAM_MIRROR3H 0x05
#endif // !__MMU_INCLUDED__
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