117 lines
2.5 KiB
C
117 lines
2.5 KiB
C
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//////////////////////////////////////////////////////////////////////////
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// //
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// 6502 CPU core //
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// Norix //
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// written 2001/02/22 //
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// last modify ----/--/-- //
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//////////////////////////////////////////////////////////////////////////
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#ifndef __CPU_INCLUDED__
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#define __CPU_INCLUDED__
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#include "typedef.h"
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#include "macro.h"
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class NES;
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class APU;
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class Mapper;
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// 6502 status flags
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#define C_FLAG 0x01 // 1: Carry
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#define Z_FLAG 0x02 // 1: Zero
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#define I_FLAG 0x04 // 1: Irq disabled
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#define D_FLAG 0x08 // 1: Decimal mode flag (NES unused)
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#define B_FLAG 0x10 // 1: Break
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#define R_FLAG 0x20 // 1: Reserved (Always 1)
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#define V_FLAG 0x40 // 1: Overflow
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#define N_FLAG 0x80 // 1: Negative
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// Interrupt
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#define NMI_FLAG 0x01
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#define IRQ_FLAG 0x02
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#define IRQ_FRAMEIRQ 0x04
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#define IRQ_DPCM 0x08
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#define IRQ_MAPPER 0x10
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#define IRQ_MAPPER2 0x20
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#define IRQ_TRIGGER 0x40 // one shot(<28><>IRQ())
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#define IRQ_TRIGGER2 0x80 // one shot(<28><>IRQ_NotPending())
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#define IRQ_MASK (~(NMI_FLAG|IRQ_FLAG))
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// Vector
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#define NMI_VECTOR 0xFFFA
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#define RES_VECTOR 0xFFFC
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#define IRQ_VECTOR 0xFFFE
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// 6502 context
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typedef struct {
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WORD PC; /* Program counter */
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BYTE A; /* CPU registers */
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BYTE P;
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BYTE X;
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BYTE Y;
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BYTE S;
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BYTE INT_pending; // <20><><EFBFBD>荞<EFBFBD>݃y<DD83><79><EFBFBD>f<EFBFBD>B<EFBFBD><42><EFBFBD>O<EFBFBD>t<EFBFBD><74><EFBFBD>O
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} R6502;
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class CPU
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{
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public:
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CPU( NES* parent );
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virtual ~CPU();
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BYTE RD6502( WORD addr );
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void WR6502( WORD addr, BYTE data );
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WORD RD6502W( WORD addr );
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void Reset();
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void NMI();
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void SetIRQ( BYTE mask );
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void ClrIRQ( BYTE mask );
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void DMA( INT cycles );
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INT EXEC( INT request_cycles );
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INT GetDmaCycles();
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void SetDmaCycles( INT cycles );
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INT GetTotalCycles();
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void SetTotalCycles( INT cycles );
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void SetContext( R6502 r ) { R = r; }
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void GetContext( R6502& r ) { r = R; }
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void SetClockProcess( BOOL bEnable ) { m_bClockProcess = bEnable; }
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//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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unsigned char DebugMemCPU (unsigned short Addr);
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int DecodeInstruction (unsigned short Addr, char *str1);
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protected:
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NES* nes;
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APU* apu;
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Mapper* mapper;
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R6502 R;
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INT TOTAL_cycles; // CPU<50>g<EFBFBD>[<5B>^<5E><><EFBFBD>T<EFBFBD>C<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD>
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INT DMA_cycles; // DMA<4D>T<EFBFBD>C<EFBFBD>N<EFBFBD><4E><EFBFBD><EFBFBD>
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// PTR
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LPBYTE STACK;
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// Zero & Negative table
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BYTE ZN_Table[256];
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// Clock process
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BOOL m_bClockProcess;
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private:
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};
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#endif // !__CPU_INCLUDED__
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