284 lines
13 KiB
C++
284 lines
13 KiB
C++
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<EFBFBD><EFBFBD>//////////////////////////////////////////////////////////////////////////
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// //
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// NES Memory Management Unit //
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// Norix //
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// written 2001/02/21 //
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// last modify ----/--/-- //
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//////////////////////////////////////////////////////////////////////////
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#define WIN32_LEAN_AND_MEAN
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#include <windows.h>
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#include "typedef.h"
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#include "macro.h"
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#include "DebugOut.h"
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#include "mmu.h"
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// CPU <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
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LPBYTE CPU_MEM_BANK[8]; // 8KXSMO
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BYTE CPU_MEM_TYPE[8];
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INT CPU_MEM_PAGE[8]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0(u
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// PPU <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
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LPBYTE PPU_MEM_BANK[12]; // 1KXSMO
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BYTE PPU_MEM_TYPE[12];
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INT PPU_MEM_PAGE[12]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0(u
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BYTE CRAM_USED[16]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0(u
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// NES<EFBFBD>0<EFBFBD>0<EFBFBD>0
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BYTE RAM [ 8*1024]; // NES<EFBFBD>QӁRAM
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BYTE WRAM[128*1024]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0/<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0RAM
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BYTE DRAM[ 40*1024]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0RAM
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BYTE XRAM[ 8*1024]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
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BYTE ERAM[ 32*1024]; // <EFBFBD>b5__jhV(uRAM
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BYTE CRAM[ 32*1024]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0RAM
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BYTE VRAM[ 4*1024]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0/<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0RAM
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BYTE SPRAM[0x100]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0RAM
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BYTE BGPAL[0x10]; // BG<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
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BYTE SPPAL[0x10]; // SP<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
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// <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
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BYTE CPUREG[0x18]; // Nes $4000-$4017
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BYTE PPUREG[0x04]; // Nes $2000-$2003
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// Frame-IRQ<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0($4017)
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BYTE FrameIRQ;
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// PPU<EFBFBD>Q<EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
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BYTE PPU56Toggle; // $2005-$2006 Toggle
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BYTE PPU7_Temp; // $2007 read buffer
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WORD loopy_t; // same as $2005/$2006
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WORD loopy_v; // same as $2005/$2006
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WORD loopy_x; // tile x offset
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// ROM<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
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LPBYTE PROM; // PROM ptr
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LPBYTE VROM; // VROM ptr
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// For dis...
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LPBYTE PROM_ACCESS = NULL;
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// ROM <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
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INT PROM_8K_SIZE, PROM_16K_SIZE, PROM_32K_SIZE;
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INT VROM_1K_SIZE, VROM_2K_SIZE, VROM_4K_SIZE, VROM_8K_SIZE;
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//
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// hQ<EFBFBD>0<EFBFBD>0<EFBFBD>0/<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0I{n0RgS
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//
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void NesSub_MemoryInitial()
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{
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INT i;
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// <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
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ZEROMEMORY( RAM, sizeof(RAM) );
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ZEROMEMORY( WRAM, sizeof(WRAM) );
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ZEROMEMORY( DRAM, sizeof(DRAM) );
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ZEROMEMORY( ERAM, sizeof(ERAM) );
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ZEROMEMORY( XRAM, sizeof(XRAM) );
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ZEROMEMORY( CRAM, sizeof(CRAM) );
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ZEROMEMORY( VRAM, sizeof(VRAM) );
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ZEROMEMORY( SPRAM, sizeof(SPRAM) );
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ZEROMEMORY( BGPAL, sizeof(BGPAL) );
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ZEROMEMORY( SPPAL, sizeof(SPPAL) );
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ZEROMEMORY( CPUREG, sizeof(CPUREG) );
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ZEROMEMORY( PPUREG, sizeof(PPUREG) );
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FrameIRQ = 0xC0;
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PROM = VROM = NULL;
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// 0 d<EFBFBD><EFBFBD>{2<EFBFBD>bk<EFBFBD>[V{
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PROM_8K_SIZE = PROM_16K_SIZE = PROM_32K_SIZE = 1;
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VROM_1K_SIZE = VROM_2K_SIZE = VROM_4K_SIZE = VROM_8K_SIZE = 1;
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// <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0-<EFBFBD><EFBFBD>[
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for( i = 0; i < 8; i++ ) {
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CPU_MEM_BANK[i] = NULL;
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CPU_MEM_TYPE[i] = BANKTYPE_ROM;
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CPU_MEM_PAGE[i] = 0;
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}
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// <EFBFBD>QӁRAM/WRAM
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SetPROM_Bank( 0, RAM, BANKTYPE_RAM );
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SetPROM_Bank( 3, WRAM, BANKTYPE_RAM );
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// <EFBFBD>0<EFBFBD>0<EFBFBD>0
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SetPROM_Bank( 1, XRAM, BANKTYPE_ROM );
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SetPROM_Bank( 2, XRAM, BANKTYPE_ROM );
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for( i = 0; i < 8; i++ ) {
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CRAM_USED[i] = 0;
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}
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// PPU VROM<EFBFBD>0<EFBFBD>0<EFBFBD>0-<EFBFBD><EFBFBD>[
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// SetVRAM_Mirror( VRAM_MIRROR4 );
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}
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// CPU ROM bank
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void SetPROM_Bank( BYTE page, LPBYTE ptr, BYTE type )
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{
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CPU_MEM_BANK[page] = ptr;
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CPU_MEM_TYPE[page] = type;
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CPU_MEM_PAGE[page] = 0;
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}
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void SetPROM_8K_Bank( BYTE page, INT bank )
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{
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bank %= PROM_8K_SIZE;
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CPU_MEM_BANK[page] = PROM+0x2000*bank;
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CPU_MEM_TYPE[page] = BANKTYPE_ROM;
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CPU_MEM_PAGE[page] = bank;
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}
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void SetPROM_16K_Bank( BYTE page, INT bank )
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{
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SetPROM_8K_Bank( page+0, bank*2+0 );
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SetPROM_8K_Bank( page+1, bank*2+1 );
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}
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void SetPROM_32K_Bank( INT bank )
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{
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SetPROM_8K_Bank( 4, bank*4+0 );
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SetPROM_8K_Bank( 5, bank*4+1 );
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SetPROM_8K_Bank( 6, bank*4+2 );
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SetPROM_8K_Bank( 7, bank*4+3 );
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}
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void SetPROM_32K_Bank( INT bank0, INT bank1, INT bank2, INT bank3 )
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{
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SetPROM_8K_Bank( 4, bank0 );
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SetPROM_8K_Bank( 5, bank1 );
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SetPROM_8K_Bank( 6, bank2 );
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SetPROM_8K_Bank( 7, bank3 );
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}
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// PPU VROM bank
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void SetVROM_Bank( BYTE page, LPBYTE ptr, BYTE type )
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{
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PPU_MEM_BANK[page] = ptr;
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PPU_MEM_TYPE[page] = type;
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PPU_MEM_PAGE[page] = 0;
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}
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void SetVROM_1K_Bank( BYTE page, INT bank )
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{
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bank %= VROM_1K_SIZE;
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PPU_MEM_BANK[page] = VROM+0x0400*bank;
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PPU_MEM_TYPE[page] = BANKTYPE_VROM;
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PPU_MEM_PAGE[page] = bank;
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}
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void SetVROM_2K_Bank( BYTE page, INT bank )
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{
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SetVROM_1K_Bank( page+0, bank*2+0 );
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SetVROM_1K_Bank( page+1, bank*2+1 );
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}
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void SetVROM_4K_Bank( BYTE page, INT bank )
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{
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SetVROM_1K_Bank( page+0, bank*4+0 );
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SetVROM_1K_Bank( page+1, bank*4+1 );
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SetVROM_1K_Bank( page+2, bank*4+2 );
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SetVROM_1K_Bank( page+3, bank*4+3 );
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}
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void SetVROM_8K_Bank( INT bank )
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{
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for( INT i = 0; i < 8; i++ ) {
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SetVROM_1K_Bank( i, bank*8+i );
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}
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}
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void SetVROM_8K_Bank( INT bank0, INT bank1, INT bank2, INT bank3,
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INT bank4, INT bank5, INT bank6, INT bank7 )
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{
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SetVROM_1K_Bank( 0, bank0 );
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SetVROM_1K_Bank( 1, bank1 );
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SetVROM_1K_Bank( 2, bank2 );
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SetVROM_1K_Bank( 3, bank3 );
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SetVROM_1K_Bank( 4, bank4 );
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SetVROM_1K_Bank( 5, bank5 );
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SetVROM_1K_Bank( 6, bank6 );
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SetVROM_1K_Bank( 7, bank7 );
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}
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void SetCRAM_1K_Bank( BYTE page, INT bank )
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{
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bank &= 0x1F;
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PPU_MEM_BANK[page] = CRAM+0x0400*bank;
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PPU_MEM_TYPE[page] = BANKTYPE_CRAM;
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PPU_MEM_PAGE[page] = bank;
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CRAM_USED[bank>>2] = 0xFF; // CRAMO(u<EFBFBD>0<EFBFBD>0<EFBFBD>0
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}
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void SetCRAM_2K_Bank( BYTE page, INT bank )
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{
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SetCRAM_1K_Bank( page+0, bank*2+0 );
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SetCRAM_1K_Bank( page+1, bank*2+1 );
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}
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void SetCRAM_4K_Bank( BYTE page, INT bank )
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{
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SetCRAM_1K_Bank( page+0, bank*4+0 );
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SetCRAM_1K_Bank( page+1, bank*4+1 );
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SetCRAM_1K_Bank( page+2, bank*4+2 );
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SetCRAM_1K_Bank( page+3, bank*4+3 );
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}
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void SetCRAM_8K_Bank( INT bank )
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{
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for( INT i = 0; i < 8; i++ ) {
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SetCRAM_1K_Bank( i, bank*8+i ); // fix
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}
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}
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void SetVRAM_1K_Bank( BYTE page, INT bank )
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{
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bank &= 3;
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PPU_MEM_BANK[page] = VRAM+0x0400*bank;
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PPU_MEM_TYPE[page] = BANKTYPE_VRAM;
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PPU_MEM_PAGE[page] = bank;
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}
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void SetVRAM_Bank( INT bank0, INT bank1, INT bank2, INT bank3 )
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{
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SetVRAM_1K_Bank( 8, bank0 );
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SetVRAM_1K_Bank( 9, bank1 );
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SetVRAM_1K_Bank( 10, bank2 );
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SetVRAM_1K_Bank( 11, bank3 );
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}
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void SetVRAM_Mirror( INT type )
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{
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switch( type ) {
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case VRAM_HMIRROR:
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SetVRAM_Bank( 0, 0, 1, 1 );
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break;
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case VRAM_VMIRROR:
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SetVRAM_Bank( 0, 1, 0, 1 );
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break;
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case VRAM_MIRROR4L:
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SetVRAM_Bank( 0, 0, 0, 0 );
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break;
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case VRAM_MIRROR4H:
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SetVRAM_Bank( 1, 1, 1, 1 );
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break;
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case VRAM_MIRROR4:
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SetVRAM_Bank( 0, 1, 2, 3 );
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break;
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}
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}
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void SetVRAM_Mirror( INT bank0, INT bank1, INT bank2, INT bank3 )
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{
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SetVRAM_1K_Bank( 8, bank0 );
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SetVRAM_1K_Bank( 9, bank1 );
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SetVRAM_1K_Bank( 10, bank2 );
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SetVRAM_1K_Bank( 11, bank3 );
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}
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