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transfer Mapper 200-255.cs

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sin365 2024-08-03 22:26:53 +08:00
parent c465f1a66e
commit f924708dd2
60 changed files with 3564 additions and 0 deletions
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48
AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper200.cs Normal file
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//////////////////////////////////////////////
// Mapper200 1200-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper200 : Mapper
{
public Mapper200(NES parent) : base(parent)
{
}
public override void Reset()
{
// SetPROM_32K_Bank( 0, 1, PROM_8K_SIZE-2, PROM_8K_SIZE-1 );
SetPROM_16K_Bank(4, 0);
SetPROM_16K_Bank(6, 0);
if (VROM_1K_SIZE != 0)
{
SetVROM_8K_Bank(0);
}
}
//void Mapper200::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
SetPROM_16K_Bank(4, addr & 0x07);
SetPROM_16K_Bank(6, addr & 0x07);
SetVROM_8K_Bank(addr & 0x07);
if ((addr & 0x01) != 0)
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper201.cs Normal file
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//////////////////////////////////////////////////////////////////////////
// Mapper201 21-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper201 : Mapper
{
public Mapper201(NES parent) : base(parent)
{
}
public override void Reset()
{
// SetPROM_32K_Bank( 0, 1, PROM_8K_SIZE-2, PROM_8K_SIZE-1 );
SetPROM_16K_Bank(4, 0);
SetPROM_16K_Bank(6, 0);
if (VROM_1K_SIZE != 0)
{
SetVROM_8K_Bank(0);
}
}
//void Mapper201::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
BYTE bank = (byte)((BYTE)addr & 0x03);
if (!((addr & 0x08) != 0))
bank = 0;
SetPROM_32K_Bank(bank);
SetVROM_8K_Bank(bank);
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper201.cs.meta Normal file
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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper202.cs Normal file
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//////////////////////////////////////////////////////////////////////////
// Mapper202 150-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper202 : Mapper
{
public Mapper202(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_16K_Bank(4, 6);
SetPROM_16K_Bank(6, 7);
if (VROM_1K_SIZE != 0)
{
SetVROM_8K_Bank(0);
}
}
//void Mapper202::ExWrite(WORD addr, BYTE data)
public override void ExWrite(ushort addr, byte data)
{
if (addr >= 0x4020)
{
WriteSub(addr, data);
}
}
//void Mapper202::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data)
{
WriteSub(addr, data);
}
//void Mapper202::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
WriteSub(addr, data);
}
void WriteSub(ushort addr, BYTE data)
{
INT bank = (addr >> 1) & 0x07;
SetPROM_16K_Bank(4, bank);
if ((addr & 0x0C) == 0x0C)
{
SetPROM_16K_Bank(6, bank + 1);
}
else
{
SetPROM_16K_Bank(6, bank);
}
SetVROM_8K_Bank(bank);
if ((addr & 0x01) != 0)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper222.cs Normal file
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//////////////////////////////////////////////////////////////////////////
// Mapper222 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper222 : Mapper
{
public Mapper222(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0)
{
SetVROM_8K_Bank(0);
}
SetVRAM_Mirror(VRAM_VMIRROR);
}
//void Mapper222::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
switch (addr & 0xF003)
{
case 0x8000:
SetPROM_8K_Bank(4, data);
break;
case 0xA000:
SetPROM_8K_Bank(5, data);
break;
case 0xB000:
SetVROM_1K_Bank(0, data);
break;
case 0xB002:
SetVROM_1K_Bank(1, data);
break;
case 0xC000:
SetVROM_1K_Bank(2, data);
break;
case 0xC002:
SetVROM_1K_Bank(3, data);
break;
case 0xD000:
SetVROM_1K_Bank(4, data);
break;
case 0xD002:
SetVROM_1K_Bank(5, data);
break;
case 0xE000:
SetVROM_1K_Bank(6, data);
break;
case 0xE002:
SetVROM_1K_Bank(7, data);
break;
}
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper225.cs Normal file
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//////////////////////////////////////////////////////////////////////////
// Mapper225 72-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper225 : Mapper
{
public Mapper225(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0, 1, 2, 3);
if (VROM_1K_SIZE)
{
SetVROM_8K_Bank(0);
}
}
//void Mapper225::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
BYTE prg_bank = (byte)((addr & 0x0F80) >> 7);
BYTE chr_bank = (byte)(addr & 0x003F);
SetVROM_1K_Bank(0, (chr_bank * 8 + 0));
SetVROM_1K_Bank(1, (chr_bank * 8 + 1));
SetVROM_1K_Bank(2, (chr_bank * 8 + 2));
SetVROM_1K_Bank(3, (chr_bank * 8 + 3));
SetVROM_1K_Bank(4, (chr_bank * 8 + 4));
SetVROM_1K_Bank(5, (chr_bank * 8 + 5));
SetVROM_1K_Bank(6, (chr_bank * 8 + 6));
SetVROM_1K_Bank(7, (chr_bank * 8 + 7));
if ((addr & 0x2000) != 0)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
if ((addr & 0x1000) != 0)
{
// 16KBbank
if ((addr & 0x0040) != 0)
{
SetPROM_8K_Bank(4, (prg_bank * 4 + 2));
SetPROM_8K_Bank(5, (prg_bank * 4 + 3));
SetPROM_8K_Bank(6, (prg_bank * 4 + 2));
SetPROM_8K_Bank(7, (prg_bank * 4 + 3));
}
else
{
SetPROM_8K_Bank(4, (prg_bank * 4 + 0));
SetPROM_8K_Bank(5, (prg_bank * 4 + 1));
SetPROM_8K_Bank(6, (prg_bank * 4 + 0));
SetPROM_8K_Bank(7, (prg_bank * 4 + 1));
}
}
else
{
SetPROM_8K_Bank(4, (prg_bank * 4 + 0));
SetPROM_8K_Bank(5, (prg_bank * 4 + 1));
SetPROM_8K_Bank(6, (prg_bank * 4 + 2));
SetPROM_8K_Bank(7, (prg_bank * 4 + 3));
}
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper226.cs Normal file
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//////////////////////////////////////////////////////////////////////////
// Mapper226 76-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper226 : Mapper
{
BYTE[] reg = new byte[2];
public Mapper226(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0);
reg[0] = 0;
reg[1] = 0;
}
//void Mapper226::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
if ((addr & 0x001) != 0)
{
reg[1] = data;
}
else
{
reg[0] = data;
}
if ((reg[0] & 0x40) != 0)
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
BYTE bank = (byte)(((reg[0] & 0x1E) >> 1) | ((reg[0] & 0x80) >> 3) | ((reg[1] & 0x01) << 5));
if ((reg[0] & 0x20) != 0)
{
if ((reg[0] & 0x01) != 0)
{
SetPROM_8K_Bank(4, bank * 4 + 2);
SetPROM_8K_Bank(5, bank * 4 + 3);
SetPROM_8K_Bank(6, bank * 4 + 2);
SetPROM_8K_Bank(7, bank * 4 + 3);
}
else
{
SetPROM_8K_Bank(4, bank * 4 + 0);
SetPROM_8K_Bank(5, bank * 4 + 1);
SetPROM_8K_Bank(6, bank * 4 + 0);
SetPROM_8K_Bank(7, bank * 4 + 1);
}
}
else
{
SetPROM_8K_Bank(4, bank * 4 + 0);
SetPROM_8K_Bank(5, bank * 4 + 1);
SetPROM_8K_Bank(6, bank * 4 + 2);
SetPROM_8K_Bank(7, bank * 4 + 3);
}
}
public override bool IsStateSave()
{
return true;
}
//void Mapper226::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
p[0] = reg[0];
p[1] = reg[1];
}
//void Mapper226::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
reg[0] = p[0];
reg[1] = p[1];
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper226.cs.meta Normal file
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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper227.cs Normal file
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//////////////////////////////////////////////////////////////////////////
// Mapper227 1200-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper227 : Mapper
{
public Mapper227(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0, 1, 0, 1);
}
//void Mapper227::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
BYTE bank = (byte)(((addr & 0x0100) >> 4) | ((addr & 0x0078) >> 3));
if ((addr & 0x0001) != 0)
{
SetPROM_32K_Bank(bank);
}
else
{
if ((addr & 0x0004) != 0)
{
SetPROM_8K_Bank(4, bank * 4 + 2);
SetPROM_8K_Bank(5, bank * 4 + 3);
SetPROM_8K_Bank(6, bank * 4 + 2);
SetPROM_8K_Bank(7, bank * 4 + 3);
}
else
{
SetPROM_8K_Bank(4, bank * 4 + 0);
SetPROM_8K_Bank(5, bank * 4 + 1);
SetPROM_8K_Bank(6, bank * 4 + 0);
SetPROM_8K_Bank(7, bank * 4 + 1);
}
}
if (!((addr & 0x0080) != 0))
{
if ((addr & 0x0200) != 0)
{
SetPROM_8K_Bank(6, (bank & 0x1C) * 4 + 14);
SetPROM_8K_Bank(7, (bank & 0x1C) * 4 + 15);
}
else
{
SetPROM_8K_Bank(6, (bank & 0x1C) * 4 + 0);
SetPROM_8K_Bank(7, (bank & 0x1C) * 4 + 1);
}
}
if ((addr & 0x0002) != 0)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper228.cs Normal file
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//////////////////////////////////////////////////////////////////////////
// Mapper228 Action 52 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper228 : Mapper
{
public Mapper228(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0);
SetVROM_8K_Bank(0);
}
//void Mapper228::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
BYTE prg = (byte)((addr & 0x0780) >> 7);
switch ((addr & 0x1800) >> 11)
{
case 1:
prg |= 0x10;
break;
case 3:
prg |= 0x20;
break;
}
if ((addr & 0x0020) != 0)
{
prg <<= 1;
if ((addr & 0x0040) != 0)
{
prg++;
}
SetPROM_8K_Bank(4, prg * 4 + 0);
SetPROM_8K_Bank(5, prg * 4 + 1);
SetPROM_8K_Bank(6, prg * 4 + 0);
SetPROM_8K_Bank(7, prg * 4 + 1);
}
else
{
SetPROM_8K_Bank(4, prg * 4 + 0);
SetPROM_8K_Bank(5, prg * 4 + 1);
SetPROM_8K_Bank(6, prg * 4 + 2);
SetPROM_8K_Bank(7, prg * 4 + 3);
}
SetVROM_8K_Bank(((addr & 0x000F) << 2) | (data & 0x03));
if ((addr & 0x2000) != 0)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper229.cs Normal file
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//////////////////////////////////////////////////////////////////////////
// Mapper229 31-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper229 : Mapper
{
public Mapper229(NES parent) : base(parent)
{
}
public override void Read(ushort addr, byte data)
{
SetPROM_32K_Bank(0);
SetVROM_8K_Bank(0);
}
//void Mapper229::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
if ((addr & 0x001E) != 0)
{
BYTE prg = (byte)(addr & 0x001F);
SetPROM_8K_Bank(4, prg * 2 + 0);
SetPROM_8K_Bank(5, prg * 2 + 1);
SetPROM_8K_Bank(6, prg * 2 + 0);
SetPROM_8K_Bank(7, prg * 2 + 1);
SetVROM_8K_Bank(addr & 0x0FFF);
}
else
{
SetPROM_32K_Bank(0);
SetVROM_8K_Bank(0);
}
if ((addr & 0x0020) != 0)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper230.cs Normal file
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//////////////////////////////////////////////////////////////////////////
// Mapper230 22-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper230 : Mapper
{
BYTE rom_sw;
public Mapper230(NES parent) : base(parent)
{
}
public override void Reset()
{
if (rom_sw != 0)
{
rom_sw = 0;
}
else
{
rom_sw = 1;
}
if (rom_sw != 0)
{
SetPROM_32K_Bank(0, 1, 14, 15);
}
else
{
SetPROM_32K_Bank(16, 17, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
}
}
//void Mapper230::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
if (rom_sw != 0)
{
SetPROM_8K_Bank(4, (data & 0x07) * 2 + 0);
SetPROM_8K_Bank(5, (data & 0x07) * 2 + 1);
}
else
{
if ((data & 0x20) != 0)
{
SetPROM_8K_Bank(4, (data & 0x1F) * 2 + 16);
SetPROM_8K_Bank(5, (data & 0x1F) * 2 + 17);
SetPROM_8K_Bank(6, (data & 0x1F) * 2 + 16);
SetPROM_8K_Bank(7, (data & 0x1F) * 2 + 17);
}
else
{
SetPROM_8K_Bank(4, (data & 0x1E) * 2 + 16);
SetPROM_8K_Bank(5, (data & 0x1E) * 2 + 17);
SetPROM_8K_Bank(6, (data & 0x1E) * 2 + 18);
SetPROM_8K_Bank(7, (data & 0x1E) * 2 + 19);
}
if ((data & 0x40) != 0)
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
}
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/Mapper231.cs Normal file
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//////////////////////////////////////////////////////////////////////////
// Mapper231 20-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper231 : Mapper
{
public Mapper231(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0);
if (VROM_1K_SIZE != 0)
{
SetVROM_8K_Bank(0);
}
}
//void Mapper231::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
if ((addr & 0x0020) != 0)
{
SetPROM_32K_Bank((BYTE)(addr >> 1));
}
else
{
BYTE bank = (byte)(addr & 0x1E);
SetPROM_8K_Bank(4, bank * 2 + 0);
SetPROM_8K_Bank(5, bank * 2 + 1);
SetPROM_8K_Bank(6, bank * 2 + 0);
SetPROM_8K_Bank(7, bank * 2 + 1);
}
if ((addr & 0x0080) != 0)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
}
}
}

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//////////////////////////////////////////////////////////////////////////
// Mapper232 Quattro Games //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper232 : Mapper
{
BYTE[] reg = new byte[2];
public Mapper232(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
reg[0] = 0x0C;
reg[1] = 0x00;
}
//void Mapper232::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data)
{
if (addr >= 0x6000)
{
Write(addr, data);
}
}
//void Mapper232::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
// if( addr == 0x9000 ) {
// reg[0] = (data & 0x18)>>1;
// } else if( addr >= 0xA000 && addr <= 0xFFFF ) {
// reg[1] = data & 0x03;
// }
if (addr <= 0x9FFF)
{
reg[0] = (byte)((data & 0x18) >> 1);
}
else
{
reg[1] = (byte)(data & 0x03);
}
SetPROM_8K_Bank(4, (reg[0] | reg[1]) * 2 + 0);
SetPROM_8K_Bank(5, (reg[0] | reg[1]) * 2 + 1);
SetPROM_8K_Bank(6, (reg[0] | 0x03) * 2 + 0);
SetPROM_8K_Bank(7, (reg[0] | 0x03) * 2 + 1);
}
public override bool IsStateSave()
{
return true;
}
//void Mapper232::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
p[0] = reg[0];
p[1] = reg[1];
}
//void Mapper232::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
reg[0] = p[0];
reg[1] = p[1];
}
}
}

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//////////////////////////////////////////////////////////////////////////
// Mapper233 42-in-1 //
//////////////////////////////////////////////////////////////////////////using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using static VirtualNes.MMU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
namespace VirtualNes.Core
{
public class Mapper233 : Mapper
{
public Mapper233(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0, 1, 2, 3);
}
//void Mapper233::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
if ((data & 0x20) != 0)
{
SetPROM_8K_Bank(4, (data & 0x1F) * 2 + 0);
SetPROM_8K_Bank(5, (data & 0x1F) * 2 + 1);
SetPROM_8K_Bank(6, (data & 0x1F) * 2 + 0);
SetPROM_8K_Bank(7, (data & 0x1F) * 2 + 1);
}
else
{
BYTE bank = (byte)((data & 0x1E) >> 1);
SetPROM_8K_Bank(4, bank * 4 + 0);
SetPROM_8K_Bank(5, bank * 4 + 1);
SetPROM_8K_Bank(6, bank * 4 + 2);
SetPROM_8K_Bank(7, bank * 4 + 3);
}
if ((data & 0xC0) == 0x00)
{
SetVRAM_Mirror(0, 0, 0, 1);
}
else if ((data & 0xC0) == 0x40)
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
else if ((data & 0xC0) == 0x80)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_MIRROR4H);
}
}
}
}

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//////////////////////////////////////////////////////////////////////////
// Mapper234 Maxi-15 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper234 : Mapper
{
BYTE[] reg = new byte[2];
public Mapper234(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0, 1, 2, 3);
reg[0] = 0;
reg[1] = 0;
}
//void Mapper234::Read(WORD addr, BYTE data)
public override void Read(ushort addr, byte data)
{
if (addr >= 0xFF80 && addr <= 0xFF9F)
{
if (reg[0] != 0)
{
reg[0] = data;
SetBank();
}
}
if (addr >= 0xFFE8 && addr <= 0xFFF7)
{
reg[1] = data;
SetBank();
}
}
//void Mapper234::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
if (addr >= 0xFF80 && addr <= 0xFF9F)
{
if (reg[0] == 0)
{
reg[0] = data;
SetBank();
}
}
if (addr >= 0xFFE8 && addr <= 0xFFF7)
{
reg[1] = data;
SetBank();
}
}
void SetBank()
{
if ((reg[0] & 0x80) != 0)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
if ((reg[0] & 0x40) != 0)
{
SetPROM_32K_Bank((reg[0] & 0x0E) | (reg[1] & 0x01));
SetVROM_8K_Bank(((reg[0] & 0x0E) << 2) | ((reg[1] >> 4) & 0x07));
}
else
{
SetPROM_32K_Bank(reg[0] & 0x0F);
SetVROM_8K_Bank(((reg[0] & 0x0F) << 2) | ((reg[1] >> 4) & 0x03));
}
}
public override bool IsStateSave()
{
return true;
}
//void Mapper234::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
p[0] = reg[0];
p[1] = reg[1];
}
//void Mapper234::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
reg[0] = p[0];
reg[1] = p[1];
}
}
}

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//////////////////////////////////////////////////////////////////////////
// Mapper235 150-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper235 : Mapper
{
public Mapper235(NES parent) : base(parent)
{
}
public override void Reset()
{
for (INT i = 0; i < 0x2000; i++)
{
DRAM[i] = 0xFF;
}
SetPROM_32K_Bank(0);
}
//void Mapper235::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
{
BYTE prg = (byte)(((addr & 0x0300) >> 3) | (addr & 0x001F));
BYTE bus = 0;
if (PROM_8K_SIZE == 64 * 2)
{
// 100-in-1
switch (addr & 0x0300)
{
case 0x0000: break;
case 0x0100: bus = 1; break;
case 0x0200: bus = 1; break;
case 0x0300: bus = 1; break;
}
}
else if (PROM_8K_SIZE == 128 * 2)
{
// 150-in-1
switch (addr & 0x0300)
{
case 0x0000: break;
case 0x0100: bus = 1; break;
case 0x0200: prg = (byte)((prg & 0x1F) | 0x20); break;
case 0x0300: bus = 1; break;
}
}
else if (PROM_8K_SIZE == 192 * 2)
{
// 150-in-1
switch (addr & 0x0300)
{
case 0x0000: break;
case 0x0100: bus = 1; break;
case 0x0200: prg = (byte)((prg & 0x1F) | 0x20); break;
case 0x0300: prg = (byte)((prg & 0x1F) | 0x40); break;
}
}
else if (PROM_8K_SIZE == 256 * 2)
{
}
if ((addr & 0x0800) != 0)
{
if ((addr & 0x1000) != 0)
{
SetPROM_8K_Bank(4, prg * 4 + 2);
SetPROM_8K_Bank(5, prg * 4 + 3);
SetPROM_8K_Bank(6, prg * 4 + 2);
SetPROM_8K_Bank(7, prg * 4 + 3);
}
else
{
SetPROM_8K_Bank(4, prg * 4 + 0);
SetPROM_8K_Bank(5, prg * 4 + 1);
SetPROM_8K_Bank(6, prg * 4 + 0);
SetPROM_8K_Bank(7, prg * 4 + 1);
}
}
else
{
SetPROM_32K_Bank(prg);
}
if (bus != 0)
{
SetPROM_Bank(4, DRAM, BANKTYPE_ROM);
SetPROM_Bank(5, DRAM, BANKTYPE_ROM);
SetPROM_Bank(6, DRAM, BANKTYPE_ROM);
SetPROM_Bank(7, DRAM, BANKTYPE_ROM);
}
if ((addr & 0x0400) != 0)
{
SetVRAM_Mirror(VRAM_MIRROR4L);
}
else if ((addr & 0x2000) != 0)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
}
}
}
}

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//////////////////////////////////////////////////////////////////////////
// Mapper236 800-in-1 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper236 : Mapper
{
BYTE bank, mode;
public Mapper236(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
bank = mode = 0;
}
//void Mapper236::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
if (addr >= 0x8000 && addr <= 0xBFFF)
{
bank = (byte)(((addr & 0x03) << 4) | (bank & 0x07));
}
else
{
bank = (byte)((addr & 0x07) | (bank & 0x30));
mode = (byte)(addr & 0x30);
}
if ((addr & 0x20) != 0)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
switch (mode)
{
case 0x00:
bank |= 0x08;
SetPROM_8K_Bank(4, bank * 2 + 0);
SetPROM_8K_Bank(5, bank * 2 + 1);
SetPROM_8K_Bank(6, (bank | 0x07) * 2 + 0);
SetPROM_8K_Bank(7, (bank | 0x07) * 2 + 1);
break;
case 0x10:
bank |= 0x37;
SetPROM_8K_Bank(4, bank * 2 + 0);
SetPROM_8K_Bank(5, bank * 2 + 1);
SetPROM_8K_Bank(6, (bank | 0x07) * 2 + 0);
SetPROM_8K_Bank(7, (bank | 0x07) * 2 + 1);
break;
case 0x20:
bank |= 0x08;
SetPROM_8K_Bank(4, (bank & 0xFE) * 2 + 0);
SetPROM_8K_Bank(5, (bank & 0xFE) * 2 + 1);
SetPROM_8K_Bank(6, (bank & 0xFE) * 2 + 2);
SetPROM_8K_Bank(7, (bank & 0xFE) * 2 + 3);
break;
case 0x30:
bank |= 0x08;
SetPROM_8K_Bank(4, bank * 2 + 0);
SetPROM_8K_Bank(5, bank * 2 + 1);
SetPROM_8K_Bank(6, bank * 2 + 0);
SetPROM_8K_Bank(7, bank * 2 + 1);
break;
}
}
//void Mapper236::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
p[0] = bank;
p[1] = mode;
}
//void Mapper236::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
bank = p[0];
mode = p[1];
}
}
}

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//////////////////////////////
// Mapper240 Gen Ke Le Zhuan //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper240 : Mapper
{
public Mapper240(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0)
{
SetVROM_8K_Bank(0);
}
}
//void Mapper240::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data)
{
if (addr >= 0x4020 && addr < 0x6000)
{
SetPROM_32K_Bank((data & 0xF0) >> 4);
SetVROM_8K_Bank(data & 0xF);
}
}
}
}

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//////////////////////////////////////////////////////////////////////////
// Mapper241 Fon Serm Bon //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper241 : Mapper
{
public Mapper241(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0);
if (VROM_1K_SIZE != 0)
{
SetVROM_8K_Bank(0);
}
}
//void Mapper241::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
if (addr == 0x8000)
{
SetPROM_32K_Bank(data);
}
}
}
}

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//////////////////////////////////////////////////////////////////////////
// Mapper242 Wai Xing Zhan Shi //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper242 : Mapper
{
public Mapper242(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0);
}
//void Mapper242::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
if ((addr & 0x01) != 0)
{
SetPROM_32K_Bank((addr & 0xF8) >> 3);
}
}
}
}

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//////////////////////////////////////////////////////////////////////////
// Mapper243 PC-Sachen/Hacker //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper243 : Mapper
{
BYTE[] reg = new byte[4];
public Mapper243(NES parent) : base(parent)
{
}
//void Mapper243::Reset()
public override void Reset()
{
SetPROM_32K_Bank(0);
if (VROM_8K_SIZE > 4)
{
SetVROM_8K_Bank(4);
}
else if (VROM_8K_SIZE != 0)
{
SetVROM_8K_Bank(0);
}
SetVRAM_Mirror(VRAM_HMIRROR);
reg[0] = 0;
reg[1] = 0;
reg[2] = 3;
reg[3] = 0;
}
//void Mapper243::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data)
{
if ((addr & 0x4101) == 0x4100)
{
reg[0] = data;
}
else if ((addr & 0x4101) == 0x4101)
{
switch (reg[0] & 0x07)
{
case 0:
reg[1] = 0;
reg[2] = 3;
break;
case 4:
reg[2] = (byte)((reg[2] & 0x06) | (data & 0x01));
break;
case 5:
reg[1] = (byte)(data & 0x01);
break;
case 6:
reg[2] = (byte)((reg[2] & 0x01) | ((data & 0x03) << 1));
break;
case 7:
reg[3] = (byte)(data & 0x01);
break;
default:
break;
}
SetPROM_32K_Bank(reg[1]);
SetVROM_8K_Bank(reg[2] * 8 + 0, reg[2] * 8 + 1, reg[2] * 8 + 2, reg[2] * 8 + 3,
reg[2] * 8 + 4, reg[2] * 8 + 5, reg[2] * 8 + 6, reg[2] * 8 + 7);
if (reg[3] != 0)
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
}
}
public override bool IsStateSave()
{
return true;
}
//void Mapper243::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
//p[0] = reg[0];
//p[1] = reg[1];
//p[2] = reg[2];
//p[3] = reg[3];
}
//void Mapper243::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
//reg[0] = p[0];
//reg[1] = p[1];
//reg[2] = p[2];
//reg[3] = p[3];
}
}
}

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//////////////////////////////////////////////////////////////////////////
// Mapper244 //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper244 : Mapper
{
public Mapper244(NES parent) : base(parent)
{
}
//void Mapper244::Reset()
public override void Reset()
{
SetPROM_32K_Bank(0);
}
//void Mapper244::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
if (addr >= 0x8065 && addr <= 0x80A4)
{
SetPROM_32K_Bank((addr - 0x8065) & 0x3);
}
if (addr >= 0x80A5 && addr <= 0x80E4)
{
SetVROM_8K_Bank((addr - 0x80A5) & 0x7);
}
}
}
}

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//////////////////////////////////////////////////////////////
// Mapper245 Yong Zhe Dou E Long //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper245 : Mapper
{
BYTE[] reg = new byte[8];
BYTE prg0, prg1;
BYTE chr01, chr23, chr4, chr5, chr6, chr7;
BYTE we_sram;
BYTE irq_type;
BYTE irq_enable;
BYTE irq_counter;
BYTE irq_latch;
BYTE irq_request;
int MMC4prg, MMC4chr;
public Mapper245(NES parent) : base(parent)
{
}
//void Mapper245::Reset()
public override void Reset()
{
for (INT i = 0; i < 8; i++)
{
reg[i] = 0x00;
}
prg0 = 0;
prg1 = 1;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
if (VROM_1K_SIZE != 0)
{
SetVROM_8K_Bank(0);
}
we_sram = 0; // Disable
irq_enable = 0; // Disable
irq_counter = 0;
irq_latch = 0;
irq_request = 0;
nes.SetIrqType(NES.IRQMETHOD.IRQ_CLOCK);
}
//void Mapper245::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
switch (addr & 0xF7FF)
{
case 0x8000:
reg[0] = data;
break;
case 0x8001:
reg[1] = data;
switch (reg[0])
{
case 0x00:
reg[3] = (byte)((data & 2) << 5);
SetPROM_8K_Bank(6, 0x3E | reg[3]);
SetPROM_8K_Bank(7, 0x3F | reg[3]);
break;
case 0x06:
prg0 = data;
break;
case 0x07:
prg1 = data;
break;
}
SetPROM_8K_Bank(4, prg0 | reg[3]);
SetPROM_8K_Bank(5, prg1 | reg[3]);
break;
case 0xA000:
reg[2] = data;
if (!nes.rom.Is4SCREEN())
{
if ((data & 0x01) != 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR);
}
break;
case 0xA001:
break;
case 0xC000:
reg[4] = data;
irq_counter = data;
irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
case 0xC001:
reg[5] = data;
irq_latch = data;
irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
case 0xE000:
reg[6] = data;
irq_enable = 0;
irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
case 0xE001:
reg[7] = data;
irq_enable = 1;
irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
}
}
//void Mapper245::Clock(INT cycles)
public override void Clock(int cycles)
{
// if( irq_request && (nes.GetIrqType() == NES::IRQ_CLOCK) ) {
// nes.cpu.IRQ_NotPending();
// }
}
//void Mapper245::HSync(INT scanline)
public override void HSync(int scanline)
{
if ((scanline >= 0 && scanline <= 239))
{
if (nes.ppu.IsDispON())
{
if (irq_enable != 0&& irq_request == 0)
{
if (scanline == 0)
{
if (irq_counter != 0)
{
irq_counter--;
}
}
if ((irq_counter--) == 0)
{
irq_request = 0xFF;
irq_counter = irq_latch;
nes.cpu.SetIRQ(IRQ_MAPPER);
}
}
}
}
// if( irq_request && (nes.GetIrqType() == NES::IRQ_HSYNC) ) {
// nes.cpu.IRQ_NotPending();
// }
}
void SetBank_CPU()
{
SetPROM_32K_Bank(prg0, prg1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
}
void SetBank_PPU()
{
if ((VROM_1K_SIZE)!= 0)
{
if (((reg[0] & 0x80) !+ 0) != 0)
{
SetVROM_8K_Bank(chr4, chr5, chr6, chr7,
chr23 + 1, chr23, chr01 + 1, chr01);
}
else
{
SetVROM_8K_Bank(chr01, chr01 + 1, chr23, chr23 + 1,
chr4, chr5, chr6, chr7);
}
}
else
{
if ((reg[0] & 0x80) != 0)
{
SetCRAM_1K_Bank(4, (chr01 + 0) & 0x07);
SetCRAM_1K_Bank(5, (chr01 + 1) & 0x07);
SetCRAM_1K_Bank(6, (chr23 + 0) & 0x07);
SetCRAM_1K_Bank(7, (chr23 + 1) & 0x07);
SetCRAM_1K_Bank(0, chr4 & 0x07);
SetCRAM_1K_Bank(1, chr5 & 0x07);
SetCRAM_1K_Bank(2, chr6 & 0x07);
SetCRAM_1K_Bank(3, chr7 & 0x07);
}
else
{
SetCRAM_1K_Bank(0, (chr01 + 0) & 0x07);
SetCRAM_1K_Bank(1, (chr01 + 1) & 0x07);
SetCRAM_1K_Bank(2, (chr23 + 0) & 0x07);
SetCRAM_1K_Bank(3, (chr23 + 1) & 0x07);
SetCRAM_1K_Bank(4, chr4 & 0x07);
SetCRAM_1K_Bank(5, chr5 & 0x07);
SetCRAM_1K_Bank(6, chr6 & 0x07);
SetCRAM_1K_Bank(7, chr7 & 0x07);
}
}
}
public override bool IsStateSave()
{
return true;
}
//void Mapper245::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
//for (INT i = 0; i < 8; i++)
//{
// p[i] = reg[i];
//}
//p[8] = prg0;
//p[9] = prg1;
//p[10] = chr01;
//p[11] = chr23;
//p[12] = chr4;
//p[13] = chr5;
//p[14] = chr6;
//p[15] = chr7;
//p[16] = irq_enable;
//p[17] = (BYTE)irq_counter;
//p[18] = irq_latch;
//p[19] = irq_request;
}
//void Mapper245::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
//for (INT i = 0; i < 8; i++)
//{
// reg[i] = p[i];
//}
//prg0 = p[8];
//prg1 = p[9];
//chr01 = p[10];
//chr23 = p[11];
//chr4 = p[12];
//chr5 = p[13];
//chr6 = p[14];
//chr7 = p[15];
//irq_enable = p[16];
//irq_counter = (INT)p[17];
//irq_latch = p[18];
//irq_request = p[19];
}
}
}

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//////////////////////////////////////////////////////////////////////////
// Mapper246 Phone Serm Berm //
//////////////////////////////////////////////////////////////////////////
using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper246 : Mapper
{
public Mapper246(NES parent) : base(parent)
{
}
//void Mapper246::Reset()
public override void Reset()
{
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
}
//void Mapper246::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data)
{
if (addr >= 0x6000 && addr < 0x8000)
{
switch (addr)
{
case 0x6000:
SetPROM_8K_Bank(4, data);
break;
case 0x6001:
SetPROM_8K_Bank(5, data);
break;
case 0x6002:
SetPROM_8K_Bank(6, data);
break;
case 0x6003:
SetPROM_8K_Bank(7, data);
break;
case 0x6004:
SetVROM_2K_Bank(0, data);
break;
case 0x6005:
SetVROM_2K_Bank(2, data);
break;
case 0x6006:
SetVROM_2K_Bank(4, data);
break;
case 0x6007:
SetVROM_2K_Bank(6, data);
break;
default:
CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
break;
}
}
}
}
}

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using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
namespace VirtualNes.Core
{
public class Mapper248 : Mapper
{
BYTE[] reg = new BYTE[8];
BYTE prg0, prg1;
BYTE chr01, chr23, chr4, chr5, chr6, chr7;
BYTE we_sram;
BYTE irq_enable;
BYTE irq_counter;
BYTE irq_latch;
BYTE irq_request;
public Mapper248(NES parent) : base(parent)
{
}
public override void Reset()
{
for (INT i = 0; i < 8; i++)
{
reg[i] = 0x00;
}
prg0 = 0;
prg1 = 1;
SetBank_CPU();
chr01 = 0;
chr23 = 2;
chr4 = 4;
chr5 = 5;
chr6 = 6;
chr7 = 7;
SetBank_PPU();
we_sram = 0; // Disable
irq_enable = 0; // Disable
irq_counter = 0;
irq_latch = 0;
irq_request = 0;
}
//void Mapper248::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data)
{
SetPROM_32K_Bank(2 * data, 2 * data + 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
}
//void Mapper248::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
switch (addr & 0xE001)
{
case 0x8000:
reg[0] = data;
SetBank_CPU();
SetBank_PPU();
break;
case 0x8001:
reg[1] = data;
switch (reg[0] & 0x07)
{
case 0x00:
chr01 = (byte)(data & 0xFE);
SetBank_PPU();
break;
case 0x01:
chr23 = (byte)(data & 0xFE);
SetBank_PPU();
break;
case 0x02:
chr4 = data;
SetBank_PPU();
break;
case 0x03:
chr5 = data;
SetBank_PPU();
break;
case 0x04:
chr6 = data;
SetBank_PPU();
break;
case 0x05:
chr7 = data;
SetBank_PPU();
break;
case 0x06:
prg0 = data;
SetBank_CPU();
break;
case 0x07:
prg1 = data;
SetBank_CPU();
break;
}
break;
case 0xA000:
reg[2] = data;
if (!nes.rom.Is4SCREEN())
{
if ((data & 0x01) != 0)
{
SetVRAM_Mirror(VRAM_HMIRROR);
}
else
{
SetVRAM_Mirror(VRAM_VMIRROR);
}
}
break;
case 0xC000:
irq_enable = 0;
irq_latch = 0xBE;
irq_counter = 0xBE;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
case 0xC001:
irq_enable = 1;
irq_latch = 0xBE;
irq_counter = 0xBE;
break;
}
}
//void Mapper248::HSync(INT scanline)
public override void HSync(int scanline)
{
if ((scanline >= 0 && scanline <= 239))
{
if (nes.ppu.IsDispON())
{
if (irq_enable != 0)
{
if ((irq_counter--) == 0)
{
irq_counter = irq_latch;
// nes->cpu->IRQ_NotPending();
nes.cpu.SetIRQ(IRQ_MAPPER);
}
}
}
}
}
void SetBank_CPU()
{
if ((reg[0] & 0x40) != 0)
{
SetPROM_32K_Bank(PROM_8K_SIZE - 2, prg1, prg0, PROM_8K_SIZE - 1);
}
else
{
SetPROM_32K_Bank(prg0, prg1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
}
}
void SetBank_PPU()
{
if (VROM_1K_SIZE != 0)
{
if ((reg[0] & 0x80) != 0)
{
SetVROM_8K_Bank(chr4, chr5, chr6, chr7,
chr01, chr01 + 1, chr23, chr23 + 1);
}
else
{
SetVROM_8K_Bank(chr01, chr01 + 1, chr23, chr23 + 1,
chr4, chr5, chr6, chr7);
}
}
}
public override bool IsStateSave()
{
return true;
}
//void Mapper248::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
//for (INT i = 0; i < 8; i++)
//{
// p[i] = reg[i];
//}
//p[8] = prg0;
//p[9] = prg1;
//p[10] = chr01;
//p[11] = chr23;
//p[12] = chr4;
//p[13] = chr5;
//p[14] = chr6;
//p[15] = chr7;
//p[16] = irq_enable;
//p[17] = (BYTE)irq_counter;
//p[18] = irq_latch;
//p[19] = irq_request;
}
//void Mapper248::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
//for (INT i = 0; i < 8; i++)
//{
// reg[i] = p[i];
//}
//prg0 = p[8];
//prg1 = p[9];
//chr01 = p[10];
//chr23 = p[11];
//chr4 = p[12];
//chr5 = p[13];
//chr6 = p[14];
//chr7 = p[15];
//irq_enable = p[16];
//irq_counter = (INT)p[17];
//irq_latch = p[18];
//irq_request = p[19];
}
}
}

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using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper249 : Mapper
{
int MMC4prg, MMC4chr;
BYTE spdata;
BYTE[] reg = new BYTE[8];
BYTE prg0, prg1;
BYTE chr01, chr23, chr4, chr5, chr6, chr7;
BYTE we_sram;
BYTE patch;
BYTE irq_type;
BYTE irq_enable;
BYTE irq_counter;
BYTE irq_latch;
BYTE irq_request;
public Mapper249(NES parent) : base(parent)
{
}
public override void Reset()
{
for (INT i = 0; i < 8; i++)
{
reg[i] = 0x00;
}
prg0 = 0;
prg1 = 1;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
chr01 = 0;
chr23 = 2;
chr4 = 4;
chr5 = 5;
chr6 = 6;
chr7 = 7;
SetVROM_8K_Bank(0);
we_sram = 0; // Disable
irq_enable = 0; // Disable
irq_counter = 0;
irq_latch = 0;
irq_request = 0;
// IRQタイプ設定
nes.SetIrqType(NES.IRQMETHOD.IRQ_CLOCK);
spdata = 0;
}
//void Mapper249::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data)
{
if (addr == 0x5000)
{
switch (data)
{
case 0x00:
spdata = 0;
break;
case 0x02:
spdata = 1;
break;
}
}
if (addr >= 0x6000 && addr < 0x8000)
{
CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
}
}
//void Mapper249::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
BYTE m0, m1, m2, m3, m4, m5, m6, m7;
switch (addr & 0xFF01)
{
case 0x8000:
case 0x8800:
reg[0] = data;
break;
case 0x8001:
case 0x8801:
switch (reg[0] & 0x07)
{
case 0x00:
if (spdata == 1)
{
m0 = (byte)(data & 0x1);
m1 = (byte)((data & 0x02) >> 1);
m2 = (byte)((data & 0x04) >> 2);
m3 = (byte)((data & 0x08) >> 3);
m4 = (byte)((data & 0x10) >> 4);
m5 = (byte)((data & 0x20) >> 5);
m6 = (byte)((data & 0x40) >> 6);
m7 = (byte)((data & 0x80) >> 7);
data = (byte)((m5 << 7) | (m4 << 6) | (m2 << 5) | (m6 << 4) | (m7 << 3) | (m3 << 2) | (m1 << 1) | m0);
}
SetVROM_1K_Bank(0, data & 0xFE);
SetVROM_1K_Bank(1, data | 0x01);
break;
case 0x01:
if (spdata == 1)
{
m0 = (byte)(data & 0x1);
m1 = (byte)((data & 0x02) >> 1);
m2 = (byte)((data & 0x04) >> 2);
m3 = (byte)((data & 0x08) >> 3);
m4 = (byte)((data & 0x10) >> 4);
m5 = (byte)((data & 0x20) >> 5);
m6 = (byte)((data & 0x40) >> 6);
m7 = (byte)((data & 0x80) >> 7);
data = (byte)((m5 << 7) | (m4 << 6) | (m2 << 5) | (m6 << 4) | (m7 << 3) | (m3 << 2) | (m1 << 1) | m0);
}
SetVROM_1K_Bank(2, data & 0xFE);
SetVROM_1K_Bank(3, data | 0x01);
break;
case 0x02:
if (spdata == 1)
{
m0 = (byte)(data & 0x1);
m1 = (byte)((data & 0x02) >> 1);
m2 = (byte)((data & 0x04) >> 2);
m3 = (byte)((data & 0x08) >> 3);
m4 = (byte)((data & 0x10) >> 4);
m5 = (byte)((data & 0x20) >> 5);
m6 = (byte)((data & 0x40) >> 6);
m7 = (byte)((data & 0x80) >> 7);
data = (byte)((m5 << 7) | (m4 << 6) | (m2 << 5) | (m6 << 4) | (m7 << 3) | (m3 << 2) | (m1 << 1) | m0);
}
SetVROM_1K_Bank(4, data);
break;
case 0x03:
if (spdata == 1)
{
m0 = (byte)(data & 0x1);
m1 = (byte)((data & 0x02) >> 1);
m2 = (byte)((data & 0x04) >> 2);
m3 = (byte)((data & 0x08) >> 3);
m4 = (byte)((data & 0x10) >> 4);
m5 = (byte)((data & 0x20) >> 5);
m6 = (byte)((data & 0x40) >> 6);
m7 = (byte)((data & 0x80) >> 7);
data = (byte)((m5 << 7) | (m4 << 6) | (m2 << 5) | (m6 << 4) | (m7 << 3) | (m3 << 2) | (m1 << 1) | m0);
}
SetVROM_1K_Bank(5, data);
break;
case 0x04:
if (spdata == 1)
{
m0 = (byte)(data & 0x1);
m1 = (byte)((data & 0x02) >> 1);
m2 = (byte)((data & 0x04) >> 2);
m3 = (byte)((data & 0x08) >> 3);
m4 = (byte)((data & 0x10) >> 4);
m5 = (byte)((data & 0x20) >> 5);
m6 = (byte)((data & 0x40) >> 6);
m7 = (byte)((data & 0x80) >> 7);
data = (byte)((m5 << 7) | (m4 << 6) | (m2 << 5) | (m6 << 4) | (m7 << 3) | (m3 << 2) | (m1 << 1) | m0);
}
SetVROM_1K_Bank(6, data);
break;
case 0x05:
if (spdata == 1)
{
m0 = (byte)(data & 0x1);
m1 = (byte)((data & 0x02) >> 1);
m2 = (byte)((data & 0x04) >> 2);
m3 = (byte)((data & 0x08) >> 3);
m4 = (byte)((data & 0x10) >> 4);
m5 = (byte)((data & 0x20) >> 5);
m6 = (byte)((data & 0x40) >> 6);
m7 = (byte)((data & 0x80) >> 7);
data = (byte)((m5 << 7) | (m4 << 6) | (m2 << 5) | (m6 << 4) | (m7 << 3) | (m3 << 2) | (m1 << 1) | m0);
}
SetVROM_1K_Bank(7, data);
break;
case 0x06:
if (spdata == 1)
{
if (data < 0x20)
{
m0 = (byte)(data & 0x1);
m1 = (byte)((data & 0x02) >> 1);
m2 = (byte)((data & 0x04) >> 2);
m3 = (byte)((data & 0x08) >> 3);
m4 = (byte)((data & 0x10) >> 4);
m5 = 0;
m6 = 0;
m7 = 0;
data = (byte)((m7 << 7) | (m6 << 6) | (m5 << 5) | (m2 << 4) | (m1 << 3) | (m3 << 2) | (m4 << 1) | m0);
}
else
{
data = (byte)(data - 0x20);
m0 = (byte)(data & 0x1);
m1 = (byte)((data & 0x02) >> 1);
m2 = (byte)((data & 0x04) >> 2);
m3 = (byte)((data & 0x08) >> 3);
m4 = (byte)((data & 0x10) >> 4);
m5 = (byte)((data & 0x20) >> 5);
m6 = (byte)((data & 0x40) >> 6);
m7 = (byte)((data & 0x80) >> 7);
data = (byte)((m5 << 7) | (m4 << 6) | (m2 << 5) | (m6 << 4) | (m7 << 3) | (m3 << 2) | (m1 << 1) | m0);
}
}
SetPROM_8K_Bank(4, data);
break;
case 0x07:
if (spdata == 1)
{
if (data < 0x20)
{
m0 = (byte)(data & 0x1);
m1 = (byte)((data & 0x02) >> 1);
m2 = (byte)((data & 0x04) >> 2);
m3 = (byte)((data & 0x08) >> 3);
m4 = (byte)((data & 0x10) >> 4);
m5 = 0;
m6 = 0;
m7 = 0;
data = (byte)((m7 << 7) | (m6 << 6) | (m5 << 5) | (m2 << 4) | (m1 << 3) | (m3 << 2) | (m4 << 1) | m0);
}
else
{
data = (byte)(data - 0x20);
m0 = (byte)(data & 0x1);
m1 = (byte)((data & 0x02) >> 1);
m2 = (byte)((data & 0x04) >> 2);
m3 = (byte)((data & 0x08) >> 3);
m4 = (byte)((data & 0x10) >> 4);
m5 = (byte)((data & 0x20) >> 5);
m6 = (byte)((data & 0x40) >> 6);
m7 = (byte)((data & 0x80) >> 7);
data = (byte)((m5 << 7) | (m4 << 6) | (m2 << 5) | (m6 << 4) | (m7 << 3) | (m3 << 2) | (m1 << 1) | m0);
}
}
SetPROM_8K_Bank(5, data);
break;
}
break;
case 0xA000:
case 0xA800:
reg[2] = data;
if (!nes.rom.Is4SCREEN())
{
if ((data & 0x01)!= 0) SetVRAM_Mirror(VRAM_HMIRROR);
else SetVRAM_Mirror(VRAM_VMIRROR);
}
break;
case 0xA001:
case 0xA801:
reg[3] = data;
break;
case 0xC000:
case 0xC800:
reg[4] = data;
irq_counter = data;
irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
case 0xC001:
case 0xC801:
reg[5] = data;
irq_latch = data;
irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
case 0xE000:
case 0xE800:
reg[6] = data;
irq_enable = 0;
irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
case 0xE001:
case 0xE801:
reg[7] = data;
irq_enable = 1;
irq_request = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
}
}
//void Mapper249::Clock(INT cycles)
public override void Clock(int cycles)
{
// if( irq_request && (nes->GetIrqType() == NES::IRQ_CLOCK) ) {
// nes->cpu->IRQ_NotPending();
// }
}
//void Mapper249::HSync(INT scanline)
public override void HSync(int scanline)
{
if ((scanline >= 0 && scanline <= 239))
{
if (nes.ppu.IsDispON())
{
if (irq_enable !=0 && irq_request == 0)
{
if (scanline == 0)
{
if (irq_counter != 0)
{
irq_counter--;
}
}
if ((irq_counter--) == 0)
{
irq_request = 0xFF;
irq_counter = irq_latch;
nes.cpu.SetIRQ(IRQ_MAPPER);
}
}
}
}
// if( irq_request && (nes->GetIrqType() == NES::IRQ_HSYNC) ) {
// nes->cpu->IRQ_NotPending();
// }
}
public override bool IsStateSave()
{
return true;
}
//void Mapper249::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
//for (INT i = 0; i < 8; i++)
//{
// p[i] = reg[i];
//}
//p[8] = prg0;
//p[9] = prg1;
//p[10] = chr01;
//p[11] = chr23;
//p[12] = chr4;
//p[13] = chr5;
//p[14] = chr6;
//p[15] = chr7;
//p[16] = irq_enable;
//p[17] = irq_counter;
//p[18] = irq_latch;
//p[19] = irq_request;
//p[20] = spdata;
}
//void Mapper249::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
//for (INT i = 0; i < 8; i++)
//{
// reg[i] = p[i];
//}
//prg0 = p[8];
//prg1 = p[9];
//chr01 = p[10];
//chr23 = p[11];
//chr4 = p[12];
//chr5 = p[13];
//chr6 = p[14];
//chr7 = p[15];
//irq_enable = p[16];
//irq_counter = p[17];
//irq_latch = p[18];
//irq_request = p[19];
//spdata = p[20];
}
}
}

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using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
using Codice.CM.Client.Differences;
namespace VirtualNes.Core
{
public class Mapper251 : Mapper
{
BYTE[] reg = new BYTE[11];
BYTE[] breg = new BYTE[4];
public Mapper251(NES parent) : base(parent)
{
}
public override void Reset()
{
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
SetVRAM_Mirror(VRAM_VMIRROR);
INT i;
for (i = 0; i < 11; i++)
reg[i] = 0;
for (i = 0; i < 4; i++)
breg[i] = 0;
}
//void Mapper251::WriteLow(WORD addr, BYTE data)
public override void WriteLow(ushort addr, byte data)
{
if ((addr & 0xE001) == 0x6000)
{
if (reg[9] != null)
{
breg[reg[10]++] = data;
if (reg[10] == 4)
{
reg[10] = 0;
SetBank();
}
}
}
}
//void Mapper251::Write(WORD addr, BYTE data)
public override void Write(ushort addr, byte data)
{
switch (addr & 0xE001)
{
case 0x8000:
reg[8] = data;
SetBank();
break;
case 0x8001:
reg[reg[8] & 0x07] = data;
SetBank();
break;
case 0xA001:
if ((data & 0x80)!= 0)
{
reg[9] = 1;
reg[10] = 0;
}
else
{
reg[9] = 0;
}
break;
}
}
//void Mapper251::SetBank()
public void SetBank()
{
INT[] chr = new INT[6];
INT[] prg = new int[4];
for (INT i = 0; i < 6; i++)
{
chr[i] = (reg[i] | (breg[1] << 4)) & ((breg[2] << 4) | 0x0F);
}
if ((reg[8] & 0x80) != 0)
{
SetVROM_8K_Bank(chr[2], chr[3], chr[4], chr[5], chr[0], chr[0] + 1, chr[1], chr[1] + 1);
}
else
{
SetVROM_8K_Bank(chr[0], chr[0] + 1, chr[1], chr[1] + 1, chr[2], chr[3], chr[4], chr[5]);
}
prg[0] = (reg[6] & ((breg[3] & 0x3F) ^ 0x3F)) | (breg[1]);
prg[1] = (reg[7] & ((breg[3] & 0x3F) ^ 0x3F)) | (breg[1]);
prg[2] = prg[3] = ((breg[3] & 0x3F) ^ 0x3F) | (breg[1]);
prg[2] &= PROM_8K_SIZE - 1;
if ((reg[8] & 0x40) != 0)
{
SetPROM_32K_Bank(prg[2], prg[1], prg[0], prg[3]);
}
else
{
SetPROM_32K_Bank(prg[0], prg[1], prg[2], prg[3]);
}
}
public override bool IsStateSave()
{
return true;
}
//void Mapper251::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
//INT i;
//for (i = 0; i < 11; i++)
//{
// p[i] = reg[i];
//}
//for (i = 0; i < 4; i++)
//{
// p[i + 11] = breg[i];
//}
}
//void Mapper251::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
//INT i;
//for (i = 0; i < 11; i++)
//{
// reg[i] = p[i];
//}
//for (i = 0; i < 4; i++)
//{
// reg[i] = p[i + 11];
//}
}
}
}

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using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
namespace VirtualNes.Core
{
public class Mapper252 : Mapper
{
BYTE[] reg = new BYTE[9];
BYTE irq_enable;
BYTE irq_counter;
BYTE irq_latch;
BYTE irq_occur;
INT irq_clock;
public Mapper252(NES parent) : base(parent)
{
}
public override void Reset()
{
for (byte i = 0; i < 8; i++)
{
reg[i] = i;
}
reg[8] = 0;
irq_enable = 0;
irq_counter = 0;
irq_latch = 0;
irq_clock = 0;
irq_occur = 0;
SetPROM_32K_Bank(0, 1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
SetVROM_8K_Bank(0);
nes.SetRenderMethod(EnumRenderMethod.POST_RENDER);
}
public override void Write(ushort addr, byte data)
{
if ((addr & 0xF000) == 0x8000)
{
SetPROM_8K_Bank(4, data);
return;
}
if ((addr & 0xF000) == 0xA000)
{
SetPROM_8K_Bank(5, data);
return;
}
switch (addr & 0xF00C)
{
case 0xB000:
reg[0] = (byte)((reg[0] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(0, reg[0]);
break;
case 0xB004:
reg[0] = (byte)((reg[0] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(0, reg[0]);
break;
case 0xB008:
reg[1] = (byte)((reg[1] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(1, reg[1]);
break;
case 0xB00C:
reg[1] = (byte)((reg[1] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(1, reg[1]);
break;
case 0xC000:
reg[2] = (byte)((reg[2] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(2, reg[2]);
break;
case 0xC004:
reg[2] = (byte)(((reg[2] & 0x0F) | ((data & 0x0F) << 4)));
SetVROM_1K_Bank(2, reg[2]);
break;
case 0xC008:
reg[3] = (byte)((reg[3] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(3, reg[3]);
break;
case 0xC00C:
reg[3] = (byte)((reg[3] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(3, reg[3]);
break;
case 0xD000:
reg[4] = (byte)((reg[4] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(4, reg[4]);
break;
case 0xD004:
reg[4] = (byte)((reg[4] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(4, reg[4]);
break;
case 0xD008:
reg[5] = (byte)((reg[5] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(5, reg[5]);
break;
case 0xD00C:
reg[5] = (byte)((reg[5] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(5, reg[5]);
break;
case 0xE000:
reg[6] = (byte)((reg[6] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(6, reg[6]);
break;
case 0xE004:
reg[6] = (byte)((reg[6] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(6, reg[6]);
break;
case 0xE008:
reg[7] = (byte)((reg[7] & 0xF0) | (data & 0x0F));
SetVROM_1K_Bank(7, reg[7]);
break;
case 0xE00C:
reg[7] = (byte)((reg[7] & 0x0F) | ((data & 0x0F) << 4));
SetVROM_1K_Bank(7, reg[7]);
break;
case 0xF000:
irq_latch = (byte)((irq_latch & 0xF0) | (data & 0x0F));
irq_occur = 0;
break;
case 0xF004:
irq_latch = (byte)((irq_latch & 0x0F) | ((data & 0x0F) << 4));
irq_occur = 0;
break;
case 0xF008:
irq_enable = (byte)(data & 0x03);
if ((irq_enable & 0x02) != 0)
{
irq_counter = irq_latch;
irq_clock = 0;
}
irq_occur = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
case 0xF00C:
irq_enable = (byte)((irq_enable & 0x01) * 3);
irq_occur = 0;
nes.cpu.ClrIRQ(IRQ_MAPPER);
break;
}
}
//void Mapper252::Clock(INT cycles)
public override void Clock(int cycles)
{
if ((irq_enable & 0x02) != 0)
{
if ((irq_clock += cycles) >= 0x72)
{
irq_clock -= 0x72;
if (irq_counter == 0xFF)
{
irq_occur = 0xFF;
irq_counter = irq_latch;
irq_enable = (byte)((irq_enable & 0x01) * 3);
nes.cpu.SetIRQ(IRQ_MAPPER);
}
else
{
irq_counter++;
}
}
// if( irq_occur ) {
// nes->cpu->IRQ_NotPending();
// }
}
}
public override bool IsStateSave()
{
return true;
}
//void Mapper252::SaveState(LPBYTE p)
public override void SaveState(byte[] p)
{
for (INT i = 0; i < 9; i++)
{
p[i] = reg[i];
}
p[9] = irq_enable;
p[10] = irq_counter;
p[11] = irq_latch;
//*(INT*)&p[12] = irq_clock;
Array.Copy(p, 12, BitConverter.GetBytes(irq_clock), 0, 4);
}
//void Mapper252::LoadState(LPBYTE p)
public override void LoadState(byte[] p)
{
for (INT i = 0; i < 9; i++)
{
reg[i] = p[i];
}
irq_enable = p[9];
irq_counter = p[10];
irq_latch = p[11];
//irq_clock = *(INT*)&p[12];
irq_clock = BitConverter.ToInt32(p,12);
}
}
}

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using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
namespace VirtualNes.Core
{
public class Mapper254 : Mapper
{
BYTE[] reg = new BYTE[8];
BYTE prg0, prg1;
BYTE chr01, chr23, chr4, chr5, chr6, chr7;
BYTE irq_type;
BYTE irq_enable;
BYTE irq_counter;
BYTE irq_latch;
BYTE irq_request;
BYTE protectflag;
public Mapper254(NES parent) : base(parent)
{
}
public override void Reset()
{
for (int i = 0; i < 8; i++)
{
reg[i] = 0x00;
}
protectflag = 0;
prg0 = 0;
prg1 = 1;
SetBank_CPU();
chr01 = 0;
chr23 = 2;
chr4 = 4;
chr5 = 5;
chr6 = 6;
chr7 = 7;
SetBank_PPU();
irq_enable = 0; // Disable
irq_counter = 0;
irq_latch = 0;
irq_request = 0;
}
public override void WriteLow(ushort addr, byte data)
{
switch (addr & 0xF000)
{
case 0x6000:
case 0x7000:
MMU.CPU_MEM_BANK[addr >> 13][addr & 0x1FFF] = data;
break;
}
}
public override byte ReadLow(ushort addr)
{
if (addr >= 0x6000)
{
if (protectflag != 0)
{
return (MMU.CPU_MEM_BANK[addr >> 13][addr & 0x1FFF]);
}
else
{
return (byte)((MMU.CPU_MEM_BANK[addr >> 13][addr & 0x1FFF]) ^ 0x1);
}
}
return base.ReadLow(addr);
}
public override void Write(ushort addr, byte data)
{
switch (addr & 0xE001)
{
case 0x8000:
protectflag = 0xFF;
reg[0] = data;
SetBank_CPU();
SetBank_PPU();
break;
case 0x8001:
reg[1] = data;
switch (reg[0] & 0x07)
{
case 0x00:
chr01 = (byte)(data & 0xFE);
SetBank_PPU();
break;
case 0x01:
chr23 = (byte)(data & 0xFE);
SetBank_PPU();
break;
case 0x02:
chr4 = data;
SetBank_PPU();
break;
case 0x03:
chr5 = data;
SetBank_PPU();
break;
case 0x04:
chr6 = data;
SetBank_PPU();
break;
case 0x05:
chr7 = data;
SetBank_PPU();
break;
case 0x06:
prg0 = data;
SetBank_CPU();
break;
case 0x07:
prg1 = data;
SetBank_CPU();
break;
}
break;
case 0xA000:
reg[2] = data;
if (!nes.rom.Is4SCREEN())
{
if ((data & 0x01) != 0) MMU.SetVRAM_Mirror(MMU.VRAM_HMIRROR);
else MMU.SetVRAM_Mirror(MMU.VRAM_VMIRROR);
}
break;
case 0xA001:
reg[3] = data;
break;
case 0xC000:
reg[4] = data;
irq_counter = data;
irq_request = 0;
nes.cpu.ClrIRQ(CPU.IRQ_MAPPER);
break;
case 0xC001:
reg[5] = data;
irq_latch = data;
irq_request = 0;
nes.cpu.ClrIRQ(CPU.IRQ_MAPPER);
break;
case 0xE000:
reg[6] = data;
irq_enable = 0;
irq_request = 0;
nes.cpu.ClrIRQ(CPU.IRQ_MAPPER);
break;
case 0xE001:
reg[7] = data;
irq_enable = 1;
irq_request = 0;
nes.cpu.ClrIRQ(CPU.IRQ_MAPPER);
break;
}
}
public override void Clock(int cycles)
{
// if( irq_request && (nes->GetIrqType() == NES::IRQ_CLOCK) ) {
// nes->cpu->IRQ_NotPending();
// }
}
public override void HSync(int scanline)
{
if ((scanline >= 0 && scanline <= 239))
{
if (nes.ppu.IsDispON())
{
if (irq_enable != 0 && irq_request == 0)
{
if (scanline == 0)
{
if (irq_counter != 0)
{
irq_counter--;
}
}
if ((irq_counter--) == 0)
{
irq_request = 0xFF;
irq_counter = irq_latch;
nes.cpu.SetIRQ(CPU.IRQ_MAPPER);
}
}
}
}
// if( irq_request && (nes->GetIrqType() == NES::IRQ_HSYNC) ) {
// nes->cpu->IRQ_NotPending();
// }
}
public void SetBank_CPU()
{
if ((reg[0] & 0x40)!=0)
{
SetPROM_32K_Bank(PROM_8K_SIZE - 2, prg1, prg0, PROM_8K_SIZE - 1);
}
else
{
SetPROM_32K_Bank(prg0, prg1, PROM_8K_SIZE - 2, PROM_8K_SIZE - 1);
}
}
public void SetBank_PPU()
{
if (VROM_1K_SIZE != 0)
{
if ((reg[0] & 0x80)!= 0)
{
SetVROM_8K_Bank(chr4, chr5, chr6, chr7,
chr01, chr01 + 1, chr23, chr23 + 1);
}
else
{
SetVROM_8K_Bank(chr01, chr01 + 1, chr23, chr23 + 1,
chr4, chr5, chr6, chr7);
}
}
else
{
if ((reg[0] & 0x80) != 0)
{
SetCRAM_1K_Bank(4, (chr01 + 0) & 0x07);
SetCRAM_1K_Bank(5, (chr01 + 1) & 0x07);
SetCRAM_1K_Bank(6, (chr23 + 0) & 0x07);
SetCRAM_1K_Bank(7, (chr23 + 1) & 0x07);
SetCRAM_1K_Bank(0, chr4 & 0x07);
SetCRAM_1K_Bank(1, chr5 & 0x07);
SetCRAM_1K_Bank(2, chr6 & 0x07);
SetCRAM_1K_Bank(3, chr7 & 0x07);
}
else
{
SetCRAM_1K_Bank(0, (chr01 + 0) & 0x07);
SetCRAM_1K_Bank(1, (chr01 + 1) & 0x07);
SetCRAM_1K_Bank(2, (chr23 + 0) & 0x07);
SetCRAM_1K_Bank(3, (chr23 + 1) & 0x07);
SetCRAM_1K_Bank(4, chr4 & 0x07);
SetCRAM_1K_Bank(5, chr5 & 0x07);
SetCRAM_1K_Bank(6, chr6 & 0x07);
SetCRAM_1K_Bank(7, chr7 & 0x07);
}
}
}
public override bool IsStateSave()
{
return true;
}
public override void SaveState(byte[] p)
{
for (int i = 0; i < 8; i++)
{
p[i] = reg[i];
}
p[8] = prg0;
p[9] = prg1;
p[10] = chr01;
p[11] = chr23;
p[12] = chr4;
p[13] = chr5;
p[14] = chr6;
p[15] = chr7;
p[16] = irq_enable;
p[17] = irq_counter;
p[18] = irq_latch;
p[19] = irq_request;
p[20] = protectflag;
}
public override void LoadState(byte[] p)
{
for (int i = 0; i < 8; i++)
{
reg[i] = p[i];
}
prg0 = p[8];
prg1 = p[9];
chr01 = p[10];
chr23 = p[11];
chr4 = p[12];
chr5 = p[13];
chr6 = p[14];
chr7 = p[15];
irq_enable = p[16];
irq_counter = p[17];
irq_latch = p[18];
irq_request = p[19];
protectflag = p[20];
}
}
}

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using Codice.CM.Client.Differences;
using System;
namespace VirtualNes.Core
{
public class Mapper255 : Mapper
{
byte[] reg = new byte[4];
public Mapper255(NES parent) : base(parent)
{
}
public override void Reset()
{
MMU.SetPROM_32K_Bank(0);
MMU.SetVROM_8K_Bank(0);
MMU.SetVRAM_Mirror(MMU.VRAM_VMIRROR);
reg[0] = 0;
reg[1] = 0;
reg[2] = 0;
reg[3] = 0;
}
//BYTE Mapper255::ReadLow(WORD addr, BYTE data)
//{
// if (addr >= 0x5800)
// {
// return reg[addr & 0x0003] & 0x0F;
// }
// else
// {
// return addr >> 8;
// }
//}
public override byte ReadLow(ushort addr)
{
if (addr >= 0x5800)
{
return (byte)(reg[addr & 0x0003] & 0x0F);
}
else
{
return (byte)(addr >> 8);
}
}
public override void WriteLow(ushort addr, byte data)
{
if (addr >= 0x5800)
{
reg[addr & 0x0003] = (byte)(data & 0x0F);
}
}
public override void Write(ushort addr, byte data)
{
byte prg = (byte)((addr & 0x0F80) >> 7);
int chr = (byte)((addr & 0x003F));
int bank = (byte)((addr & 0x4000) >> 14);
if ((addr & 0x2000) != 0 )
{
MMU.SetVRAM_Mirror(MMU.VRAM_HMIRROR);
}
else
{
MMU.SetVRAM_Mirror(MMU.VRAM_VMIRROR);
}
if ((addr & 0x1000) !=0)
{
if ((addr & 0x0040) != 0)
{
MMU.SetPROM_8K_Bank(4, 0x80 * bank + prg * 4 + 2);
MMU.SetPROM_8K_Bank(5, 0x80 * bank + prg * 4 + 3);
MMU.SetPROM_8K_Bank(6, 0x80 * bank + prg * 4 + 2);
MMU.SetPROM_8K_Bank(7, 0x80 * bank + prg * 4 + 3);
}
else
{
MMU.SetPROM_8K_Bank(4, 0x80 * bank + prg * 4 + 0);
MMU.SetPROM_8K_Bank(5, 0x80 * bank + prg * 4 + 1);
MMU.SetPROM_8K_Bank(6, 0x80 * bank + prg * 4 + 0);
MMU.SetPROM_8K_Bank(7, 0x80 * bank + prg * 4 + 1);
}
}
else
{
MMU.SetPROM_8K_Bank(4, 0x80 * bank + prg * 4 + 0);
MMU.SetPROM_8K_Bank(5, 0x80 * bank + prg * 4 + 1);
MMU.SetPROM_8K_Bank(6, 0x80 * bank + prg * 4 + 2);
MMU.SetPROM_8K_Bank(7, 0x80 * bank + prg * 4 + 3);
}
MMU.SetVROM_1K_Bank(0, 0x200 * bank + chr * 8 + 0);
MMU.SetVROM_1K_Bank(1, 0x200 * bank + chr * 8 + 1);
MMU.SetVROM_1K_Bank(2, 0x200 * bank + chr * 8 + 2);
MMU.SetVROM_1K_Bank(3, 0x200 * bank + chr * 8 + 3);
MMU.SetVROM_1K_Bank(4, 0x200 * bank + chr * 8 + 4);
MMU.SetVROM_1K_Bank(5, 0x200 * bank + chr * 8 + 5);
MMU.SetVROM_1K_Bank(6, 0x200 * bank + chr * 8 + 6);
MMU.SetVROM_1K_Bank(7, 0x200 * bank + chr * 8 + 7);
}
// For state save
public override bool IsStateSave()
{
return true;
}
public override void SaveState(byte[] p)
{
p[0] = reg[0];
p[1] = reg[1];
p[2] = reg[2];
p[3] = reg[3];
}
public override void LoadState(byte[] p)
{
reg[0] = p[0];
reg[1] = p[1];
reg[2] = p[2];
reg[3] = p[3];
}
}
}

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AxibugEmuOnline.Client/Assets/VirtualNes.Core/Mapper/_MapName.cs Normal file
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using static VirtualNes.MMU;
using static VirtualNes.Core.CPU;
using INT = System.Int32;
using BYTE = System.Byte;
using System;
namespace VirtualNes.Core
{
public class _MapName : Mapper
{
public _MapName(NES parent) : base(parent)
{
}
public override void Reset()
{
}
}
}

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