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MAME:MC68000 Register* 更换所有下标取值，改为直接指针运算解引用

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sin365 2025-11-26 17:09:08 +08:00
parent 79ada55c3c
commit f53fcbfee0
5 changed files with 345 additions and 296 deletions
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340
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/BitArithemetic.cs
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@ -16,19 +16,19 @@ namespace cpu.m68000
// switch (size) // switch (size)
// { // {
// case 0: // Byte // case 0: // Byte
// D[dstReg].s8 &= ReadValueB(srcMode, srcReg); // D_ptr_dstReg->s8 &= ReadValueB(srcMode, srcReg);
// pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg]; // pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg];
// N = (D[dstReg].s8 & 0x80) != 0; // N = (D_ptr_dstReg->s8 & 0x80) != 0;
// Z = (D[dstReg].s8 == 0); // Z = (D_ptr_dstReg->s8 == 0);
// return; // return;
// case 1: // Word // case 1: // Word
// D[dstReg].s16 &= ReadValueW(srcMode, srcReg); // D_ptr_dstReg->s16 &= ReadValueW(srcMode, srcReg);
// pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg]; // pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg];
// N = (D[dstReg].s16 & 0x8000) != 0; // N = (D_ptr_dstReg->s16 & 0x8000) != 0;
// Z = (D[dstReg].s16 == 0); // Z = (D_ptr_dstReg->s16 == 0);
// return; // return;
// case 2: // Long // case 2: // Long
// D[dstReg].s32 &= ReadValueL(srcMode, srcReg); // D_ptr_dstReg->s32 &= ReadValueL(srcMode, srcReg);
// if (srcMode == 0 || (srcMode == 7 && srcReg == 4)) // if (srcMode == 0 || (srcMode == 7 && srcReg == 4))
// { // {
// pendingCycles -= 8 + EACyclesL[srcMode, srcReg]; // pendingCycles -= 8 + EACyclesL[srcMode, srcReg];
@ -37,8 +37,8 @@ namespace cpu.m68000
// { // {
// pendingCycles -= 6 + EACyclesL[srcMode, srcReg]; // pendingCycles -= 6 + EACyclesL[srcMode, srcReg];
// } // }
// N = (D[dstReg].s32 & 0x80000000) != 0; // N = (D_ptr_dstReg->s32 & 0x80000000) != 0;
// Z = (D[dstReg].s32 == 0); // Z = (D_ptr_dstReg->s32 == 0);
// return; // return;
// } // }
//} //}
@ -49,24 +49,25 @@ namespace cpu.m68000
int srcMode = (op >> 3) & 0x07; int srcMode = (op >> 3) & 0x07;
int srcReg = op & 0x07; int srcReg = op & 0x07;
Register* D_ptr_dstReg = D + dstReg;
V = false; V = false;
C = false; C = false;
switch (size) switch (size)
{ {
case 0: // Byte case 0: // Byte
D[dstReg].s8 &= ReadValueB(srcMode, srcReg); D_ptr_dstReg->s8 &= ReadValueB(srcMode, srcReg);
pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg]; pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg];
N = (D[dstReg].s8 & 0x80) != 0; N = (D_ptr_dstReg->s8 & 0x80) != 0;
Z = (D[dstReg].s8 == 0); Z = (D_ptr_dstReg->s8 == 0);
return; return;
case 1: // Word case 1: // Word
D[dstReg].s16 &= ReadValueW(srcMode, srcReg); D_ptr_dstReg->s16 &= ReadValueW(srcMode, srcReg);
pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg]; pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg];
N = (D[dstReg].s16 & 0x8000) != 0; N = (D_ptr_dstReg->s16 & 0x8000) != 0;
Z = (D[dstReg].s16 == 0); Z = (D_ptr_dstReg->s16 == 0);
return; return;
case 2: // Long case 2: // Long
D[dstReg].s32 &= ReadValueL(srcMode, srcReg); D_ptr_dstReg->s32 &= ReadValueL(srcMode, srcReg);
if (srcMode == 0 || (srcMode == 7 && srcReg == 4)) if (srcMode == 0 || (srcMode == 7 && srcReg == 4))
{ {
pendingCycles -= 8 + EACyclesL[srcMode, srcReg]; pendingCycles -= 8 + EACyclesL[srcMode, srcReg];
@ -75,8 +76,8 @@ namespace cpu.m68000
{ {
pendingCycles -= 6 + EACyclesL[srcMode, srcReg]; pendingCycles -= 6 + EACyclesL[srcMode, srcReg];
} }
N = (D[dstReg].s32 & 0x80000000) != 0; N = (D_ptr_dstReg->s32 & 0x80000000) != 0;
Z = (D[dstReg].s32 == 0); Z = (D_ptr_dstReg->s32 == 0);
return; return;
} }
} }
@ -91,12 +92,13 @@ namespace cpu.m68000
V = false; V = false;
C = false; C = false;
Register* D_ptr_srcReg = D + srcReg;
switch (size) switch (size)
{ {
case 0: // Byte case 0: // Byte
{ {
sbyte dest = PeekValueB(dstMode, dstReg); sbyte dest = PeekValueB(dstMode, dstReg);
sbyte value = (sbyte)(dest & D[srcReg].s8); sbyte value = (sbyte)(dest & D_ptr_srcReg->s8);
WriteValueB(dstMode, dstReg, value); WriteValueB(dstMode, dstReg, value);
pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg]; pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x80) != 0; N = (value & 0x80) != 0;
@ -106,7 +108,7 @@ namespace cpu.m68000
case 1: // Word case 1: // Word
{ {
short dest = PeekValueW(dstMode, dstReg); short dest = PeekValueW(dstMode, dstReg);
short value = (short)(dest & D[srcReg].s16); short value = (short)(dest & D_ptr_srcReg->s16);
WriteValueW(dstMode, dstReg, value); WriteValueW(dstMode, dstReg, value);
pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg]; pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x8000) != 0; N = (value & 0x8000) != 0;
@ -116,7 +118,7 @@ namespace cpu.m68000
case 2: // Long case 2: // Long
{ {
int dest = PeekValueL(dstMode, dstReg); int dest = PeekValueL(dstMode, dstReg);
int value = dest & D[srcReg].s32; int value = dest & D_ptr_srcReg->s32;
WriteValueL(dstMode, dstReg, value); WriteValueL(dstMode, dstReg, value);
pendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesL[dstMode, dstReg]; pendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesL[dstMode, dstReg];
N = (value & 0x80000000) != 0; N = (value & 0x80000000) != 0;
@ -194,12 +196,13 @@ namespace cpu.m68000
V = false; V = false;
C = false; C = false;
Register* D_ptr_srcReg = D + srcReg;
switch (size) switch (size)
{ {
case 0: // Byte case 0: // Byte
{ {
sbyte dest = PeekValueB(dstMode, dstReg); sbyte dest = PeekValueB(dstMode, dstReg);
sbyte value = (sbyte)(dest ^ D[srcReg].s8); sbyte value = (sbyte)(dest ^ D_ptr_srcReg->s8);
WriteValueB(dstMode, dstReg, value); WriteValueB(dstMode, dstReg, value);
pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg]; pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x80) != 0; N = (value & 0x80) != 0;
@ -209,7 +212,7 @@ namespace cpu.m68000
case 1: // Word case 1: // Word
{ {
short dest = PeekValueW(dstMode, dstReg); short dest = PeekValueW(dstMode, dstReg);
short value = (short)(dest ^ D[srcReg].s16); short value = (short)(dest ^ D_ptr_srcReg->s16);
WriteValueW(dstMode, dstReg, value); WriteValueW(dstMode, dstReg, value);
pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg]; pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x8000) != 0; N = (value & 0x8000) != 0;
@ -219,7 +222,7 @@ namespace cpu.m68000
case 2: // Long case 2: // Long
{ {
int dest = PeekValueL(dstMode, dstReg); int dest = PeekValueL(dstMode, dstReg);
int value = dest ^ D[srcReg].s32; int value = dest ^ D_ptr_srcReg->s32;
WriteValueL(dstMode, dstReg, value); WriteValueL(dstMode, dstReg, value);
pendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesL[dstMode, dstReg]; pendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesL[dstMode, dstReg];
N = (value & 0x80000000) != 0; N = (value & 0x80000000) != 0;
@ -295,22 +298,23 @@ namespace cpu.m68000
V = false; V = false;
C = false; C = false;
Register* D_ptr_dstReg = D + dstReg;
switch (size) switch (size)
{ {
case 0: // Byte case 0: // Byte
D[dstReg].s8 |= ReadValueB(srcMode, srcReg); D_ptr_dstReg->s8 |= ReadValueB(srcMode, srcReg);
pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg]; pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg];
N = (D[dstReg].s8 & 0x80) != 0; N = (D_ptr_dstReg->s8 & 0x80) != 0;
Z = (D[dstReg].s8 == 0); Z = (D_ptr_dstReg->s8 == 0);
return; return;
case 1: // Word case 1: // Word
D[dstReg].s16 |= ReadValueW(srcMode, srcReg); D_ptr_dstReg->s16 |= ReadValueW(srcMode, srcReg);
pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg]; pendingCycles -= (srcMode == 0) ? 4 : 4 + EACyclesBW[srcMode, srcReg];
N = (D[dstReg].s16 & 0x8000) != 0; N = (D_ptr_dstReg->s16 & 0x8000) != 0;
Z = (D[dstReg].s16 == 0); Z = (D_ptr_dstReg->s16 == 0);
return; return;
case 2: // Long case 2: // Long
D[dstReg].s32 |= ReadValueL(srcMode, srcReg); D_ptr_dstReg->s32 |= ReadValueL(srcMode, srcReg);
if (srcMode == 0 || (srcMode == 7 && srcReg == 4)) if (srcMode == 0 || (srcMode == 7 && srcReg == 4))
{ {
pendingCycles -= 8 + EACyclesL[srcMode, srcReg]; pendingCycles -= 8 + EACyclesL[srcMode, srcReg];
@ -319,8 +323,8 @@ namespace cpu.m68000
{ {
pendingCycles -= 6 + EACyclesL[srcMode, srcReg]; pendingCycles -= 6 + EACyclesL[srcMode, srcReg];
} }
N = (D[dstReg].s32 & 0x80000000) != 0; N = (D_ptr_dstReg->s32 & 0x80000000) != 0;
Z = (D[dstReg].s32 == 0); Z = (D_ptr_dstReg->s32 == 0);
return; return;
} }
} }
@ -336,12 +340,13 @@ namespace cpu.m68000
V = false; V = false;
C = false; C = false;
Register* D_ptr_srcReg = D + srcReg;
switch (size) switch (size)
{ {
case 0: // Byte case 0: // Byte
{ {
sbyte dest = PeekValueB(dstMode, dstReg); sbyte dest = PeekValueB(dstMode, dstReg);
sbyte value = (sbyte)(dest | D[srcReg].s8); sbyte value = (sbyte)(dest | D_ptr_srcReg->s8);
WriteValueB(dstMode, dstReg, value); WriteValueB(dstMode, dstReg, value);
pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg]; pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x80) != 0; N = (value & 0x80) != 0;
@ -351,7 +356,7 @@ namespace cpu.m68000
case 1: // Word case 1: // Word
{ {
short dest = PeekValueW(dstMode, dstReg); short dest = PeekValueW(dstMode, dstReg);
short value = (short)(dest | D[srcReg].s16); short value = (short)(dest | D_ptr_srcReg->s16);
WriteValueW(dstMode, dstReg, value); WriteValueW(dstMode, dstReg, value);
pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg]; pendingCycles -= (dstMode == 0) ? 4 : 8 + EACyclesBW[dstMode, dstReg];
N = (value & 0x8000) != 0; N = (value & 0x8000) != 0;
@ -361,7 +366,7 @@ namespace cpu.m68000
case 2: // Long case 2: // Long
{ {
int dest = PeekValueL(dstMode, dstReg); int dest = PeekValueL(dstMode, dstReg);
int value = dest | D[srcReg].s32; int value = dest | D_ptr_srcReg->s32;
WriteValueL(dstMode, dstReg, value); WriteValueL(dstMode, dstReg, value);
pendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesL[dstMode, dstReg]; pendingCycles -= (dstMode == 0) ? 8 : 12 + EACyclesL[dstMode, dstReg];
N = (value & 0x80000000) != 0; N = (value & 0x80000000) != 0;
@ -478,42 +483,43 @@ namespace cpu.m68000
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
Register* D_ptr_rot = D + rot;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D_ptr_rot->s32 & 63;
V = false; V = false;
C = false; C = false;
Register* D_ptr_reg = D + reg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = X = (D[reg].u8 & 0x80) != 0; C = X = (D_ptr_reg->u8 & 0x80) != 0;
D[reg].u8 <<= 1; D_ptr_reg->u8 <<= 1;
} }
N = (D[reg].s8 & 0x80) != 0; N = (D_ptr_reg->s8 & 0x80) != 0;
Z = D[reg].u8 == 0; Z = D_ptr_reg->u8 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 1: // word case 1: // word
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = X = (D[reg].u16 & 0x8000) != 0; C = X = (D_ptr_reg->u16 & 0x8000) != 0;
D[reg].u16 <<= 1; D_ptr_reg->u16 <<= 1;
} }
N = (D[reg].s16 & 0x8000) != 0; N = (D_ptr_reg->s16 & 0x8000) != 0;
Z = D[reg].u16 == 0; Z = D_ptr_reg->u16 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 2: // long case 2: // long
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = X = (D[reg].u32 & 0x80000000) != 0; C = X = (D_ptr_reg->u32 & 0x80000000) != 0;
D[reg].u32 <<= 1; D_ptr_reg->u32 <<= 1;
} }
N = (D[reg].s32 & 0x80000000) != 0; N = (D_ptr_reg->s32 & 0x80000000) != 0;
Z = D[reg].u32 == 0; Z = D_ptr_reg->u32 == 0;
pendingCycles -= 8 + (rot * 2); pendingCycles -= 8 + (rot * 2);
return; return;
} }
@ -551,42 +557,43 @@ namespace cpu.m68000
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
Register* D_ptr_rot = D + rot;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D_ptr_rot->s32 & 63;
V = false; V = false;
C = false; C = false;
Register* D_ptr_reg = D + reg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = X = (D[reg].u8 & 1) != 0; C = X = (D_ptr_reg->u8 & 1) != 0;
D[reg].u8 >>= 1; D_ptr_reg->u8 >>= 1;
} }
N = (D[reg].s8 & 0x80) != 0; N = (D_ptr_reg->s8 & 0x80) != 0;
Z = D[reg].u8 == 0; Z = D_ptr_reg->u8 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 1: // word case 1: // word
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = X = (D[reg].u16 & 1) != 0; C = X = (D_ptr_reg->u16 & 1) != 0;
D[reg].u16 >>= 1; D_ptr_reg->u16 >>= 1;
} }
N = (D[reg].s16 & 0x8000) != 0; N = (D_ptr_reg->s16 & 0x8000) != 0;
Z = D[reg].u16 == 0; Z = D_ptr_reg->u16 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 2: // long case 2: // long
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = X = (D[reg].u32 & 1) != 0; C = X = (D_ptr_reg->u32 & 1) != 0;
D[reg].u32 >>= 1; D_ptr_reg->u32 >>= 1;
} }
N = (D[reg].s32 & 0x80000000) != 0; N = (D_ptr_reg->s32 & 0x80000000) != 0;
Z = D[reg].u32 == 0; Z = D_ptr_reg->u32 == 0;
pendingCycles -= 8 + (rot * 2); pendingCycles -= 8 + (rot * 2);
return; return;
} }
@ -625,48 +632,49 @@ namespace cpu.m68000
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
Register* D_ptr_rot = D + rot;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D_ptr_rot->s32 & 63;
V = false; V = false;
C = false; C = false;
Register* D_ptr_reg = D + reg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
bool msb = D[reg].s8 < 0; bool msb = D_ptr_reg->s8 < 0;
C = X = (D[reg].u8 & 0x80) != 0; C = X = (D_ptr_reg->u8 & 0x80) != 0;
D[reg].s8 <<= 1; D_ptr_reg->s8 <<= 1;
V |= (D[reg].s8 < 0) != msb; V |= (D_ptr_reg->s8 < 0) != msb;
} }
N = (D[reg].s8 & 0x80) != 0; N = (D_ptr_reg->s8 & 0x80) != 0;
Z = D[reg].u8 == 0; Z = D_ptr_reg->u8 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 1: // word case 1: // word
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
bool msb = D[reg].s16 < 0; bool msb = D_ptr_reg->s16 < 0;
C = X = (D[reg].u16 & 0x8000) != 0; C = X = (D_ptr_reg->u16 & 0x8000) != 0;
D[reg].s16 <<= 1; D_ptr_reg->s16 <<= 1;
V |= (D[reg].s16 < 0) != msb; V |= (D_ptr_reg->s16 < 0) != msb;
} }
N = (D[reg].s16 & 0x8000) != 0; N = (D_ptr_reg->s16 & 0x8000) != 0;
Z = D[reg].u16 == 0; Z = D_ptr_reg->u16 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 2: // long case 2: // long
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
bool msb = D[reg].s32 < 0; bool msb = D_ptr_reg->s32 < 0;
C = X = (D[reg].u32 & 0x80000000) != 0; C = X = (D_ptr_reg->u32 & 0x80000000) != 0;
D[reg].s32 <<= 1; D_ptr_reg->s32 <<= 1;
V |= (D[reg].s32 < 0) != msb; V |= (D_ptr_reg->s32 < 0) != msb;
} }
N = (D[reg].s32 & 0x80000000) != 0; N = (D_ptr_reg->s32 & 0x80000000) != 0;
Z = D[reg].u32 == 0; Z = D_ptr_reg->u32 == 0;
pendingCycles -= 8 + (rot * 2); pendingCycles -= 8 + (rot * 2);
return; return;
} }
@ -705,48 +713,49 @@ namespace cpu.m68000
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
Register* D_ptr_rot = D + rot;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D_ptr_rot->s32 & 63;
V = false; V = false;
C = false; C = false;
Register* D_ptr_reg = D + reg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
bool msb = D[reg].s8 < 0; bool msb = D_ptr_reg->s8 < 0;
C = X = (D[reg].u8 & 1) != 0; C = X = (D_ptr_reg->u8 & 1) != 0;
D[reg].s8 >>= 1; D_ptr_reg->s8 >>= 1;
V |= (D[reg].s8 < 0) != msb; V |= (D_ptr_reg->s8 < 0) != msb;
} }
N = (D[reg].s8 & 0x80) != 0; N = (D_ptr_reg->s8 & 0x80) != 0;
Z = D[reg].u8 == 0; Z = D_ptr_reg->u8 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 1: // word case 1: // word
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
bool msb = D[reg].s16 < 0; bool msb = D_ptr_reg->s16 < 0;
C = X = (D[reg].u16 & 1) != 0; C = X = (D_ptr_reg->u16 & 1) != 0;
D[reg].s16 >>= 1; D_ptr_reg->s16 >>= 1;
V |= (D[reg].s16 < 0) != msb; V |= (D_ptr_reg->s16 < 0) != msb;
} }
N = (D[reg].s16 & 0x8000) != 0; N = (D_ptr_reg->s16 & 0x8000) != 0;
Z = D[reg].u16 == 0; Z = D_ptr_reg->u16 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 2: // long case 2: // long
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
bool msb = D[reg].s32 < 0; bool msb = D_ptr_reg->s32 < 0;
C = X = (D[reg].u32 & 1) != 0; C = X = (D_ptr_reg->u32 & 1) != 0;
D[reg].s32 >>= 1; D_ptr_reg->s32 >>= 1;
V |= (D[reg].s32 < 0) != msb; V |= (D_ptr_reg->s32 < 0) != msb;
} }
N = (D[reg].s32 & 0x80000000) != 0; N = (D_ptr_reg->s32 & 0x80000000) != 0;
Z = D[reg].u32 == 0; Z = D_ptr_reg->u32 == 0;
pendingCycles -= 8 + (rot * 2); pendingCycles -= 8 + (rot * 2);
return; return;
} }
@ -788,42 +797,43 @@ namespace cpu.m68000
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
Register* D_ptr_rot = D + rot;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D_ptr_rot->s32 & 63;
V = false; V = false;
C = false; C = false;
Register* D_ptr_reg = D + reg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].u8 & 0x80) != 0; C = (D_ptr_reg->u8 & 0x80) != 0;
D[reg].u8 = (byte)((D[reg].u8 << 1) | (D[reg].u8 >> 7)); D_ptr_reg->u8 = (byte)((D_ptr_reg->u8 << 1) | (D_ptr_reg->u8 >> 7));
} }
N = (D[reg].s8 & 0x80) != 0; N = (D_ptr_reg->s8 & 0x80) != 0;
Z = D[reg].u8 == 0; Z = D_ptr_reg->u8 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 1: // word case 1: // word
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].u16 & 0x8000) != 0; C = (D_ptr_reg->u16 & 0x8000) != 0;
D[reg].u16 = (ushort)((D[reg].u16 << 1) | (D[reg].u16 >> 15)); D_ptr_reg->u16 = (ushort)((D_ptr_reg->u16 << 1) | (D_ptr_reg->u16 >> 15));
} }
N = (D[reg].s16 & 0x8000) != 0; N = (D_ptr_reg->s16 & 0x8000) != 0;
Z = D[reg].u16 == 0; Z = D_ptr_reg->u16 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 2: // long case 2: // long
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].u32 & 0x80000000) != 0; C = (D_ptr_reg->u32 & 0x80000000) != 0;
D[reg].u32 = ((D[reg].u32 << 1) | (D[reg].u32 >> 31)); D_ptr_reg->u32 = ((D_ptr_reg->u32 << 1) | (D_ptr_reg->u32 >> 31));
} }
N = (D[reg].s32 & 0x80000000) != 0; N = (D_ptr_reg->s32 & 0x80000000) != 0;
Z = D[reg].u32 == 0; Z = D_ptr_reg->u32 == 0;
pendingCycles -= 8 + (rot * 2); pendingCycles -= 8 + (rot * 2);
return; return;
} }
@ -861,42 +871,43 @@ namespace cpu.m68000
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
Register* D_ptr_rot = D + rot;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D_ptr_rot->s32 & 63;
V = false; V = false;
C = false; C = false;
Register* D_ptr_reg = D + reg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].u8 & 1) != 0; C = (D_ptr_reg->u8 & 1) != 0;
D[reg].u8 = (byte)((D[reg].u8 >> 1) | (D[reg].u8 << 7)); D_ptr_reg->u8 = (byte)((D_ptr_reg->u8 >> 1) | (D_ptr_reg->u8 << 7));
} }
N = (D[reg].s8 & 0x80) != 0; N = (D_ptr_reg->s8 & 0x80) != 0;
Z = D[reg].u8 == 0; Z = D_ptr_reg->u8 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 1: // word case 1: // word
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].u16 & 1) != 0; C = (D_ptr_reg->u16 & 1) != 0;
D[reg].u16 = (ushort)((D[reg].u16 >> 1) | (D[reg].u16 << 15)); D_ptr_reg->u16 = (ushort)((D_ptr_reg->u16 >> 1) | (D_ptr_reg->u16 << 15));
} }
N = (D[reg].s16 & 0x8000) != 0; N = (D_ptr_reg->s16 & 0x8000) != 0;
Z = D[reg].u16 == 0; Z = D_ptr_reg->u16 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 2: // long case 2: // long
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].u32 & 1) != 0; C = (D_ptr_reg->u32 & 1) != 0;
D[reg].u32 = ((D[reg].u32 >> 1) | (D[reg].u32 << 31)); D_ptr_reg->u32 = ((D_ptr_reg->u32 >> 1) | (D_ptr_reg->u32 << 31));
} }
N = (D[reg].s32 & 0x80000000) != 0; N = (D_ptr_reg->s32 & 0x80000000) != 0;
Z = D[reg].u32 == 0; Z = D_ptr_reg->u32 == 0;
pendingCycles -= 8 + (rot * 2); pendingCycles -= 8 + (rot * 2);
return; return;
} }
@ -934,45 +945,46 @@ namespace cpu.m68000
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
Register* D_ptr_rot = D + rot;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D_ptr_rot->s32 & 63;
C = X; C = X;
V = false; V = false;
Register* D_ptr_reg = D + reg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].u8 & 0x80) != 0; C = (D_ptr_reg->u8 & 0x80) != 0;
D[reg].u8 = (byte)((D[reg].u8 << 1) | (X ? 1 : 0)); D_ptr_reg->u8 = (byte)((D_ptr_reg->u8 << 1) | (X ? 1 : 0));
X = C; X = C;
} }
N = (D[reg].s8 & 0x80) != 0; N = (D_ptr_reg->s8 & 0x80) != 0;
Z = D[reg].s8 == 0; Z = D_ptr_reg->s8 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 1: // word case 1: // word
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].u16 & 0x8000) != 0; C = (D_ptr_reg->u16 & 0x8000) != 0;
D[reg].u16 = (ushort)((D[reg].u16 << 1) | (X ? 1 : 0)); D_ptr_reg->u16 = (ushort)((D_ptr_reg->u16 << 1) | (X ? 1 : 0));
X = C; X = C;
} }
N = (D[reg].s16 & 0x8000) != 0; N = (D_ptr_reg->s16 & 0x8000) != 0;
Z = D[reg].s16 == 0; Z = D_ptr_reg->s16 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 2: // long case 2: // long
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].s32 & 0x80000000) != 0; C = (D_ptr_reg->s32 & 0x80000000) != 0;
D[reg].s32 = ((D[reg].s32 << 1) | (X ? 1 : 0)); D_ptr_reg->s32 = ((D_ptr_reg->s32 << 1) | (X ? 1 : 0));
X = C; X = C;
} }
N = (D[reg].s32 & 0x80000000) != 0; N = (D_ptr_reg->s32 & 0x80000000) != 0;
Z = D[reg].s32 == 0; Z = D_ptr_reg->s32 == 0;
pendingCycles -= 8 + (rot * 2); pendingCycles -= 8 + (rot * 2);
return; return;
} }
@ -1013,45 +1025,46 @@ namespace cpu.m68000
int m = (op >> 5) & 1; int m = (op >> 5) & 1;
int reg = op & 7; int reg = op & 7;
Register* D_ptr_rot = D + rot;
if (m == 0 && rot == 0) rot = 8; if (m == 0 && rot == 0) rot = 8;
else if (m == 1) rot = D[rot].s32 & 63; else if (m == 1) rot = D_ptr_rot->s32 & 63;
C = X; C = X;
V = false; V = false;
Register* D_ptr_reg = D + reg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].u8 & 1) != 0; C = (D_ptr_reg->u8 & 1) != 0;
D[reg].u8 = (byte)((D[reg].u8 >> 1) | (X ? 0x80 : 0)); D_ptr_reg->u8 = (byte)((D_ptr_reg->u8 >> 1) | (X ? 0x80 : 0));
X = C; X = C;
} }
N = (D[reg].s8 & 0x80) != 0; N = (D_ptr_reg->s8 & 0x80) != 0;
Z = D[reg].s8 == 0; Z = D_ptr_reg->s8 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 1: // word case 1: // word
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].u16 & 1) != 0; C = (D_ptr_reg->u16 & 1) != 0;
D[reg].u16 = (ushort)((D[reg].u16 >> 1) | (X ? 0x8000 : 0)); D_ptr_reg->u16 = (ushort)((D_ptr_reg->u16 >> 1) | (X ? 0x8000 : 0));
X = C; X = C;
} }
N = (D[reg].s16 & 0x8000) != 0; N = (D_ptr_reg->s16 & 0x8000) != 0;
Z = D[reg].s16 == 0; Z = D_ptr_reg->s16 == 0;
pendingCycles -= 6 + (rot * 2); pendingCycles -= 6 + (rot * 2);
return; return;
case 2: // long case 2: // long
for (int i = 0; i < rot; i++) for (int i = 0; i < rot; i++)
{ {
C = (D[reg].s32 & 1) != 0; C = (D_ptr_reg->s32 & 1) != 0;
D[reg].u32 = ((D[reg].u32 >> 1) | (X ? 0x80000000 : 0)); D_ptr_reg->u32 = ((D_ptr_reg->u32 >> 1) | (X ? 0x80000000 : 0));
X = C; X = C;
} }
N = (D[reg].s32 & 0x80000000) != 0; N = (D_ptr_reg->s32 & 0x80000000) != 0;
Z = D[reg].s32 == 0; Z = D_ptr_reg->s32 == 0;
pendingCycles -= 8 + (rot * 2); pendingCycles -= 8 + (rot * 2);
return; return;
} }
@ -1087,10 +1100,11 @@ namespace cpu.m68000
void SWAP() void SWAP()
{ {
int reg = op & 7; int reg = op & 7;
D[reg].u32 = (D[reg].u32 << 16) | (D[reg].u32 >> 16); Register* D_ptr_reg = D + reg;
D_ptr_reg->u32 = (D_ptr_reg->u32 << 16) | (D_ptr_reg->u32 >> 16);
V = C = false; V = C = false;
Z = D[reg].u32 == 0; Z = D_ptr_reg->u32 == 0;
N = (D[reg].s32 & 0x80000000) != 0; N = (D_ptr_reg->s32 & 0x80000000) != 0;
pendingCycles -= 4; pendingCycles -= 4;
} }

39
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/DataMovement.cs
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@ -125,18 +125,19 @@ namespace cpu.m68000
int size = ((op >> 6) & 0x01); int size = ((op >> 6) & 0x01);
int aReg = (op & 0x07); int aReg = (op & 0x07);
Register* A_ptr_aReg = A + aReg; Register* A_ptr_aReg = A + aReg;
Register* D_ptr_dReg = D + dReg;
if (dir == 0 && size == 0) if (dir == 0 && size == 0)
{ {
int ea; int ea;
ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2; ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2;
D[dReg].u32 = (D[dReg].u32 & 0xffff0000) | (ushort)(((byte)ReadByte(ea) << 8) + (byte)ReadByte(ea + 2)); D_ptr_dReg->u32 = (D_ptr_dReg->u32 & 0xffff0000) | (ushort)(((byte)ReadByte(ea) << 8) + (byte)ReadByte(ea + 2));
pendingCycles -= 16; pendingCycles -= 16;
} }
else if (dir == 0 && size == 1) else if (dir == 0 && size == 1)
{ {
int ea; int ea;
ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2; ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2;
D[dReg].u32 = (uint)(((byte)ReadByte(ea) << 24) + ((byte)ReadByte(ea + 2) << 16) + ((byte)ReadByte(ea + 4) << 8) + (byte)ReadByte(ea + 6)); D_ptr_dReg->u32 = (uint)(((byte)ReadByte(ea) << 24) + ((byte)ReadByte(ea + 2) << 16) + ((byte)ReadByte(ea + 4) << 8) + (byte)ReadByte(ea + 6));
pendingCycles -= 24; pendingCycles -= 24;
} }
else if (dir == 1 && size == 0) else if (dir == 1 && size == 0)
@ -144,7 +145,7 @@ namespace cpu.m68000
uint src; uint src;
int ea; int ea;
ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2; ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2;
src = D[dReg].u32; src = D_ptr_dReg->u32;
WriteByte(ea, (sbyte)((src >> 8) & 0xff)); WriteByte(ea, (sbyte)((src >> 8) & 0xff));
WriteByte(ea + 2, (sbyte)(src & 0xff)); WriteByte(ea + 2, (sbyte)(src & 0xff));
pendingCycles -= 16; pendingCycles -= 16;
@ -154,7 +155,7 @@ namespace cpu.m68000
uint src; uint src;
int ea; int ea;
ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2; ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2;
src = D[dReg].u32; src = D_ptr_dReg->u32;
WriteByte(ea, (sbyte)((src >> 24) & 0xff)); WriteByte(ea, (sbyte)((src >> 24) & 0xff));
WriteByte(ea + 2, (sbyte)((src >> 16) & 0xff)); WriteByte(ea + 2, (sbyte)((src >> 16) & 0xff));
WriteByte(ea + 4, (sbyte)((src >> 8) & 0xff)); WriteByte(ea + 4, (sbyte)((src >> 8) & 0xff));
@ -262,7 +263,7 @@ namespace cpu.m68000
if ((registers & 1) == 1) if ((registers & 1) == 1)
{ {
address -= 2; address -= 2;
WriteWord(address, D[i].s16); WriteWord(address, (D + i)->s16);
regCount++; regCount++;
} }
registers >>= 1; registers >>= 1;
@ -275,7 +276,7 @@ namespace cpu.m68000
{ {
if ((registers & 1) == 1) if ((registers & 1) == 1)
{ {
WriteWord(address, D[i].s16); WriteWord(address, (D + i)->s16);
address += 2; address += 2;
regCount++; regCount++;
} }
@ -314,7 +315,7 @@ namespace cpu.m68000
if ((registers & 1) == 1) if ((registers & 1) == 1)
{ {
address -= 4; address -= 4;
WriteLong(address, D[i].s32); WriteLong(address, (D + i)->s32);
regCount++; regCount++;
} }
registers >>= 1; registers >>= 1;
@ -327,7 +328,7 @@ namespace cpu.m68000
{ {
if ((registers & 1) == 1) if ((registers & 1) == 1)
{ {
WriteLong(address, D[i].s32); WriteLong(address, (D + i)->s32);
address += 4; address += 4;
regCount++; regCount++;
} }
@ -385,11 +386,11 @@ namespace cpu.m68000
{ {
if (srcMode == 7 && (srcReg == 2 || srcReg == 3)) if (srcMode == 7 && (srcReg == 2 || srcReg == 3))
{ {
D[i].s32 = ReadPcrelWord(address); (D + i)->s32 = ReadPcrelWord(address);
} }
else else
{ {
D[i].s32 = ReadWord(address); (D + i)->s32 = ReadWord(address);
} }
address += 2; address += 2;
regCount++; regCount++;
@ -426,11 +427,11 @@ namespace cpu.m68000
{ {
if (srcMode == 7 && (srcReg == 2 || srcReg == 3)) if (srcMode == 7 && (srcReg == 2 || srcReg == 3))
{ {
D[i].s32 = ReadPcrelLong(address); (D + i)->s32 = ReadPcrelLong(address);
} }
else else
{ {
D[i].s32 = ReadLong(address); (D + i)->s32 = ReadLong(address);
} }
address += 4; address += 4;
regCount++; regCount++;
@ -527,18 +528,18 @@ namespace cpu.m68000
{ {
int size = (op >> 6) & 1; int size = (op >> 6) & 1;
int reg = op & 7; int reg = op & 7;
Register* D_ptr_reg = D + reg;
switch (size) switch (size)
{ {
case 0: // ext.w case 0: // ext.w
D[reg].s16 = D[reg].s8; D_ptr_reg->s16 = D_ptr_reg->s8;
N = (D[reg].s16 & 0x8000) != 0; N = (D_ptr_reg->s16 & 0x8000) != 0;
Z = (D[reg].s16 == 0); Z = (D_ptr_reg->s16 == 0);
break; break;
case 1: // ext.l case 1: // ext.l
D[reg].s32 = D[reg].s16; D_ptr_reg->s32 = D_ptr_reg->s16;
N = (D[reg].s32 & 0x80000000) != 0; N = (D_ptr_reg->s32 & 0x80000000) != 0;
Z = (D[reg].s32 == 0); Z = (D_ptr_reg->s32 == 0);
break; break;
} }

180
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/IntegerMath.cs
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@ -11,44 +11,45 @@ namespace cpu.m68000
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
Register* D_ptr_Dreg = D + Dreg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
{ {
sbyte value = ReadValueB(mode, reg); sbyte value = ReadValueB(mode, reg);
int result = D[Dreg].s8 + value; int result = D_ptr_Dreg->s8 + value;
int uresult = D[Dreg].u8 + (byte)value; int uresult = D_ptr_Dreg->u8 + (byte)value;
X = C = (uresult & 0x100) != 0; X = C = (uresult & 0x100) != 0;
V = result > sbyte.MaxValue || result < sbyte.MinValue; V = result > sbyte.MaxValue || result < sbyte.MinValue;
N = (result & 0x80) != 0; N = (result & 0x80) != 0;
Z = (result & 0xff) == 0; Z = (result & 0xff) == 0;
D[Dreg].s8 = (sbyte)result; D_ptr_Dreg->s8 = (sbyte)result;
pendingCycles -= 4 + EACyclesBW[mode, reg]; pendingCycles -= 4 + EACyclesBW[mode, reg];
return; return;
} }
case 1: // word case 1: // word
{ {
short value = ReadValueW(mode, reg); short value = ReadValueW(mode, reg);
int result = D[Dreg].s16 + value; int result = D_ptr_Dreg->s16 + value;
int uresult = D[Dreg].u16 + (ushort)value; int uresult = D_ptr_Dreg->u16 + (ushort)value;
X = C = (uresult & 0x10000) != 0; X = C = (uresult & 0x10000) != 0;
V = result > short.MaxValue || result < short.MinValue; V = result > short.MaxValue || result < short.MinValue;
N = (result & 0x8000) != 0; N = (result & 0x8000) != 0;
Z = (result & 0xffff) == 0; Z = (result & 0xffff) == 0;
D[Dreg].s16 = (short)result; D_ptr_Dreg->s16 = (short)result;
pendingCycles -= 4 + EACyclesBW[mode, reg]; pendingCycles -= 4 + EACyclesBW[mode, reg];
return; return;
} }
case 2: // long case 2: // long
{ {
int value = ReadValueL(mode, reg); int value = ReadValueL(mode, reg);
long result = (long)D[Dreg].s32 + (long)value; long result = (long)D_ptr_Dreg->s32 + (long)value;
ulong uresult = (ulong)D[Dreg].u32 + ((ulong)(uint)value); ulong uresult = (ulong)D_ptr_Dreg->u32 + ((ulong)(uint)value);
X = C = (uresult & 0x100000000) != 0; X = C = (uresult & 0x100000000) != 0;
V = result > int.MaxValue || result < int.MinValue; V = result > int.MaxValue || result < int.MinValue;
N = (result & 0x80000000) != 0; N = (result & 0x80000000) != 0;
Z = (uint)result == 0; Z = (uint)result == 0;
D[Dreg].s32 = (int)result; D_ptr_Dreg->s32 = (int)result;
if (mode == 0 || mode == 1 || (mode == 7 && reg == 4)) if (mode == 0 || mode == 1 || (mode == 7 && reg == 4))
{ {
pendingCycles -= 8 + EACyclesL[mode, reg]; pendingCycles -= 8 + EACyclesL[mode, reg];
@ -69,13 +70,14 @@ namespace cpu.m68000
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
Register* D_ptr_Dreg = D + Dreg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
{ {
sbyte value = PeekValueB(mode, reg); sbyte value = PeekValueB(mode, reg);
int result = value + D[Dreg].s8; int result = value + D_ptr_Dreg->s8;
int uresult = (byte)value + D[Dreg].u8; int uresult = (byte)value + D_ptr_Dreg->u8;
X = C = (uresult & 0x100) != 0; X = C = (uresult & 0x100) != 0;
V = result > sbyte.MaxValue || result < sbyte.MinValue; V = result > sbyte.MaxValue || result < sbyte.MinValue;
N = (result & 0x80) != 0; N = (result & 0x80) != 0;
@ -87,8 +89,8 @@ namespace cpu.m68000
case 1: // word case 1: // word
{ {
short value = PeekValueW(mode, reg); short value = PeekValueW(mode, reg);
int result = value + D[Dreg].s16; int result = value + D_ptr_Dreg->s16;
int uresult = (ushort)value + D[Dreg].u16; int uresult = (ushort)value + D_ptr_Dreg->u16;
X = C = (uresult & 0x10000) != 0; X = C = (uresult & 0x10000) != 0;
V = result > short.MaxValue || result < short.MinValue; V = result > short.MaxValue || result < short.MinValue;
N = (result & 0x8000) != 0; N = (result & 0x8000) != 0;
@ -100,8 +102,8 @@ namespace cpu.m68000
case 2: // long case 2: // long
{ {
int value = PeekValueL(mode, reg); int value = PeekValueL(mode, reg);
long result = (long)value + (long)D[Dreg].s32; long result = (long)value + (long)D_ptr_Dreg->s32;
ulong uresult = ((ulong)(uint)value) + (ulong)D[Dreg].u32; ulong uresult = ((ulong)(uint)value) + (ulong)D_ptr_Dreg->u32;
X = C = (uresult & 0x100000000) != 0; X = C = (uresult & 0x100000000) != 0;
V = result > int.MaxValue || result < int.MinValue; V = result > int.MaxValue || result < int.MinValue;
N = (result & 0x80000000) != 0; N = (result & 0x80000000) != 0;
@ -279,44 +281,45 @@ namespace cpu.m68000
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
Register* D_ptr_dReg = D + dReg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
{ {
sbyte a = D[dReg].s8; sbyte a = D_ptr_dReg->s8;
sbyte b = ReadValueB(mode, reg); sbyte b = ReadValueB(mode, reg);
int result = a - b; int result = a - b;
X = C = ((a < b) ^ ((a ^ b) >= 0) == false); X = C = ((a < b) ^ ((a ^ b) >= 0) == false);
V = result > sbyte.MaxValue || result < sbyte.MinValue; V = result > sbyte.MaxValue || result < sbyte.MinValue;
N = (result & 0x80) != 0; N = (result & 0x80) != 0;
Z = result == 0; Z = result == 0;
D[dReg].s8 = (sbyte)result; D_ptr_dReg->s8 = (sbyte)result;
pendingCycles -= 4 + EACyclesBW[mode, reg]; pendingCycles -= 4 + EACyclesBW[mode, reg];
return; return;
} }
case 1: // word case 1: // word
{ {
short a = D[dReg].s16; short a = D_ptr_dReg->s16;
short b = ReadValueW(mode, reg); short b = ReadValueW(mode, reg);
int result = a - b; int result = a - b;
X = C = ((a < b) ^ ((a ^ b) >= 0) == false); X = C = ((a < b) ^ ((a ^ b) >= 0) == false);
V = result > short.MaxValue || result < short.MinValue; V = result > short.MaxValue || result < short.MinValue;
N = (result & 0x8000) != 0; N = (result & 0x8000) != 0;
Z = result == 0; Z = result == 0;
D[dReg].s16 = (short)result; D_ptr_dReg->s16 = (short)result;
pendingCycles -= 4 + EACyclesBW[mode, reg]; pendingCycles -= 4 + EACyclesBW[mode, reg];
return; return;
} }
case 2: // long case 2: // long
{ {
int a = D[dReg].s32; int a = D_ptr_dReg->s32;
int b = ReadValueL(mode, reg); int b = ReadValueL(mode, reg);
long result = (long)a - (long)b; long result = (long)a - (long)b;
X = C = ((a < b) ^ ((a ^ b) >= 0) == false); X = C = ((a < b) ^ ((a ^ b) >= 0) == false);
V = result > int.MaxValue || result < int.MinValue; V = result > int.MaxValue || result < int.MinValue;
N = (result & 0x80000000) != 0; N = (result & 0x80000000) != 0;
Z = result == 0; Z = result == 0;
D[dReg].s32 = (int)result; D_ptr_dReg->s32 = (int)result;
if (mode == 0 || mode == 1 || (mode == 7 && reg == 4)) if (mode == 0 || mode == 1 || (mode == 7 && reg == 4))
{ {
pendingCycles -= 8 + EACyclesL[mode, reg]; pendingCycles -= 8 + EACyclesL[mode, reg];
@ -337,12 +340,13 @@ namespace cpu.m68000
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
Register* D_ptr_dReg = D + dReg;
switch (size) switch (size)
{ {
case 0: // byte case 0: // byte
{ {
sbyte a = PeekValueB(mode, reg); sbyte a = PeekValueB(mode, reg);
sbyte b = D[dReg].s8; sbyte b = D_ptr_dReg->s8;
int result = a - b; int result = a - b;
X = C = ((a < b) ^ ((a ^ b) >= 0) == false); X = C = ((a < b) ^ ((a ^ b) >= 0) == false);
V = result > sbyte.MaxValue || result < sbyte.MinValue; V = result > sbyte.MaxValue || result < sbyte.MinValue;
@ -355,7 +359,7 @@ namespace cpu.m68000
case 1: // word case 1: // word
{ {
short a = PeekValueW(mode, reg); short a = PeekValueW(mode, reg);
short b = D[dReg].s16; short b = D_ptr_dReg->s16;
int result = a - b; int result = a - b;
X = C = ((a < b) ^ ((a ^ b) >= 0) == false); X = C = ((a < b) ^ ((a ^ b) >= 0) == false);
V = result > short.MaxValue || result < short.MinValue; V = result > short.MaxValue || result < short.MinValue;
@ -368,7 +372,7 @@ namespace cpu.m68000
case 2: // long case 2: // long
{ {
int a = PeekValueL(mode, reg); int a = PeekValueL(mode, reg);
int b = D[dReg].s32; int b = D_ptr_dReg->s32;
long result = (long)a - (long)b; long result = (long)a - (long)b;
X = C = ((a < b) ^ ((a ^ b) >= 0) == false); X = C = ((a < b) ^ ((a ^ b) >= 0) == false);
V = result > int.MaxValue || result < int.MinValue; V = result > int.MaxValue || result < int.MinValue;
@ -669,7 +673,7 @@ namespace cpu.m68000
int boundMode = (op >> 3) & 0x07; int boundMode = (op >> 3) & 0x07;
int boundReg = op & 0x07; int boundReg = op & 0x07;
short src, bound; short src, bound;
src = D[dreg].s16; src = (D + dreg)->s16;
bound = ReadValueW(boundMode, boundReg); bound = ReadValueW(boundMode, boundReg);
Z = (src == 0); Z = (src == 0);
V = false; V = false;
@ -746,8 +750,9 @@ namespace cpu.m68000
{ {
int dstReg = (op >> 9) & 0x07; int dstReg = (op >> 9) & 0x07;
int srcReg = op & 0x07; int srcReg = op & 0x07;
uint dst = D[dstReg].u32; Register* D_ptr_dstReg = D + dstReg;
uint src = D[srcReg].u32; uint dst = D_ptr_dstReg->u32;
uint src = (D + srcReg)->u32;
uint res; uint res;
res = (uint)((dst & 0x0f) - (src & 0x0f) - (X ? 1 : 0)); res = (uint)((dst & 0x0f) - (src & 0x0f) - (X ? 1 : 0));
V = false; V = false;
@ -768,7 +773,7 @@ namespace cpu.m68000
} }
res = res & 0xff; res = res & 0xff;
Z &= (res == 0); Z &= (res == 0);
D[dstReg].u32 = (D[dstReg].u32 & 0xffffff00) | res; D_ptr_dstReg->u32 = (D_ptr_dstReg->u32 & 0xffffff00) | res;
pendingCycles -= 6; pendingCycles -= 6;
} }
@ -790,11 +795,11 @@ namespace cpu.m68000
} }
if (dstReg == 7) if (dstReg == 7)
{ {
A_dstReg->u32 -= 2; A_dstReg->u32 -= 2;
} }
else else
{ {
A_dstReg->u32--; A_dstReg->u32--;
} }
src = (uint)ReadByte(A_srcReg->s32); src = (uint)ReadByte(A_srcReg->s32);
dst = (uint)ReadByte(A_dstReg->s32); dst = (uint)ReadByte(A_dstReg->s32);
@ -827,8 +832,10 @@ namespace cpu.m68000
int dstReg = (op >> 9) & 0x07; int dstReg = (op >> 9) & 0x07;
int srcReg = op & 0x07; int srcReg = op & 0x07;
uint src, dst, res; uint src, dst, res;
src = D[srcReg].u32; Register* D_ptr_srcReg = D + srcReg;
dst = D[dstReg].u32; Register* D_ptr_dstReg = D + dstReg;
src = D_ptr_srcReg->u32;
dst = D_ptr_dstReg->u32;
res = (uint)((src & 0x0f) + (dst & 0x0f) + (X ? 1 : 0)); res = (uint)((src & 0x0f) + (dst & 0x0f) + (X ? 1 : 0));
V = (((~res) & 0x80) != 0); V = (((~res) & 0x80) != 0);
if (res > 9) if (res > 9)
@ -845,7 +852,7 @@ namespace cpu.m68000
N = ((res & 0x80) != 0); N = ((res & 0x80) != 0);
res = res & 0xff; res = res & 0xff;
Z &= (res == 0); Z &= (res == 0);
D[dstReg].u32 = (((D[dstReg].u32) & 0xffffff00) | res); D_ptr_dstReg->u32 = (((D_ptr_dstReg->u32) & 0xffffff00) | res);
pendingCycles -= 6; pendingCycles -= 6;
} }
@ -867,11 +874,11 @@ namespace cpu.m68000
} }
if (dstReg == 7) if (dstReg == 7)
{ {
A_dstReg->u32 -= 2; A_dstReg->u32 -= 2;
} }
else else
{ {
A_dstReg->u32--; A_dstReg->u32--;
} }
src = (uint)ReadByte(A_srcReg->s32); src = (uint)ReadByte(A_srcReg->s32);
dst = (uint)ReadByte(A_dstReg->s32); dst = (uint)ReadByte(A_dstReg->s32);
@ -900,10 +907,12 @@ namespace cpu.m68000
{ {
int reg_a = (op >> 9) & 0x07; int reg_a = (op >> 9) & 0x07;
int reg_b = op & 0x07; int reg_b = op & 0x07;
Register* D_ptr_reg_a = D + reg_a;
Register* D_ptr_reg_b = D + reg_b;
uint tmp; uint tmp;
tmp = D[reg_a].u32; tmp = D_ptr_reg_a->u32;
D[reg_a].u32 = D[reg_b].u32; D_ptr_reg_a->u32 = D_ptr_reg_b->u32;
D[reg_b].u32 = tmp; D_ptr_reg_b->u32 = tmp;
pendingCycles -= 6; pendingCycles -= 6;
} }
@ -927,9 +936,10 @@ namespace cpu.m68000
int reg_a = (op >> 9) & 0x07; int reg_a = (op >> 9) & 0x07;
int reg_b = op & 0x07; int reg_b = op & 0x07;
Register* A_ptr_reg_b = A + reg_b; Register* A_ptr_reg_b = A + reg_b;
Register* D_ptr_reg_a = D + reg_a;
uint tmp; uint tmp;
tmp = D[reg_a].u32; tmp = D_ptr_reg_a->u32;
D[reg_a].u32 = A_ptr_reg_b->u32; D_ptr_reg_a->u32 = A_ptr_reg_b->u32;
A_ptr_reg_b->u32 = tmp; A_ptr_reg_b->u32 = tmp;
pendingCycles -= 6; pendingCycles -= 6;
} }
@ -940,12 +950,14 @@ namespace cpu.m68000
int dstReg = (op >> 9) & 0x07; int dstReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03; int size = (op >> 6) & 0x03;
int srcReg = op & 0x07; int srcReg = op & 0x07;
Register* D_ptr_srcReg = D + srcReg;
Register* D_ptr_dstReg = D + dstReg;
switch (size) switch (size)
{ {
case 0: case 0:
{ {
uint src = D[srcReg].u32 & 0xff; uint src = D_ptr_srcReg->u32 & 0xff;
uint dst = D[dstReg].u32 & 0xff; uint dst = D_ptr_dstReg->u32 & 0xff;
uint res; uint res;
res = (uint)(dst + src + (X ? 1 : 0)); res = (uint)(dst + src + (X ? 1 : 0));
N = ((res & 0x80) != 0); N = ((res & 0x80) != 0);
@ -953,14 +965,14 @@ namespace cpu.m68000
X = C = ((res & 0x100) != 0); X = C = ((res & 0x100) != 0);
res = res & 0xff; res = res & 0xff;
Z &= (res == 0); Z &= (res == 0);
D[dstReg].u32 = (D[dstReg].u32 & 0xffffff00) | res; D_ptr_dstReg->u32 = (D_ptr_dstReg->u32 & 0xffffff00) | res;
pendingCycles -= 4; pendingCycles -= 4;
return; return;
} }
case 1: case 1:
{ {
uint src = D[srcReg].u32 & 0xffff; uint src = D_ptr_srcReg->u32 & 0xffff;
uint dst = D[dstReg].u32 & 0xffff; uint dst = D_ptr_dstReg->u32 & 0xffff;
uint res; uint res;
res = (uint)(dst + src + (X ? 1 : 0)); res = (uint)(dst + src + (X ? 1 : 0));
N = ((res & 0x8000) != 0); N = ((res & 0x8000) != 0);
@ -968,21 +980,21 @@ namespace cpu.m68000
X = C = ((res & 0x10000) != 0); X = C = ((res & 0x10000) != 0);
res = res & 0xffff; res = res & 0xffff;
Z &= (res == 0); Z &= (res == 0);
D[dstReg].u32 = (D[dstReg].u32 & 0xffff0000) | res; D_ptr_dstReg->u32 = (D_ptr_dstReg->u32 & 0xffff0000) | res;
pendingCycles -= 4; pendingCycles -= 4;
return; return;
} }
case 2: case 2:
{ {
uint src = D[srcReg].u32; uint src = D_ptr_srcReg->u32;
uint dst = D[dstReg].u32; uint dst = D_ptr_dstReg->u32;
uint res; uint res;
res = (uint)(dst + src + (X ? 1 : 0)); res = (uint)(dst + src + (X ? 1 : 0));
N = ((res & 0x80000000) != 0); N = ((res & 0x80000000) != 0);
V = ((((src ^ res) & (dst ^ res)) & 0x80000000) != 0); V = ((((src ^ res) & (dst ^ res)) & 0x80000000) != 0);
X = C = ((((src & dst) | (~res & (src | dst))) & 0x80000000) != 0); X = C = ((((src & dst) | (~res & (src | dst))) & 0x80000000) != 0);
Z &= (res == 0); Z &= (res == 0);
D[dstReg].u32 = res; D_ptr_dstReg->u32 = res;
pendingCycles -= 8; pendingCycles -= 8;
return; return;
} }
@ -1011,11 +1023,11 @@ namespace cpu.m68000
} }
if (dstReg == 7) if (dstReg == 7)
{ {
A_dstReg->u32 -= 2; A_dstReg->u32 -= 2;
} }
else else
{ {
A_dstReg->u32--; A_dstReg->u32--;
} }
uint src = (uint)ReadByte(A_srcReg->s32); uint src = (uint)ReadByte(A_srcReg->s32);
uint dst = (uint)ReadByte(A_dstReg->s32); uint dst = (uint)ReadByte(A_dstReg->s32);
@ -1034,7 +1046,7 @@ namespace cpu.m68000
{ {
A_srcReg->u32 -= 2; A_srcReg->u32 -= 2;
uint src = (uint)ReadWord(A_srcReg->s32); uint src = (uint)ReadWord(A_srcReg->s32);
A_dstReg->u32 -= 2; A_dstReg->u32 -= 2;
uint dst = (uint)ReadWord(A_dstReg->s32); uint dst = (uint)ReadWord(A_dstReg->s32);
uint res; uint res;
res = (uint)(dst + src + (X ? 1 : 0)); res = (uint)(dst + src + (X ? 1 : 0));
@ -1051,7 +1063,7 @@ namespace cpu.m68000
{ {
A_srcReg->u32 -= 4; A_srcReg->u32 -= 4;
uint src = (uint)ReadLong(A_srcReg->s32); uint src = (uint)ReadLong(A_srcReg->s32);
A_dstReg->u32 -= 4; A_dstReg->u32 -= 4;
uint dst = (uint)ReadWord(A_dstReg->s32); uint dst = (uint)ReadWord(A_dstReg->s32);
uint res; uint res;
res = (uint)(dst + src + (X ? 1 : 0)); res = (uint)(dst + src + (X ? 1 : 0));
@ -1072,12 +1084,14 @@ namespace cpu.m68000
int dstReg = (op >> 9) & 0x07; int dstReg = (op >> 9) & 0x07;
int size = (op >> 6) & 0x03; int size = (op >> 6) & 0x03;
int srcReg = op & 0x07; int srcReg = op & 0x07;
Register* D_ptr_srcReg = D + srcReg;
Register* D_ptr_dstReg = D + dstReg;
switch (size) switch (size)
{ {
case 0: case 0:
{ {
uint src = D[srcReg].u32 & 0xff; uint src = D_ptr_srcReg->u32 & 0xff;
uint dst = D[dstReg].u32 & 0xff; uint dst = D_ptr_dstReg->u32 & 0xff;
uint res; uint res;
res = (uint)(dst - src - (X ? 1 : 0)); res = (uint)(dst - src - (X ? 1 : 0));
N = ((res & 0x80) != 0); N = ((res & 0x80) != 0);
@ -1085,14 +1099,14 @@ namespace cpu.m68000
V = ((((src ^ dst) & (res ^ dst)) & 0x80) != 0); V = ((((src ^ dst) & (res ^ dst)) & 0x80) != 0);
res = res & 0xff; res = res & 0xff;
Z &= (res == 0); Z &= (res == 0);
D[dstReg].u32 = (D[dstReg].u32 & 0xffffff00) | res; D_ptr_dstReg->u32 = (D_ptr_dstReg->u32 & 0xffffff00) | res;
pendingCycles -= 4; pendingCycles -= 4;
return; return;
} }
case 1: case 1:
{ {
uint src = D[srcReg].u32 & 0xffff; uint src = D_ptr_srcReg->u32 & 0xffff;
uint dst = D[dstReg].u32 & 0xffff; uint dst = D_ptr_dstReg->u32 & 0xffff;
uint res; uint res;
res = (uint)(dst - src - (X ? 1 : 0)); res = (uint)(dst - src - (X ? 1 : 0));
N = ((res & 0x8000) != 0); N = ((res & 0x8000) != 0);
@ -1100,21 +1114,21 @@ namespace cpu.m68000
V = ((((src ^ dst) & (res ^ dst)) & 0x8000) != 0); V = ((((src ^ dst) & (res ^ dst)) & 0x8000) != 0);
res = res & 0xffff; res = res & 0xffff;
Z &= (res == 0); Z &= (res == 0);
D[dstReg].u32 = (D[dstReg].u32 & 0xffff0000) | res; D_ptr_dstReg->u32 = (D_ptr_dstReg->u32 & 0xffff0000) | res;
pendingCycles -= 4; pendingCycles -= 4;
return; return;
} }
case 2: case 2:
{ {
uint src = D[srcReg].u32; uint src = D_ptr_srcReg->u32;
uint dst = D[dstReg].u32; uint dst = D_ptr_dstReg->u32;
uint res; uint res;
res = (uint)(dst - src - (X ? 1 : 0)); res = (uint)(dst - src - (X ? 1 : 0));
N = ((res & 0x80000000) != 0); N = ((res & 0x80000000) != 0);
X = C = (((((src & res) | (~dst & (src | res))) >> 23) & 0x100) != 0); X = C = (((((src & res) | (~dst & (src | res))) >> 23) & 0x100) != 0);
V = (((((src ^ dst) & (res ^ dst)) >> 24) & 0x80) != 0); V = (((((src ^ dst) & (res ^ dst)) >> 24) & 0x80) != 0);
Z &= (res == 0); Z &= (res == 0);
D[dstReg].u32 = res; D_ptr_dstReg->u32 = res;
pendingCycles -= 8; pendingCycles -= 8;
return; return;
} }
@ -1143,11 +1157,11 @@ namespace cpu.m68000
} }
if (dstReg == 7) if (dstReg == 7)
{ {
A_dstReg->u32 -= 2; A_dstReg->u32 -= 2;
} }
else else
{ {
A_dstReg->u32--; A_dstReg->u32--;
} }
uint src = (uint)ReadByte(A_srcReg->s32); uint src = (uint)ReadByte(A_srcReg->s32);
uint dst = (uint)ReadByte(A_dstReg->s32); uint dst = (uint)ReadByte(A_dstReg->s32);
@ -1166,7 +1180,7 @@ namespace cpu.m68000
{ {
A_srcReg->u32 -= 2; A_srcReg->u32 -= 2;
uint src = (uint)ReadWord(A_srcReg->s32); uint src = (uint)ReadWord(A_srcReg->s32);
A_dstReg->u32 -= 2; A_dstReg->u32 -= 2;
uint dst = (uint)ReadWord(A_dstReg->s32); uint dst = (uint)ReadWord(A_dstReg->s32);
uint res; uint res;
res = (uint)(dst - src - (X ? 1 : 0)); res = (uint)(dst - src - (X ? 1 : 0));
@ -1183,7 +1197,7 @@ namespace cpu.m68000
{ {
A_srcReg->u32 -= 4; A_srcReg->u32 -= 4;
uint src = (uint)ReadLong(A_srcReg->s32); uint src = (uint)ReadLong(A_srcReg->s32);
A_dstReg->u32 -= 4; A_dstReg->u32 -= 4;
uint dst = (uint)ReadWord(A_dstReg->s32); uint dst = (uint)ReadWord(A_dstReg->s32);
uint res; uint res;
res = (uint)(dst - src - (X ? 1 : 0)); res = (uint)(dst - src - (X ? 1 : 0));
@ -1210,7 +1224,7 @@ namespace cpu.m68000
// { // {
// case 0: // byte // case 0: // byte
// { // {
// sbyte a = D[dReg].s8; // sbyte a = D_ptr_dReg->s8;
// sbyte b = ReadValueB(mode, reg); // sbyte b = ReadValueB(mode, reg);
// int result = a - b; // int result = a - b;
// N = (result & 0x80) != 0; // N = (result & 0x80) != 0;
@ -1222,7 +1236,7 @@ namespace cpu.m68000
// } // }
// case 1: // word // case 1: // word
// { // {
// short a = D[dReg].s16; // short a = D_ptr_dReg->s16;
// short b = ReadValueW(mode, reg); // short b = ReadValueW(mode, reg);
// int result = a - b; // int result = a - b;
// N = (result & 0x8000) != 0; // N = (result & 0x8000) != 0;
@ -1234,7 +1248,7 @@ namespace cpu.m68000
// } // }
// case 2: // long // case 2: // long
// { // {
// int a = D[dReg].s32; // int a = D_ptr_dReg->s32;
// int b = ReadValueL(mode, reg); // int b = ReadValueL(mode, reg);
// long result = (long)a - (long)b; // long result = (long)a - (long)b;
// N = (result & 0x80000000) != 0; // N = (result & 0x80000000) != 0;
@ -1270,7 +1284,7 @@ namespace cpu.m68000
} }
case 1: // word case 1: // word
{ {
short a = (D+ dReg)->s16; short a = (D + dReg)->s16;
short b = ReadValueW(mode, reg); short b = ReadValueW(mode, reg);
int result = a - b; int result = a - b;
N = (result & 0x8000) != 0; N = (result & 0x8000) != 0;
@ -1454,7 +1468,7 @@ namespace cpu.m68000
switch (mode) switch (mode)
{ {
case 0: // Dn case 0: // Dn
a = D[reg].s8; break; a = (D + reg)->s8; break;
case 1: // An case 1: // An
a = A_ptr_reg->s8; break; a = A_ptr_reg->s8; break;
case 2: // (An) case 2: // (An)
@ -1489,7 +1503,7 @@ namespace cpu.m68000
a = value; break; a = value; break;
case 4: // immediate case 4: // immediate
value = (sbyte)ReadOpWord(PC); PC += 2; value = (sbyte)ReadOpWord(PC); PC += 2;
a = value;break; a = value; break;
default: default:
throw new Exception("Invalid addressing mode!"); throw new Exception("Invalid addressing mode!");
} }
@ -1542,9 +1556,9 @@ namespace cpu.m68000
int dreg = (op >> 9) & 7; int dreg = (op >> 9) & 7;
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
Register* D_ptr_dreg = D + dreg;
uint result = (uint)(D[dreg].u16 * (ushort)ReadValueW(mode, reg)); uint result = (uint)(D_ptr_dreg->u16 * (ushort)ReadValueW(mode, reg));
D[dreg].u32 = result; D_ptr_dreg->u32 = result;
V = false; V = false;
C = false; C = false;
@ -1560,9 +1574,9 @@ namespace cpu.m68000
int dreg = (op >> 9) & 7; int dreg = (op >> 9) & 7;
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
Register* D_ptr_dreg = D + dreg;
int result = D[dreg].s16 * ReadValueW(mode, reg); int result = D_ptr_dreg->s16 * ReadValueW(mode, reg);
D[dreg].s32 = result; D_ptr_dreg->s32 = result;
V = false; V = false;
C = false; C = false;
@ -1580,7 +1594,8 @@ namespace cpu.m68000
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
uint source = (ushort)ReadValueW(mode, reg); uint source = (ushort)ReadValueW(mode, reg);
uint dest = D[dreg].u32; Register* D_ptr_dreg = D + dreg;
uint dest = D_ptr_dreg->u32;
if (source == 0) if (source == 0)
{ {
@ -1596,7 +1611,7 @@ namespace cpu.m68000
N = (quotient & 0x8000) != 0; N = (quotient & 0x8000) != 0;
V = false; V = false;
C = false; C = false;
D[dreg].u32 = (quotient & 0xFFFF) | (remainder << 16); D_ptr_dreg->u32 = (quotient & 0xFFFF) | (remainder << 16);
} }
else else
{ {
@ -1614,7 +1629,8 @@ namespace cpu.m68000
int reg = (op >> 0) & 7; int reg = (op >> 0) & 7;
int source = ReadValueW(mode, reg); int source = ReadValueW(mode, reg);
int dest = D[dreg].s32; Register* D_ptr_dreg = D + dreg;
int dest = D_ptr_dreg->s32;
if (source == 0) if (source == 0)
{ {
@ -1630,7 +1646,7 @@ namespace cpu.m68000
N = (quotient & 0x8000) != 0; N = (quotient & 0x8000) != 0;
V = false; V = false;
C = false; C = false;
D[dreg].s32 = (quotient & 0xFFFF) | (remainder << 16); D_ptr_dreg->s32 = (quotient & 0xFFFF) | (remainder << 16);
} }
else else
{ {

51
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/ProgramFlow.cs
View File

@ -135,9 +135,10 @@ namespace cpu.m68000
else else
{ {
int reg = op & 7; int reg = op & 7;
D[reg].u16--; Register* D_ptr_reg = D + reg;
D_ptr_reg->u16--;
if (D[reg].u16 == 0xFFFF) if (D_ptr_reg->u16 == 0xFFFF)
{ {
PC += 2; // counter underflowed, break out of loop PC += 2; // counter underflowed, break out of loop
pendingCycles -= 14; pendingCycles -= 14;
@ -207,7 +208,7 @@ namespace cpu.m68000
C = false; C = false;
/*if (mode == 0) /*if (mode == 0)
{ {
//D[reg].u8 = (byte)(result | 0x80); //D_ptr_reg->u8 = (byte)(result | 0x80);
}*/ }*/
WriteValueB(mode, reg, (sbyte)(result | 0x80)); WriteValueB(mode, reg, (sbyte)(result | 0x80));
pendingCycles -= (mode == 0) ? 4 : 14 + EACyclesBW[mode, reg]; pendingCycles -= (mode == 0) ? 4 : 14 + EACyclesBW[mode, reg];
@ -241,7 +242,8 @@ namespace cpu.m68000
{ {
bit &= 31; bit &= 31;
int mask = 1 << bit; int mask = 1 << bit;
Z = (D[reg].s32 & mask) == 0; Register* D_ptr_reg = D + reg;
Z = (D_ptr_reg->s32 & mask) == 0;
pendingCycles -= 10; pendingCycles -= 10;
} }
else else
@ -258,13 +260,14 @@ namespace cpu.m68000
int dReg = (op >> 9) & 7; int dReg = (op >> 9) & 7;
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = op & 7; int reg = op & 7;
int bit = D[dReg].s32; int bit = (D + dReg)->s32;
if (mode == 0) if (mode == 0)
{ {
bit &= 31; bit &= 31;
int mask = 1 << bit; int mask = 1 << bit;
Z = (D[reg].s32 & mask) == 0; Register* D_ptr_reg = D + reg;
Z = (D_ptr_reg->s32 & mask) == 0;
pendingCycles -= 6; pendingCycles -= 6;
} }
else else
@ -286,8 +289,9 @@ namespace cpu.m68000
{ {
bit &= 31; bit &= 31;
int mask = 1 << bit; int mask = 1 << bit;
Z = (D[reg].s32 & mask) == 0; Register* D_ptr_reg = D + reg;
D[reg].s32 ^= mask; Z = (D_ptr_reg->s32 & mask) == 0;
D_ptr_reg->s32 ^= mask;
pendingCycles -= 12; pendingCycles -= 12;
} }
else else
@ -308,14 +312,15 @@ namespace cpu.m68000
int dReg = (op >> 9) & 7; int dReg = (op >> 9) & 7;
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = op & 7; int reg = op & 7;
int bit = D[dReg].s32; int bit = (D + dReg)->s32;
if (mode == 0) if (mode == 0)
{ {
bit &= 31; bit &= 31;
int mask = 1 << bit; int mask = 1 << bit;
Z = (D[reg].s32 & mask) == 0; Register* D_ptr_reg = D + reg;
D[reg].s32 ^= mask; Z = (D_ptr_reg->s32 & mask) == 0;
D_ptr_reg->s32 ^= mask;
pendingCycles -= 8; pendingCycles -= 8;
} }
else else
@ -340,8 +345,9 @@ namespace cpu.m68000
{ {
bit &= 31; bit &= 31;
int mask = 1 << bit; int mask = 1 << bit;
Z = (D[reg].s32 & mask) == 0; Register* D_ptr_reg = D + reg;
D[reg].s32 &= ~mask; Z = (D_ptr_reg->s32 & mask) == 0;
D_ptr_reg->s32 &= ~mask;
pendingCycles -= 14; pendingCycles -= 14;
} }
else else
@ -361,14 +367,15 @@ namespace cpu.m68000
int dReg = (op >> 9) & 7; int dReg = (op >> 9) & 7;
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = op & 7; int reg = op & 7;
int bit = D[dReg].s32; int bit = (D + dReg)->s32;
if (mode == 0) if (mode == 0)
{ {
bit &= 31; bit &= 31;
int mask = 1 << bit; int mask = 1 << bit;
Z = (D[reg].s32 & mask) == 0; Register* D_ptr_reg = D + reg;
D[reg].s32 &= ~mask; Z = (D_ptr_reg->s32 & mask) == 0;
D_ptr_reg->s32 &= ~mask;
pendingCycles -= 10; pendingCycles -= 10;
} }
else else
@ -394,8 +401,9 @@ namespace cpu.m68000
{ {
bit &= 31; bit &= 31;
int mask = 1 << bit; int mask = 1 << bit;
Z = (D[reg].s32 & mask) == 0; Register* D_ptr_reg = D + reg;
D[reg].s32 |= mask; Z = (D_ptr_reg->s32 & mask) == 0;
D_ptr_reg->s32 |= mask;
pendingCycles -= 12; pendingCycles -= 12;
} }
else else
@ -416,14 +424,15 @@ namespace cpu.m68000
int dReg = (op >> 9) & 7; int dReg = (op >> 9) & 7;
int mode = (op >> 3) & 7; int mode = (op >> 3) & 7;
int reg = op & 7; int reg = op & 7;
int bit = D[dReg].s32; int bit = (D + dReg)->s32;
if (mode == 0) if (mode == 0)
{ {
bit &= 31; bit &= 31;
int mask = 1 << bit; int mask = 1 << bit;
Z = (D[reg].s32 & mask) == 0; Register* D_ptr_reg = D + reg;
D[reg].s32 |= mask; Z = (D_ptr_reg->s32 & mask) == 0;
D_ptr_reg->s32 |= mask;
pendingCycles -= 8; pendingCycles -= 8;
} }
else else

31
AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Memory.cs
View File

@ -10,7 +10,7 @@ namespace cpu.m68000
// switch (mode) // switch (mode)
// { // {
// case 0: // Dn // case 0: // Dn
// return D[reg].s8; // return D_ptr_reg->s8;
// case 1: // An // case 1: // An
// return A_ptr_reg->s8; // return A_ptr_reg->s8;
// case 2: // (An) // case 2: // (An)
@ -113,7 +113,7 @@ namespace cpu.m68000
// switch (mode) // switch (mode)
// { // {
// case 0: // Dn // case 0: // Dn
// return D[reg].s16; // return D_ptr_reg->s16;
// case 1: // An // case 1: // An
// return A_ptr_reg->s16; // return A_ptr_reg->s16;
// case 2: // (An) // case 2: // (An)
@ -215,7 +215,7 @@ namespace cpu.m68000
// switch (mode) // switch (mode)
// { // {
// case 0: // Dn // case 0: // Dn
// return D[reg].s32; // return D_ptr_reg->s32;
// case 1: // An // case 1: // An
// return A_ptr_reg->s32; // return A_ptr_reg->s32;
// case 2: // (An) // case 2: // (An)
@ -319,7 +319,7 @@ namespace cpu.m68000
switch (mode) switch (mode)
{ {
case 0: // Dn case 0: // Dn
return D[reg].s8; return (D + reg)->s8;
case 1: // An case 1: // An
{ {
Register* A_ptr_reg = A + reg; Register* A_ptr_reg = A + reg;
@ -384,7 +384,7 @@ namespace cpu.m68000
switch (mode) switch (mode)
{ {
case 0: // Dn case 0: // Dn
return D[reg].s16; return (D + reg)->s16;
case 1: // An case 1: // An
{ {
@ -450,7 +450,7 @@ namespace cpu.m68000
switch (mode) switch (mode)
{ {
case 0: // Dn case 0: // Dn
return D[reg].s32; return (D + reg)->s32;
case 1: // An case 1: // An
{ {
Register* A_ptr_reg = A + reg; Register* A_ptr_reg = A + reg;
@ -540,7 +540,7 @@ namespace cpu.m68000
// switch (mode) // switch (mode)
// { // {
// case 0x00: // Dn // case 0x00: // Dn
// D[reg].s8 = value; // D_ptr_reg->s8 = value;
// return; // return;
// case 0x01: // An // case 0x01: // An
// A_ptr_reg->s32 = value; // A_ptr_reg->s32 = value;
@ -644,7 +644,7 @@ namespace cpu.m68000
// switch (mode) // switch (mode)
// { // {
// case 0x00: // Dn // case 0x00: // Dn
// D[reg].s16 = value; // D_ptr_reg->s16 = value;
// return; // return;
// case 0x01: // An // case 0x01: // An
// A_ptr_reg->s32 = value; // A_ptr_reg->s32 = value;
@ -821,9 +821,15 @@ namespace cpu.m68000
default: indexReg = 8; break; default: indexReg = 8; break;
} }
if (da == 0) if (da == 0)
indexReg *= size == 0 ? D[reg].s16 : D[reg].s32; {
Register* D_ptr_reg = D + reg;
indexReg *= size == 0 ? D_ptr_reg->s16 : D_ptr_reg->s32;
}
else else
indexReg *= size == 0 ? (A + reg)->s16 : (A + reg)->s32; {
Register* A_ptr_reg = A + reg;
indexReg *= size == 0 ? A_ptr_reg->s16 : A_ptr_reg->s32;
}
return displacement + indexReg; return displacement + indexReg;
} }
@ -849,7 +855,10 @@ namespace cpu.m68000
default: indexReg = 8; break; default: indexReg = 8; break;
} }
if (da == 0) if (da == 0)
indexReg *= size == 0 ? D[reg].s16 : D[reg].s32; {
Register* D_ptr_reg = D + reg;
indexReg *= size == 0 ? D_ptr_reg->s16 : D_ptr_reg->s32;
}
else else
{ {
Register* A_ptr_reg = A + reg; Register* A_ptr_reg = A + reg;