AxibugEmuOnline/virtuanessrc097-master/NES/MMU.h

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<EFBFBD><EFBFBD>//////////////////////////////////////////////////////////////////////////
// //
// NES Memory Management Unit //
// Norix //
// written 2001/02/21 //
// last modify ----/--/-- //
//////////////////////////////////////////////////////////////////////////
#ifndef __MMU_INCLUDED__
#define __MMU_INCLUDED__
#include "typedef.h"
#include "macro.h"
// CPU <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
extern LPBYTE CPU_MEM_BANK[8]; // 8KXSMO
extern BYTE CPU_MEM_TYPE[8];
extern INT CPU_MEM_PAGE[8]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0(u
// PPU <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
extern LPBYTE PPU_MEM_BANK[12]; // 1KXSMO
extern BYTE PPU_MEM_TYPE[12];
extern INT PPU_MEM_PAGE[12]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0(u
extern BYTE CRAM_USED[16]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0(u
// NES<EFBFBD>0<EFBFBD>0<EFBFBD>0
extern BYTE RAM [ 8*1024]; // NES<EFBFBD>QӁRAM
extern BYTE WRAM[128*1024]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0/<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0RAM
extern BYTE DRAM[ 40*1024]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0RAM
extern BYTE XRAM[ 8*1024]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
extern BYTE ERAM[ 32*1024]; // <EFBFBD>b5__jhV(uRAM
extern BYTE CRAM[ 32*1024]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0RAM
extern BYTE VRAM[ 4*1024]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0/<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0RAM
extern BYTE SPRAM[0x100]; // <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0RAM
extern BYTE BGPAL[0x10]; // BG<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
extern BYTE SPPAL[0x10]; // SP<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
// <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
extern BYTE CPUREG[0x18]; // Nes $4000-$4017
extern BYTE PPUREG[0x04]; // Nes $2000-$2003
// Frame-IRQ<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0($4017)
extern BYTE FrameIRQ;
// PPU<EFBFBD>Q<EFBFBD><EFBFBD><EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
extern BYTE PPU56Toggle; // $2005-$2006 Toggle
extern BYTE PPU7_Temp; // $2007 read buffer
extern WORD loopy_t; // same as $2005/$2006
extern WORD loopy_v; // same as $2005/$2006
extern WORD loopy_x; // tile x offset
// ROM<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
extern LPBYTE PROM; // PROM ptr
extern LPBYTE VROM; // VROM ptr
#ifdef _DATATRACE
// For dis...
extern LPBYTE PROM_ACCESS;
#endif
// ROM <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
extern INT PROM_8K_SIZE, PROM_16K_SIZE, PROM_32K_SIZE;
extern INT VROM_1K_SIZE, VROM_2K_SIZE, VROM_4K_SIZE, VROM_8K_SIZE;
// <EFBFBD><EFBFBD>pe
extern void NesSub_MemoryInitial();
extern void SetPROM_Bank( BYTE page, LPBYTE ptr, BYTE type );
extern void SetPROM_8K_Bank ( BYTE page, INT bank );
extern void SetPROM_16K_Bank( BYTE page, INT bank );
extern void SetPROM_32K_Bank( INT bank );
extern void SetPROM_32K_Bank( INT bank0, INT bank1, INT bank2, INT bank3 );
extern void SetVROM_Bank( BYTE page, LPBYTE ptr, BYTE type );
extern void SetVROM_1K_Bank( BYTE page, INT bank );
extern void SetVROM_2K_Bank( BYTE page, INT bank );
extern void SetVROM_4K_Bank( BYTE page, INT bank );
extern void SetVROM_8K_Bank( INT bank );
extern void SetVROM_8K_Bank( INT bank0, INT bank1, INT bank2, INT bank3,
INT bank4, INT bank5, INT bank6, INT bank7 );
extern void SetCRAM_1K_Bank( BYTE page, INT bank );
extern void SetCRAM_2K_Bank( BYTE page, INT bank );
extern void SetCRAM_4K_Bank( BYTE page, INT bank );
extern void SetCRAM_8K_Bank( INT bank );
extern void SetVRAM_1K_Bank( BYTE page, INT bank );
extern void SetVRAM_Bank( INT bank0, INT bank1, INT bank2, INT bank3 );
extern void SetVRAM_Mirror( INT type );
extern void SetVRAM_Mirror( INT bank0, INT bank1, INT bank2, INT bank3 );
// <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
// For PROM (CPU)
#define BANKTYPE_ROM 0x00
#define BANKTYPE_RAM 0xFF
#define BANKTYPE_DRAM 0x01
#define BANKTYPE_MAPPER 0x80
// For VROM/VRAM/CRAM (PPU)
#define BANKTYPE_VROM 0x00
#define BANKTYPE_CRAM 0x01
#define BANKTYPE_VRAM 0x80
// <EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0<EFBFBD>0
#define VRAM_HMIRROR 0x00 // Horizontal
#define VRAM_VMIRROR 0x01 // Virtical
#define VRAM_MIRROR4 0x02 // All screen
#define VRAM_MIRROR4L 0x03 // PA10 L<EFBFBD>V<EFBFBD>[ $2000-$23FFn0<EFBFBD>0<EFBFBD>0<EFBFBD>0
#define VRAM_MIRROR4H 0x04 // PA10 H<EFBFBD>V<EFBFBD>[ $2400-$27FFn0<EFBFBD>0<EFBFBD>0<EFBFBD>0
#endif // !__MMU_INCLUDED__