From 79ada55c3c19087d19c39d9b57cf90801f4ced70 Mon Sep 17 00:00:00 2001 From: sin365 <353374337@qq.com> Date: Wed, 26 Nov 2025 16:01:42 +0800 Subject: [PATCH] =?UTF-8?q?MAME:MC68000=20Register*=20A=20=E6=9B=B4?= =?UTF-8?q?=E6=8D=A2=E6=89=80=E6=9C=89=E4=B8=8B=E6=A0=87=E5=8F=96=E5=80=BC?= =?UTF-8?q?=EF=BC=8C=E6=94=B9=E4=B8=BA=E7=9B=B4=E6=8E=A5=E6=8C=87=E9=92=88?= =?UTF-8?q?=E8=BF=90=E7=AE=97=E8=A7=A3=E5=BC=95=E7=94=A8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../cpu/m68000/Instructions/DataMovement.cs | 42 ++-- .../cpu/m68000/Instructions/IntegerMath.cs | 163 ++++++------ .../cpu/m68000/Instructions/ProgramFlow.cs | 11 +- .../cpu/m68000/Instructions/Supervisor.cs | 5 +- .../Plugins/Mame.Core/cpu/m68000/Memory.cs | 232 +++++++++++------- 5 files changed, 268 insertions(+), 185 deletions(-) diff --git a/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/DataMovement.cs b/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/DataMovement.cs index 79a7b281..13bbe623 100644 --- a/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/DataMovement.cs +++ b/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/DataMovement.cs @@ -64,10 +64,10 @@ namespace cpu.m68000 int dstReg = ((op >> 9) & 0x07); int srcMode = ((op >> 3) & 0x07); int srcReg = (op & 0x07); - + Register* A_dstReg = A + dstReg; if (size == 3) // Word { - A[dstReg].s32 = ReadValueW(srcMode, srcReg); + A_dstReg->s32 = ReadValueW(srcMode, srcReg); switch (srcMode) { case 0: pendingCycles -= 4; break; @@ -92,7 +92,7 @@ namespace cpu.m68000 } else { // Long - A[dstReg].s32 = ReadValueL(srcMode, srcReg); + A_dstReg->s32 = ReadValueL(srcMode, srcReg); switch (srcMode) { case 0: pendingCycles -= 4; break; @@ -124,17 +124,18 @@ namespace cpu.m68000 int dir = ((op >> 7) & 0x01); int size = ((op >> 6) & 0x01); int aReg = (op & 0x07); + Register* A_ptr_aReg = A + aReg; if (dir == 0 && size == 0) { int ea; - ea = A[aReg].s32 + ReadOpWord(PC); PC += 2; + ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2; D[dReg].u32 = (D[dReg].u32 & 0xffff0000) | (ushort)(((byte)ReadByte(ea) << 8) + (byte)ReadByte(ea + 2)); pendingCycles -= 16; } else if (dir == 0 && size == 1) { int ea; - ea = A[aReg].s32 + ReadOpWord(PC); PC += 2; + ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2; D[dReg].u32 = (uint)(((byte)ReadByte(ea) << 24) + ((byte)ReadByte(ea + 2) << 16) + ((byte)ReadByte(ea + 4) << 8) + (byte)ReadByte(ea + 6)); pendingCycles -= 24; } @@ -142,7 +143,7 @@ namespace cpu.m68000 { uint src; int ea; - ea = A[aReg].s32 + ReadOpWord(PC); PC += 2; + ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2; src = D[dReg].u32; WriteByte(ea, (sbyte)((src >> 8) & 0xff)); WriteByte(ea + 2, (sbyte)(src & 0xff)); @@ -152,7 +153,7 @@ namespace cpu.m68000 { uint src; int ea; - ea = A[aReg].s32 + ReadOpWord(PC); PC += 2; + ea = A_ptr_aReg->s32 + ReadOpWord(PC); PC += 2; src = D[dReg].u32; WriteByte(ea, (sbyte)((src >> 24) & 0xff)); WriteByte(ea + 2, (sbyte)((src >> 16) & 0xff)); @@ -240,6 +241,7 @@ namespace cpu.m68000 int address = ReadAddress(dstMode, dstReg); int regCount = 0; + Register* A_dstReg = A + dstReg; if (size == 0) { // word-assign @@ -250,7 +252,7 @@ namespace cpu.m68000 if ((registers & 1) == 1) { address -= 2; - WriteWord(address, A[i].s16); + WriteWord(address, (A + i)->s16); regCount++; } registers >>= 1; @@ -265,7 +267,7 @@ namespace cpu.m68000 } registers >>= 1; } - A[dstReg].s32 = address; + A_dstReg->s32 = address; } else { // increment address @@ -283,7 +285,7 @@ namespace cpu.m68000 { if ((registers & 1) == 1) { - WriteWord(address, A[i].s16); + WriteWord(address, (A + i)->s16); address += 2; regCount++; } @@ -302,7 +304,7 @@ namespace cpu.m68000 if ((registers & 1) == 1) { address -= 4; - WriteLong(address, A[i].s32); + WriteLong(address, (A + i)->s32); regCount++; } registers >>= 1; @@ -317,7 +319,7 @@ namespace cpu.m68000 } registers >>= 1; } - A[dstReg].s32 = address; + A_dstReg->s32 = address; } else { // increment address @@ -335,7 +337,7 @@ namespace cpu.m68000 { if ((registers & 1) == 1) { - WriteLong(address, A[i].s32); + WriteLong(address, (A + i)->s32); address += 4; regCount++; } @@ -400,11 +402,11 @@ namespace cpu.m68000 { if (srcMode == 7 && (srcReg == 2 || srcReg == 3)) { - A[i].s32 = ReadPcrelWord(address); + (A + i)->s32 = ReadPcrelWord(address); } else { - A[i].s32 = ReadWord(address); + (A + i)->s32 = ReadWord(address); } address += 2; regCount++; @@ -413,7 +415,7 @@ namespace cpu.m68000 } pendingCycles -= regCount * 4; if (srcMode == 3) - A[srcReg].s32 = address; + (A + srcReg)->s32 = address; } else { @@ -441,11 +443,11 @@ namespace cpu.m68000 { if (srcMode == 7 && (srcReg == 2 || srcReg == 3)) { - A[i].s32 = ReadPcrelLong(address); + (A + i)->s32 = ReadPcrelLong(address); } else { - A[i].s32 = ReadLong(address); + (A + i)->s32 = ReadLong(address); } address += 4; regCount++; @@ -454,7 +456,7 @@ namespace cpu.m68000 } pendingCycles -= regCount * 8; if (srcMode == 3) - A[srcReg].s32 = address; + (A + srcReg)->s32 = address; } switch (srcMode) @@ -482,7 +484,7 @@ namespace cpu.m68000 int sReg = (op >> 0) & 7; int dReg = (op >> 9) & 7; - A[dReg].u32 = (uint)ReadAddress(mode, sReg); + (A + dReg)->u32 = (uint)ReadAddress(mode, sReg); switch (mode) { case 2: pendingCycles -= 4; break; diff --git a/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/IntegerMath.cs b/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/IntegerMath.cs index d3ae1a72..a8a77847 100644 --- a/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/IntegerMath.cs +++ b/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/IntegerMath.cs @@ -253,16 +253,17 @@ namespace cpu.m68000 int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; + Register* A_ptr_aReg = A + aReg; if (size == 0) // word { int value = ReadValueW(mode, reg); - A[aReg].s32 += value; + A_ptr_aReg->s32 += value; pendingCycles -= 8 + EACyclesBW[mode, reg]; } else { // long int value = ReadValueL(mode, reg); - A[aReg].s32 += value; + A_ptr_aReg->s32 += value; if (mode == 0 || mode == 1 || (mode == 7 && reg == 4)) pendingCycles -= 8 + EACyclesL[mode, reg]; else @@ -514,16 +515,17 @@ namespace cpu.m68000 int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; + Register* A_ptr_aReg = A + aReg; if (size == 0) // word { int value = ReadValueW(mode, reg); - A[aReg].s32 -= value; + A_ptr_aReg->s32 -= value; pendingCycles -= 8 + EACyclesBW[mode, reg]; } else { // long int value = ReadValueL(mode, reg); - A[aReg].s32 -= value; + A_ptr_aReg->s32 -= value; if (mode == 0 || mode == 1 || (mode == 7 && reg == 4)) pendingCycles -= 8 + EACyclesL[mode, reg]; else @@ -775,25 +777,27 @@ namespace cpu.m68000 { int dstReg = (op >> 9) & 0x07; int srcReg = op & 0x07; + Register* A_srcReg = A + srcReg; + Register* A_dstReg = A + dstReg; uint src, dst, res; if (srcReg == 7) { - A[srcReg].u32 -= 2; + A_srcReg->u32 -= 2; } else { - A[srcReg].u32--; + A_srcReg->u32--; } if (dstReg == 7) { - A[dstReg].u32 -= 2; + A_dstReg->u32 -= 2; } else { - A[dstReg].u32--; + A_dstReg->u32--; } - src = (uint)ReadByte(A[srcReg].s32); - dst = (uint)ReadByte(A[dstReg].s32); + src = (uint)ReadByte(A_srcReg->s32); + dst = (uint)ReadByte(A_dstReg->s32); res = (uint)((dst & 0x0f) - (src & 0x0f) - (X ? 1 : 0)); V = false; if (res > 9) @@ -813,7 +817,7 @@ namespace cpu.m68000 } res = res & 0xff; Z &= (res == 0); - WriteByte(A[dstReg].s32, (sbyte)res); + WriteByte(A_dstReg->s32, (sbyte)res); pendingCycles -= 18; } @@ -850,25 +854,27 @@ namespace cpu.m68000 { int dstReg = (op >> 9) & 0x07; int srcReg = op & 0x07; + Register* A_srcReg = A + srcReg; + Register* A_dstReg = A + dstReg; uint src, dst, res; if (srcReg == 7) { - A[srcReg].u32 -= 2; + A_srcReg->u32 -= 2; } else { - A[srcReg].u32--; + A_srcReg->u32--; } if (dstReg == 7) { - A[dstReg].u32 -= 2; + A_dstReg->u32 -= 2; } else { - A[dstReg].u32--; + A_dstReg->u32--; } - src = (uint)ReadByte(A[srcReg].s32); - dst = (uint)ReadByte(A[dstReg].s32); + src = (uint)ReadByte(A_srcReg->s32); + dst = (uint)ReadByte(A_dstReg->s32); res = (uint)((src & 0x0f) + (dst & 0x0f) + (X ? 1 : 0)); V = (((~res) & 0x80) != 0); if (res > 9) @@ -885,7 +891,7 @@ namespace cpu.m68000 N = ((res & 0x80) != 0); res = res & 0xff; Z &= (res == 0); - WriteByte(A[dstReg].s32, (sbyte)res); + WriteByte(A_dstReg->s32, (sbyte)res); pendingCycles -= 18; } @@ -907,9 +913,11 @@ namespace cpu.m68000 int reg_a = (op >> 9) & 0x07; int reg_b = op & 0x07; uint tmp; - tmp = A[reg_a].u32; - A[reg_a].u32 = A[reg_b].u32; - A[reg_b].u32 = tmp; + Register* A_ptr_reg_a = A + reg_a; + Register* A_ptr_reg_b = A + reg_b; + tmp = A_ptr_reg_a->u32; + A_ptr_reg_a->u32 = A_ptr_reg_b->u32; + A_ptr_reg_b->u32 = tmp; pendingCycles -= 6; } @@ -918,10 +926,11 @@ namespace cpu.m68000 { int reg_a = (op >> 9) & 0x07; int reg_b = op & 0x07; + Register* A_ptr_reg_b = A + reg_b; uint tmp; tmp = D[reg_a].u32; - D[reg_a].u32 = A[reg_b].u32; - A[reg_b].u32 = tmp; + D[reg_a].u32 = A_ptr_reg_b->u32; + A_ptr_reg_b->u32 = tmp; pendingCycles -= 6; } @@ -986,28 +995,30 @@ namespace cpu.m68000 int dstReg = (op >> 9) & 0x07; int size = (op >> 6) & 0x03; int srcReg = op & 0x07; + Register* A_srcReg = A + srcReg; + Register* A_dstReg = A + dstReg; switch (size) { case 0: { if (srcReg == 7) { - A[srcReg].u32 -= 2; + A_srcReg->u32 -= 2; } else { - A[srcReg].u32--; + A_srcReg->u32--; } if (dstReg == 7) { - A[dstReg].u32 -= 2; + A_dstReg->u32 -= 2; } else { - A[dstReg].u32--; + A_dstReg->u32--; } - uint src = (uint)ReadByte(A[srcReg].s32); - uint dst = (uint)ReadByte(A[dstReg].s32); + uint src = (uint)ReadByte(A_srcReg->s32); + uint dst = (uint)ReadByte(A_dstReg->s32); uint res; res = (uint)(dst + src + (X ? 1 : 0)); N = ((res & 0x80) != 0); @@ -1015,16 +1026,16 @@ namespace cpu.m68000 X = C = ((res & 0x100) != 0); res = res & 0xff; Z &= (res == 0); - WriteByte(A[dstReg].s32, (sbyte)res); + WriteByte(A_dstReg->s32, (sbyte)res); pendingCycles -= 18; return; } case 1: { - A[srcReg].u32 -= 2; - uint src = (uint)ReadWord(A[srcReg].s32); - A[dstReg].u32 -= 2; - uint dst = (uint)ReadWord(A[dstReg].s32); + A_srcReg->u32 -= 2; + uint src = (uint)ReadWord(A_srcReg->s32); + A_dstReg->u32 -= 2; + uint dst = (uint)ReadWord(A_dstReg->s32); uint res; res = (uint)(dst + src + (X ? 1 : 0)); N = ((res & 0x8000) != 0); @@ -1032,23 +1043,23 @@ namespace cpu.m68000 X = C = ((res & 0x10000) != 0); res = res & 0xffff; Z &= (res == 0); - WriteWord(A[dstReg].s32, (short)res); + WriteWord(A_dstReg->s32, (short)res); pendingCycles -= 18; return; } case 2: { - A[srcReg].u32 -= 4; - uint src = (uint)ReadLong(A[srcReg].s32); - A[dstReg].u32 -= 4; - uint dst = (uint)ReadWord(A[dstReg].s32); + A_srcReg->u32 -= 4; + uint src = (uint)ReadLong(A_srcReg->s32); + A_dstReg->u32 -= 4; + uint dst = (uint)ReadWord(A_dstReg->s32); uint res; res = (uint)(dst + src + (X ? 1 : 0)); N = ((res & 0x80000000) != 0); V = (((((src ^ res) & (dst ^ res)) >> 24) & 0x80) != 0); X = C = (((((src & dst) | (~res & (src | dst))) >> 23) & 0x100) != 0); Z &= (res == 0); - WriteLong(A[dstReg].s32, (int)res); + WriteLong(A_dstReg->s32, (int)res); pendingCycles -= 30; return; } @@ -1116,28 +1127,30 @@ namespace cpu.m68000 int dstReg = (op >> 9) & 0x07; int size = (op >> 6) & 0x03; int srcReg = op & 0x07; + Register* A_srcReg = A + srcReg; + Register* A_dstReg = A + dstReg; switch (size) { case 0: { if (srcReg == 7) { - A[srcReg].u32 -= 2; + A_srcReg->u32 -= 2; } else { - A[srcReg].u32--; + A_srcReg->u32--; } if (dstReg == 7) { - A[dstReg].u32 -= 2; + A_dstReg->u32 -= 2; } else { - A[dstReg].u32--; + A_dstReg->u32--; } - uint src = (uint)ReadByte(A[srcReg].s32); - uint dst = (uint)ReadByte(A[dstReg].s32); + uint src = (uint)ReadByte(A_srcReg->s32); + uint dst = (uint)ReadByte(A_dstReg->s32); uint res; res = (uint)(dst - src - (X ? 1 : 0)); N = ((res & 0x80) != 0); @@ -1145,16 +1158,16 @@ namespace cpu.m68000 V = ((((src ^ dst) & (res ^ dst)) & 0x80) != 0); res = res & 0xff; Z &= (res == 0); - WriteByte(A[dstReg].s32, (sbyte)res); + WriteByte(A_dstReg->s32, (sbyte)res); pendingCycles -= 18; return; } case 1: { - A[srcReg].u32 -= 2; - uint src = (uint)ReadWord(A[srcReg].s32); - A[dstReg].u32 -= 2; - uint dst = (uint)ReadWord(A[dstReg].s32); + A_srcReg->u32 -= 2; + uint src = (uint)ReadWord(A_srcReg->s32); + A_dstReg->u32 -= 2; + uint dst = (uint)ReadWord(A_dstReg->s32); uint res; res = (uint)(dst - src - (X ? 1 : 0)); N = ((res & 0x8000) != 0); @@ -1162,23 +1175,23 @@ namespace cpu.m68000 V = ((((src ^ dst) & (res ^ dst)) & 0x8000) != 0); res = res & 0xffff; Z &= (res == 0); - WriteWord(A[dstReg].s32, (short)res); + WriteWord(A_dstReg->s32, (short)res); pendingCycles -= 18; return; } case 2: { - A[srcReg].u32 -= 4; - uint src = (uint)ReadLong(A[srcReg].s32); - A[dstReg].u32 -= 4; - uint dst = (uint)ReadWord(A[dstReg].s32); + A_srcReg->u32 -= 4; + uint src = (uint)ReadLong(A_srcReg->s32); + A_dstReg->u32 -= 4; + uint dst = (uint)ReadWord(A_dstReg->s32); uint res; res = (uint)(dst - src - (X ? 1 : 0)); N = ((res & 0x80000000) != 0); X = C = (((((src & res) | (~dst & (src | res))) >> 23) & 0x100) != 0); V = (((((src ^ dst) & (res ^ dst)) >> 24) & 0x80) != 0); Z &= (res == 0); - WriteLong(A[dstReg].s32, (int)res); + WriteLong(A_dstReg->s32, (int)res); pendingCycles -= 30; return; } @@ -1290,11 +1303,12 @@ namespace cpu.m68000 int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; + Register* A_ptr_aReg = A + aReg; switch (size) { case 0: // word { - int a = A[aReg].s32; + int a = A_ptr_aReg->s32; short b = ReadValueW(mode, reg); long result = a - b; N = (result & 0x80000000) != 0; @@ -1306,7 +1320,7 @@ namespace cpu.m68000 } case 1: // long { - int a = A[aReg].s32; + int a = A_ptr_aReg->s32; int b = ReadValueL(mode, reg); long result = a - b; N = (result & 0x80000000) != 0; @@ -1326,12 +1340,14 @@ namespace cpu.m68000 int size = (op >> 6) & 3; int ayReg = (op >> 0) & 7; + Register* A_axReg = A + axReg; + Register* A_ayReg = A + ayReg; switch (size) { case 0: // byte { - sbyte a = ReadByte(A[axReg].s32); A[axReg].s32 += 1; // Does A7 stay word aligned??? - sbyte b = ReadByte(A[ayReg].s32); A[ayReg].s32 += 1; + sbyte a = ReadByte(A_axReg->s32); A_axReg->s32 += 1; // Does A7 stay word aligned??? + sbyte b = ReadByte(A_ayReg->s32); A_ayReg->s32 += 1; int result = a - b; N = (result & 0x80) != 0; Z = (result & 0xff) == 0; @@ -1342,8 +1358,8 @@ namespace cpu.m68000 } case 1: // word { - short a = ReadWord(A[axReg].s32); A[axReg].s32 += 2; - short b = ReadWord(A[ayReg].s32); A[ayReg].s32 += 2; + short a = ReadWord(A_axReg->s32); A_axReg->s32 += 2; + short b = ReadWord(A_ayReg->s32); A_ayReg->s32 += 2; int result = a - b; N = (result & 0x8000) != 0; Z = (result & 0xffff) == 0; @@ -1354,8 +1370,8 @@ namespace cpu.m68000 } case 2: // long { - int a = ReadLong(A[axReg].s32); A[axReg].s32 += 4; - int b = ReadLong(A[ayReg].s32); A[ayReg].s32 += 4; + int a = ReadLong(A_axReg->s32); A_axReg->s32 += 4; + int b = ReadLong(A_ayReg->s32); A_ayReg->s32 += 4; long result = a - b; N = (result & 0x80000000) != 0; Z = (uint)result == 0; @@ -1424,6 +1440,7 @@ namespace cpu.m68000 int size = (op >> 6) & 3; int mode = (op >> 3) & 7; int reg = (op >> 0) & 7; + Register* A_ptr_reg = A + reg; switch (size) { @@ -1439,21 +1456,21 @@ namespace cpu.m68000 case 0: // Dn a = D[reg].s8; break; case 1: // An - a = A[reg].s8; break; + a = A_ptr_reg->s8; break; case 2: // (An) - a = ReadByte(A[reg].s32); break; + a = ReadByte(A_ptr_reg->s32); break; case 3: // (An)+ - value = ReadByte(A[reg].s32); - A[reg].s32 += reg == 7 ? 2 : 1; + value = ReadByte(A_ptr_reg->s32); + A_ptr_reg->s32 += reg == 7 ? 2 : 1; a = value; break; case 4: // -(An) - A[reg].s32 -= reg == 7 ? 2 : 1; - a = ReadByte(A[reg].s32); break; + A_ptr_reg->s32 -= reg == 7 ? 2 : 1; + a = ReadByte(A_ptr_reg->s32); break; case 5: // (d16,An) - value = ReadByte((A[reg].s32 + ReadOpWord(PC))); PC += 2; + value = ReadByte((A_ptr_reg->s32 + ReadOpWord(PC))); PC += 2; a = value; break; case 6: // (d8,An,Xn) - a = ReadByte(A[reg].s32 + GetIndex()); break; + a = ReadByte(A_ptr_reg->s32 + GetIndex()); break; case 7: switch (reg) { diff --git a/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/ProgramFlow.cs b/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/ProgramFlow.cs index 1eb503d6..b16c6afa 100644 --- a/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/ProgramFlow.cs +++ b/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/ProgramFlow.cs @@ -1,4 +1,5 @@ using System; +using System.Text.RegularExpressions; namespace cpu.m68000 { @@ -499,10 +500,11 @@ namespace cpu.m68000 int reg = op & 7; Register* ptrA7 = &A[7]; + Register* A_ptr_reg = A + reg; ptrA7->s32 -= 4; short offset = ReadOpWord(PC); PC += 2; - WriteLong(ptrA7->s32, A[reg].s32); - A[reg].s32 = ptrA7->s32; + WriteLong(ptrA7->s32, A_ptr_reg->s32); + A_ptr_reg->s32 = ptrA7->s32; ptrA7->s32 += offset; pendingCycles -= 16; } @@ -512,8 +514,9 @@ namespace cpu.m68000 { int reg = op & 7; Register* ptrA7 = &A[7]; - ptrA7->s32 = A[reg].s32; - A[reg].s32 = ReadLong(ptrA7->s32); + Register* A_ptr_reg = A + reg; + ptrA7->s32 = A_ptr_reg->s32; + A_ptr_reg->s32 = ReadLong(ptrA7->s32); ptrA7->s32 += 4; pendingCycles -= 12; } diff --git a/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/Supervisor.cs b/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/Supervisor.cs index ade4ee8a..5e347f39 100644 --- a/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/Supervisor.cs +++ b/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Instructions/Supervisor.cs @@ -61,13 +61,14 @@ namespace cpu.m68000 } else { + Register* A_ptr_reg = A + reg; if (dir == 0) { - usp = A[reg].s32; + usp = A_ptr_reg->s32; } else { - A[reg].s32 = usp; + A_ptr_reg->s32 = usp; } } pendingCycles -= 4; diff --git a/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Memory.cs b/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Memory.cs index 06a362f1..2a57820b 100644 --- a/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Memory.cs +++ b/AxibugEmuOnline.Client/Assets/Plugins/Mame.Core/cpu/m68000/Memory.cs @@ -12,21 +12,21 @@ namespace cpu.m68000 // case 0: // Dn // return D[reg].s8; // case 1: // An - // return A[reg].s8; + // return A_ptr_reg->s8; // case 2: // (An) - // return ReadByte(A[reg].s32); + // return ReadByte(A_ptr_reg->s32); // case 3: // (An)+ - // value = ReadByte(A[reg].s32); - // A[reg].s32 += reg == 7 ? 2 : 1; + // value = ReadByte(A_ptr_reg->s32); + // A_ptr_reg->s32 += reg == 7 ? 2 : 1; // return value; // case 4: // -(An) - // A[reg].s32 -= reg == 7 ? 2 : 1; - // return ReadByte(A[reg].s32); + // A_ptr_reg->s32 -= reg == 7 ? 2 : 1; + // return ReadByte(A_ptr_reg->s32); // case 5: // (d16,An) - // value = ReadByte((A[reg].s32 + ReadOpWord(PC))); PC += 2; + // value = ReadByte((A_ptr_reg->s32 + ReadOpWord(PC))); PC += 2; // return value; // case 6: // (d8,An,Xn) - // return ReadByte(A[reg].s32 + GetIndex()); + // return ReadByte(A_ptr_reg->s32 + GetIndex()); // case 7: // switch (reg) // { @@ -65,14 +65,14 @@ namespace cpu.m68000 return ReadByte((A + reg)->s32); case 3: // (An)+ { - Register* ptr = &A[reg]; + Register* ptr = A + reg; value = ReadByte(ptr->s32); ptr->s32 += reg == 7 ? 2 : 1; } return value; case 4: // -(An) { - Register* ptr = &A[reg]; + Register* ptr = A + reg; ptr->s32 -= reg == 7 ? 2 : 1; return ReadByte(ptr->s32); } @@ -115,21 +115,21 @@ namespace cpu.m68000 // case 0: // Dn // return D[reg].s16; // case 1: // An - // return A[reg].s16; + // return A_ptr_reg->s16; // case 2: // (An) - // return ReadWord(A[reg].s32); + // return ReadWord(A_ptr_reg->s32); // case 3: // (An)+ - // value = ReadWord(A[reg].s32); - // A[reg].s32 += 2; + // value = ReadWord(A_ptr_reg->s32); + // A_ptr_reg->s32 += 2; // return value; // case 4: // -(An) - // A[reg].s32 -= 2; - // return ReadWord(A[reg].s32); + // A_ptr_reg->s32 -= 2; + // return ReadWord(A_ptr_reg->s32); // case 5: // (d16,An) - // value = ReadWord((A[reg].s32 + ReadOpWord(PC))); PC += 2; + // value = ReadWord((A_ptr_reg->s32 + ReadOpWord(PC))); PC += 2; // return value; // case 6: // (d8,An,Xn) - // return ReadWord(A[reg].s32 + GetIndex()); + // return ReadWord(A_ptr_reg->s32 + GetIndex()); // case 7: // switch (reg) // { @@ -168,14 +168,14 @@ namespace cpu.m68000 return ReadWord((A + reg)->s32); case 3: // (An)+ { - Register* ptr = &A[reg]; + Register* ptr = A + reg; value = ReadWord(ptr->s32); ptr->s32 += 2; return value; } case 4: // -(An) { - Register* ptr = &A[reg]; + Register* ptr = A + reg; ptr->s32 -= 2; return ReadWord(ptr->s32); } @@ -217,21 +217,21 @@ namespace cpu.m68000 // case 0: // Dn // return D[reg].s32; // case 1: // An - // return A[reg].s32; + // return A_ptr_reg->s32; // case 2: // (An) - // return ReadLong(A[reg].s32); + // return ReadLong(A_ptr_reg->s32); // case 3: // (An)+ - // value = ReadLong(A[reg].s32); - // A[reg].s32 += 4; + // value = ReadLong(A_ptr_reg->s32); + // A_ptr_reg->s32 += 4; // return value; // case 4: // -(An) - // A[reg].s32 -= 4; - // return ReadLong(A[reg].s32); + // A_ptr_reg->s32 -= 4; + // return ReadLong(A_ptr_reg->s32); // case 5: // (d16,An) - // value = ReadLong((A[reg].s32 + ReadOpWord(PC))); PC += 2; + // value = ReadLong((A_ptr_reg->s32 + ReadOpWord(PC))); PC += 2; // return value; // case 6: // (d8,An,Xn) - // return ReadLong(A[reg].s32 + GetIndex()); + // return ReadLong(A_ptr_reg->s32 + GetIndex()); // case 7: // switch (reg) // { @@ -271,14 +271,14 @@ namespace cpu.m68000 return ReadLong((A + reg)->s32); case 3: // (An)+ { - Register* ptr = &A[reg]; + Register* ptr = A + reg; value = ReadLong(ptr->s32); ptr->s32 += 4; } return value; case 4: // -(An) { - Register* ptr = &A[reg]; + Register* ptr = A + reg; ptr->s32 -= 4; return ReadLong(ptr->s32); } @@ -321,20 +321,39 @@ namespace cpu.m68000 case 0: // Dn return D[reg].s8; case 1: // An - return A[reg].s8; + { + Register* A_ptr_reg = A + reg; + return A_ptr_reg->s8; + } case 2: // (An) - return ReadByte(A[reg].s32); + { + Register* A_ptr_reg = A + reg; + return ReadByte(A_ptr_reg->s32); + } case 3: // (An)+ - value = ReadByte(A[reg].s32); - return value; + { + + Register* A_ptr_reg = A + reg; + value = ReadByte(A_ptr_reg->s32); + return value; + } case 4: // -(An) - value = ReadByte(A[reg].s32 - (reg == 7 ? 2 : 1)); - return value; + { + Register* A_ptr_reg = A + reg; + value = ReadByte(A_ptr_reg->s32 - (reg == 7 ? 2 : 1)); + return value; + } case 5: // (d16,An) - value = ReadByte((A[reg].s32 + ReadOpWord(PC))); - return value; + { + Register* A_ptr_reg = A + reg; + value = ReadByte((A_ptr_reg->s32 + ReadOpWord(PC))); + return value; + } case 6: // (d8,An,Xn) - return ReadByte(A[reg].s32 + PeekIndex()); + { + Register* A_ptr_reg = A + reg; + return ReadByte(A_ptr_reg->s32 + PeekIndex()); + } case 7: switch (reg) { @@ -367,20 +386,40 @@ namespace cpu.m68000 case 0: // Dn return D[reg].s16; case 1: // An - return A[reg].s16; + { + + Register* A_ptr_reg = A + reg; + return A_ptr_reg->s16; + } case 2: // (An) - return ReadWord(A[reg].s32); + { + Register* A_ptr_reg = A + reg; + return ReadWord(A_ptr_reg->s32); + } case 3: // (An)+ - value = ReadWord(A[reg].s32); - return value; + { + Register* A_ptr_reg = A + reg; + value = ReadWord(A_ptr_reg->s32); + return value; + } case 4: // -(An) - value = ReadWord(A[reg].s32 - 2); - return value; + { + + Register* A_ptr_reg = A + reg; + value = ReadWord(A_ptr_reg->s32 - 2); + return value; + } case 5: // (d16,An) - value = ReadWord((A[reg].s32 + ReadOpWord(PC))); - return value; + { + Register* A_ptr_reg = A + reg; + value = ReadWord((A_ptr_reg->s32 + ReadOpWord(PC))); + return value; + } case 6: // (d8,An,Xn) - return ReadWord(A[reg].s32 + PeekIndex()); + { + Register* A_ptr_reg = A + reg; + return ReadWord(A_ptr_reg->s32 + PeekIndex()); + } case 7: switch (reg) { @@ -413,20 +452,38 @@ namespace cpu.m68000 case 0: // Dn return D[reg].s32; case 1: // An - return A[reg].s32; + { + Register* A_ptr_reg = A + reg; + return A_ptr_reg->s32; + } case 2: // (An) - return ReadLong(A[reg].s32); + { + Register* A_ptr_reg = A + reg; + return ReadLong(A_ptr_reg->s32); + } case 3: // (An)+ - value = ReadLong(A[reg].s32); - return value; + { + Register* A_ptr_reg = A + reg; + value = ReadLong(A_ptr_reg->s32); + return value; + } case 4: // -(An) - value = ReadLong(A[reg].s32 - 4); - return value; + { + Register* A_ptr_reg = A + reg; + value = ReadLong(A_ptr_reg->s32 - 4); + return value; + } case 5: // (d16,An) - value = ReadLong((A[reg].s32 + ReadOpWord(PC))); - return value; + { + Register* A_ptr_reg = A + reg; + value = ReadLong((A_ptr_reg->s32 + ReadOpWord(PC))); + return value; + } case 6: // (d8,An,Xn) - return ReadLong(A[reg].s32 + PeekIndex()); + { + Register* A_ptr_reg = A + reg; + return ReadLong(A_ptr_reg->s32 + PeekIndex()); + } case 7: switch (reg) { @@ -458,11 +515,11 @@ namespace cpu.m68000 { case 0: throw new Exception("Invalid addressing mode!"); // Dn case 1: throw new Exception("Invalid addressing mode!"); // An - case 2: return A[reg].s32; // (An) - case 3: return A[reg].s32; // (An)+ - case 4: return A[reg].s32; // -(An) - case 5: addr = A[reg].s32 + ReadOpWord(PC); PC += 2; return addr; // (d16,An) - case 6: return A[reg].s32 + GetIndex(); // (d8,An,Xn) + case 2: return (A + reg)->s32; // (An) + case 3: return (A + reg)->s32; // (An)+ + case 4: return (A + reg)->s32; // -(An) + case 5: addr = (A + reg)->s32 + ReadOpWord(PC); PC += 2; return addr; // (d16,An) + case 6: return (A + reg)->s32 + GetIndex(); // (d8,An,Xn) case 7: switch (reg) { @@ -486,24 +543,24 @@ namespace cpu.m68000 // D[reg].s8 = value; // return; // case 0x01: // An - // A[reg].s32 = value; + // A_ptr_reg->s32 = value; // return; // case 0x02: // (An) - // WriteByte(A[reg].s32, value); + // WriteByte(A_ptr_reg->s32, value); // return; // case 0x03: // (An)+ - // WriteByte(A[reg].s32, value); - // A[reg].s32 += reg == 7 ? 2 : 1; + // WriteByte(A_ptr_reg->s32, value); + // A_ptr_reg->s32 += reg == 7 ? 2 : 1; // return; // case 0x04: // -(An) - // A[reg].s32 -= reg == 7 ? 2 : 1; - // WriteByte(A[reg].s32, value); + // A_ptr_reg->s32 -= reg == 7 ? 2 : 1; + // WriteByte(A_ptr_reg->s32, value); // return; // case 0x05: // (d16,An) - // WriteByte(A[reg].s32 + ReadOpWord(PC), value); PC += 2; + // WriteByte(A_ptr_reg->s32 + ReadOpWord(PC), value); PC += 2; // return; // case 0x06: // (d8,An,Xn) - // WriteByte(A[reg].s32 + GetIndex(), value); + // WriteByte(A_ptr_reg->s32 + GetIndex(), value); // return; // case 0x07: // switch (reg) @@ -542,14 +599,14 @@ namespace cpu.m68000 return; case 0x03: // (An)+ { - Register* ptr = &A[reg]; + Register* ptr = A + reg; WriteByte(ptr->s32, value); ptr->s32 += reg == 7 ? 2 : 1; } return; case 0x04: // -(An) { - Register* ptr = &A[reg]; + Register* ptr = A + reg; ptr->s32 -= reg == 7 ? 2 : 1; WriteByte(ptr->s32, value); } @@ -590,24 +647,24 @@ namespace cpu.m68000 // D[reg].s16 = value; // return; // case 0x01: // An - // A[reg].s32 = value; + // A_ptr_reg->s32 = value; // return; // case 0x02: // (An) - // WriteWord(A[reg].s32, value); + // WriteWord(A_ptr_reg->s32, value); // return; // case 0x03: // (An)+ - // WriteWord(A[reg].s32, value); - // A[reg].s32 += 2; + // WriteWord(A_ptr_reg->s32, value); + // A_ptr_reg->s32 += 2; // return; // case 0x04: // -(An) - // A[reg].s32 -= 2; - // WriteWord(A[reg].s32, value); + // A_ptr_reg->s32 -= 2; + // WriteWord(A_ptr_reg->s32, value); // return; // case 0x05: // (d16,An) - // WriteWord(A[reg].s32 + ReadOpWord(PC), value); PC += 2; + // WriteWord(A_ptr_reg->s32 + ReadOpWord(PC), value); PC += 2; // return; // case 0x06: // (d8,An,Xn) - // WriteWord(A[reg].s32 + GetIndex(), value); + // WriteWord(A_ptr_reg->s32 + GetIndex(), value); // return; // case 0x07: // switch (reg) @@ -647,14 +704,14 @@ namespace cpu.m68000 return; case 0x03: // (An)+ { - Register* ptr = &A[reg]; + Register* ptr = A + reg; WriteWord(ptr->s32, value); ptr->s32 += 2; } return; case 0x04: // -(An) { - Register* ptr = &A[reg]; + Register* ptr = A + reg; ptr->s32 -= 2; WriteWord(ptr->s32, value); } @@ -702,14 +759,14 @@ namespace cpu.m68000 return; case 0x03: // (An)+ { - Register* ptr = &A[reg]; + Register* ptr = A + reg; WriteLong(ptr->s32, value); ptr->s32 += 4; } return; case 0x04: // -(An) { - Register* ptr = &A[reg]; + Register* ptr = A + reg; ptr->s32 -= 4; WriteLong(ptr->s32, value); } @@ -766,7 +823,7 @@ namespace cpu.m68000 if (da == 0) indexReg *= size == 0 ? D[reg].s16 : D[reg].s32; else - indexReg *= size == 0 ? A[reg].s16 : A[reg].s32; + indexReg *= size == 0 ? (A + reg)->s16 : (A + reg)->s32; return displacement + indexReg; } @@ -794,7 +851,10 @@ namespace cpu.m68000 if (da == 0) indexReg *= size == 0 ? D[reg].s16 : D[reg].s32; else - indexReg *= size == 0 ? A[reg].s16 : A[reg].s32; + { + Register* A_ptr_reg = A + reg; + indexReg *= size == 0 ? A_ptr_reg->s16 : A_ptr_reg->s32; + } return displacement + indexReg; }